https://github.com/mustartt created https://github.com/llvm/llvm-project/pull/133617
https://reviews.llvm.org/D124060 >From d10bfa59ba468d1f3159aad66b532e4be0e56831 Mon Sep 17 00:00:00 2001 From: Henry Jiang <henry.jia...@ibm.com> Date: Sun, 30 Mar 2025 00:23:10 -0400 Subject: [PATCH] Enable indiviual crbits tracking at O2 --- clang/lib/Basic/Targets/PPC.cpp | 5 -- llvm/lib/Target/PowerPC/PPC.td | 82 ++++++++++---------- llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 9 +++ llvm/lib/Target/PowerPC/PPCSubtarget.h | 1 + llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 7 -- 5 files changed, 53 insertions(+), 51 deletions(-) diff --git a/clang/lib/Basic/Targets/PPC.cpp b/clang/lib/Basic/Targets/PPC.cpp index 425ad68bb9098..61d567892b498 100644 --- a/clang/lib/Basic/Targets/PPC.cpp +++ b/clang/lib/Basic/Targets/PPC.cpp @@ -559,11 +559,6 @@ bool PPCTargetInfo::initFeatureMap( .Case("pwr9", true) .Case("pwr8", true) .Default(false); - Features["crbits"] = llvm::StringSwitch<bool>(CPU) - .Case("ppc64le", true) - .Case("pwr9", true) - .Case("pwr8", true) - .Default(false); Features["vsx"] = llvm::StringSwitch<bool>(CPU) .Case("ppc64le", true) .Case("pwr9", true) diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td index 39da428461393..9f0f271b619c7 100644 --- a/llvm/lib/Target/PowerPC/PPC.td +++ b/llvm/lib/Target/PowerPC/PPC.td @@ -74,7 +74,7 @@ def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true", // Specify if we should store and manipulate i1 values in the individual // condition register bits. -def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true", +def FeatureCRBits : SubtargetFeature<"crbits", "HasCRBits", "true", "Use condition-register bits individually">; def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true", "Enable classic FPU instructions", @@ -390,6 +390,7 @@ def ProcessorFeatures { FeatureFPCVT, FeatureISEL, FeaturePOPCNTD, + FeatureCRBits, FeatureCMPB, FeatureLDBRX, Feature64Bit, @@ -577,79 +578,82 @@ include "GISel/PPCRegisterBanks.td" // def : Processor<"generic", G3Itineraries, [Directive32, FeatureHardFloat, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, FeatureICBT, FeatureBookE, - FeatureMSYNC, FeatureMFTB]>; + FeatureMSYNC, FeatureMFTB, + FeatureCRBits]>; def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL, FeatureFRES, FeatureFRSQRTE, FeatureICBT, FeatureBookE, - FeatureMSYNC, FeatureMFTB]>; -def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU]>; + FeatureMSYNC, FeatureMFTB, + FeatureCRBits]>; +def : Processor<"601", G3Itineraries, [Directive601, FeatureFPU, + FeatureCRBits]>; def : Processor<"602", G3Itineraries, [Directive602, FeatureFPU, - FeatureMFTB]>; -def : Processor<"603", G3Itineraries, [Directive603, - FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; -def : Processor<"603e", G3Itineraries, [Directive603, - FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; +def : Processor<"603", G3Itineraries, [Directive603, FeatureFRES, + FeatureFRSQRTE, FeatureMFTB, + FeatureCRBits]>; +def : Processor<"603e", G3Itineraries, [Directive603, FeatureFRES, + FeatureFRSQRTE, FeatureMFTB, + FeatureCRBits]>; def : Processor<"603ev", G3Itineraries, [Directive603, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"604", G3Itineraries, [Directive604, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"604e", G3Itineraries, [Directive604, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"620", G3Itineraries, [Directive620, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"750", G4Itineraries, [Directive750, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"g3", G3Itineraries, [Directive750, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : ProcessorModel<"970", G5Model, [Directive970, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : ProcessorModel<"g5", G5Model, [Directive970, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX, FeatureFRES, FeatureFRSQRTE, Feature64Bit /*, Feature64BitRegs */, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, FeatureCRBits]>; def : ProcessorModel<"e500", PPCE500Model, - [DirectiveE500, - FeatureICBT, FeatureBookE, - FeatureISEL, FeatureMFTB, FeatureMSYNC, FeatureSPE]>; + [DirectiveE500, FeatureICBT, FeatureBookE, + FeatureISEL, FeatureMFTB, FeatureMSYNC, + FeatureSPE, FeatureCRBits]>; def : ProcessorModel<"e500mc", PPCE500mcModel, [DirectiveE500mc, FeatureSTFIWX, FeatureICBT, FeatureBookE, - FeatureISEL, FeatureMFTB]>; + FeatureISEL, FeatureMFTB, FeatureCRBits]>; def : ProcessorModel<"e5500", PPCE5500Model, [DirectiveE5500, FeatureMFOCRF, Feature64Bit, FeatureSTFIWX, FeatureICBT, FeatureBookE, - FeatureISEL, FeatureMFTB]>; + FeatureISEL, FeatureMFTB, FeatureCRBits]>; def : ProcessorModel<"a2", PPCA2Model, [DirectiveA2, FeatureICBT, FeatureBookE, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, @@ -658,41 +662,41 @@ def : ProcessorModel<"a2", PPCA2Model, FeatureFPRND, FeatureFPCVT, FeatureISEL, FeatureSlowPOPCNTD, FeatureCMPB, FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */, FeatureMFTB, - FeatureISA2_06]>; + FeatureISA2_06, FeatureCRBits]>; def : ProcessorModel<"pwr3", G5Model, [DirectivePwr3, FeatureAltivec, FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF, - FeatureSTFIWX, Feature64Bit]>; + FeatureSTFIWX, Feature64Bit, FeatureCRBits]>; def : ProcessorModel<"pwr4", G5Model, [DirectivePwr4, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, - FeatureSTFIWX, Feature64Bit, FeatureMFTB]>; + FeatureSTFIWX, Feature64Bit, FeatureMFTB, FeatureCRBits]>; def : ProcessorModel<"pwr5", G5Model, [DirectivePwr5, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX, Feature64Bit, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, FeatureCRBits]>; def : ProcessorModel<"pwr5x", G5Model, [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureSTFIWX, FeatureFPRND, Feature64Bit, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, FeatureCRBits]>; def : ProcessorModel<"pwr6", G5Model, [DirectivePwr6, FeatureAltivec, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, FeatureFPRND, Feature64Bit /*, Feature64BitRegs */, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, FeatureCRBits]>; def : ProcessorModel<"pwr6x", G5Model, [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB, FeatureFPRND, Feature64Bit, - FeatureMFTB, DeprecatedDST]>; + FeatureMFTB, DeprecatedDST, FeatureCRBits]>; def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>; def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>; def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>; @@ -702,15 +706,15 @@ def : ProcessorModel<"pwr11", P10Model, ProcessorFeatures.P11Features>; def : ProcessorModel<"future", NoSchedModel, ProcessorFeatures.FutureFeatures>; def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : ProcessorModel<"ppc64", G5Model, [Directive64, FeatureAltivec, FeatureMFOCRF, FeatureFSqrt, FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX, Feature64Bit /*, Feature64BitRegs */, - FeatureMFTB]>; + FeatureMFTB, FeatureCRBits]>; def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.P8Features>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp index 75a0272af7c31..746358d273dff 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -26,6 +26,7 @@ #include "llvm/IR/GlobalValue.h" #include "llvm/IR/GlobalVariable.h" #include "llvm/MC/TargetRegistry.h" +#include "llvm/Support/CodeGen.h" #include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetMachine.h" #include "llvm/TargetParser/PPCTargetParser.h" @@ -149,6 +150,14 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, false); } +bool PPCSubtarget::useCRBits() const { + if (!hasCRBits()) + return false; + if (CPUDirective >= PPC::DIR_PWR8) + return true; + return TM.getOptLevel() >= CodeGenOptLevel::Default; +} + bool PPCSubtarget::enableMachineScheduler() const { return true; } bool PPCSubtarget::enableMachinePipeliner() const { diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h index 9a97d1aa4dab0..fcb17d71e8e7c 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -209,6 +209,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo { } POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; } + bool useCRBits() const; const Triple &getTargetTriple() const { return TargetTriple; } diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 5ee13a92cf993..fa611f831a09a 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -210,13 +210,6 @@ static std::string computeFSAdditions(StringRef FS, CodeGenOptLevel OL, FullFS = "+64bit"; } - if (OL >= CodeGenOptLevel::Default) { - if (!FullFS.empty()) - FullFS = "+crbits," + FullFS; - else - FullFS = "+crbits"; - } - if (OL != CodeGenOptLevel::None) { if (!FullFS.empty()) FullFS = "+invariant-function-descriptors," + FullFS; _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
