from:"Gong LingQin via Phabricator via cfe\-commits"

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-10-27 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D136906

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/module.modulemap
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/larchintrin.h
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+declare void @llvm.loongarch.dbar(i32)
+
+define void @foo() nounwind {
+; CHECK-LABEL: foo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:dbar 0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.dbar(i32 0)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -0,0 +1,10 @@
+; RUN: not llc --mtriple=loongarch64 --disable-verify < %s 2>&1 | FileCheck %s
+
+define void @foo(i32 %x) nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' must be a constant integer
+entry:
+  call void @llvm.loongarch.dbar(i32 %x)
+  ret void
+}
+
+declare void @llvm.loongarch.dbar(i32)
Index: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
===
--- llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -35,6 +35,8 @@
   SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3>
 ]>;
 
+def SDT_LoongArchDBAR : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
+
 // TODO: Add LoongArch specific DAG Nodes
 // Target-independent nodes, but with target-specific formats.
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
@@ -63,6 +65,8 @@
 def loongarch_bitrev_w : SDNode<"LoongArchISD::BITREV_W", SDTUnaryOp>;
 def loongarch_clzw : SDNode<"LoongArchISD::CLZ_W", SDTIntBitCountUnaryOp>;
 def loongarch_ctzw : SDNode<"LoongArchISD::CTZ_W", SDTIntBitCountUnaryOp>;
+def loongarch_dbar : SDNode<"LoongArchISD::DBAR", SDT_LoongArchDBAR,
+ [SDNPHasChain, SDNPSideEffect]>;
 
 //===--===//
 // Operand and SDNode transformation definitions.
@@ -130,7 +134,8 @@
   let ParserMatchClass = UImmAsmOperand<14>;
 }
 
-def uimm15 : Operand {
+def uimm15 : Operand,
+ ImmLeaf (Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<15>;
 }
 
@@ -1261,6 +1266,16 @@
   (PseudoAtomicLoadXor32 GPR:$incr, GPR:$addr)>;
 } // Predicates = [IsLA32]
 
+/// Intrinsics
+
+let Predicates = [IsLA32] in {
+def : Pat<(int_loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+} // Predicates = [IsLA32]
+
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+} // Predicates = [IsLA64]
+
 /// Other pseudo-instructions
 
 // Pessimistically assume the stack pointer will be clobbered
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.h
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -56,6 +56,9 @@
   REVB_2W,
   BITREV_4B,
   BITREV_W,
+
+  // Intrinsic operations
+  DBAR,
 };
 } // end namespace LoongArchISD
 
@@ -162,6 +165,7 @@
   SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArch

[PATCH] D139915: [Clang][LoongArch] Add intrinsic for asrtle, asrtgt, lddir, ldpte and cpucfg

2022-12-20 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.h:91
   IOCSRWR_D,
+
+  CPUCFG,

SixWeining wrote:
> Better to leave some comment like line 82?
Thanks, I'll add comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139915/new/

https://reviews.llvm.org/D139915

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D139915: [Clang][LoongArch] Add intrinsic for asrtle, asrtgt, lddir, ldpte and cpucfg

2022-12-20 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 484465.
gonglingqin added a comment.

Add comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139915/new/

https://reviews.llvm.org/D139915

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -15,6 +15,7 @@
 declare void @llvm.loongarch.iocsrwr.b(i32, i32)
 declare void @llvm.loongarch.iocsrwr.h(i32, i32)
 declare void @llvm.loongarch.iocsrwr.w(i32, i32)
+declare i32 @llvm.loongarch.cpucfg(i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -145,3 +146,13 @@
   tail call void @llvm.loongarch.iocsrwr.w(i32 %a, i32 %b)
   ret void
 }
+
+define i32 @cpucfg(i32 %a) {
+; CHECK-LABEL: cpucfg:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cpucfg $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.cpucfg(i32 %a)
+  ret i32 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -14,6 +14,10 @@
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i64)
+declare void @llvm.loongarch.ldpte.d(i64, i64)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -136,3 +140,43 @@
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtle_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:asrtle.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtgt_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:asrtgt.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i64 @lddir_d(i64 %a) {
+; CHECK-LABEL: lddir_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lddir $a0, $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i64 1)
+  ret i64 %0
+}
+
+define void @ldpte_d(i64 %a) {
+; CHECK-LABEL: ldpte_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ldpte $a0, 1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.ldpte.d(i64 %a, i64 1)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -13,6 +13,10 @@
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i32)
+declare void @llvm.loongarch.ldpte.d(i64, i32)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
@@ -104,3 +108,31 @@
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtle.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtgt.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i64 @lddir_d(i64 %a) {
+; CHECK: llvm.loongarch.lddir.d requires target: loongarch64
+entry:
+  %0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i32 1)
+  ret i64 %0
+}
+
+define void @ldpte_d(i64 %a) {
+; CHECK: llvm.loongarch.ldpte.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.ldpte.d(i64 %a, i32 1)
+  ret void
+}
In

[PATCH] D139987: [Clang][LoongArch] Add intrinsic for rdtime_d, rdtimeh_w and rdtimel_w

2022-12-20 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: clang/lib/Headers/larchintrin.h:17-20
+typedef struct drdtime {
+  unsigned long dvalue;
+  unsigned long dtimeid;
+} __drdtime_t;

SixWeining wrote:
> Should be moved into the belowing `#if __loongarch_grlen == 64`.
Thanks. I will modify it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139987/new/

https://reviews.llvm.org/D139987

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D139987: [Clang][LoongArch] Add intrinsic for rdtime_d, rdtimeh_w and rdtimel_w

2022-12-20 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 484466.
gonglingqin added a comment.

Address @SixWeining's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139987/new/

https://reviews.llvm.org/D139987

Files:
  clang/lib/Headers/larchintrin.h
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c

Index: clang/test/CodeGen/LoongArch/intrinsic-la64.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -316,3 +316,23 @@
   __iocsrwr_d(a, b);
   __builtin_loongarch_iocsrwr_d(a, b);
 }
+
+// CHECK-LABEL: @rdtime_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect "rdtime.d $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// CHECK-NEXT:ret void
+//
+void rdtime_d() {
+  __rdtime_d();
+}
+
+// CHECK-LABEL: @rdtime(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// CHECK-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void rdtime() {
+  __rdtimeh_w();
+  __rdtimel_w();
+}
Index: clang/test/CodeGen/LoongArch/intrinsic-la32.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la32.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la32.c
@@ -154,3 +154,14 @@
   __iocsrwr_w(a, b);
   __builtin_loongarch_iocsrwr_w(a, b);
 }
+
+// LA32-LABEL: @rdtime(
+// LA32-NEXT:  entry:
+// LA32-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// LA32-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// LA32-NEXT:ret void
+//
+void rdtime() {
+  __rdtimeh_w();
+  __rdtimel_w();
+}
Index: clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
@@ -95,3 +95,7 @@
 void iocsrwr_d(unsigned long int a, unsigned int b) {
   __builtin_loongarch_iocsrwr_d(a, b); // expected-error {{this builtin requires target: loongarch64}}
 }
+
+void rdtime_d() {
+  __rdtime_d(); // expected-error {{call to undeclared function '__rdtime_d'}}
+}
Index: clang/lib/Headers/larchintrin.h
===
--- clang/lib/Headers/larchintrin.h
+++ clang/lib/Headers/larchintrin.h
@@ -14,6 +14,46 @@
 extern "C" {
 #endif
 
+typedef struct rdtime {
+  unsigned int value;
+  unsigned int timeid;
+} __rdtime_t;
+
+#if __loongarch_grlen == 64
+typedef struct drdtime {
+  unsigned long dvalue;
+  unsigned long dtimeid;
+} __drdtime_t;
+
+extern __inline __drdtime_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__rdtime_d(void) {
+  __drdtime_t __drdtime;
+  __asm__ volatile(
+  "rdtime.d %[val], %[tid]\n\t"
+  : [val] "=&r"(__drdtime.dvalue), [tid] "=&r"(__drdtime.dtimeid));
+  return __drdtime;
+}
+#endif
+
+extern __inline __rdtime_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__rdtimeh_w(void) {
+  __rdtime_t __rdtime;
+  __asm__ volatile("rdtimeh.w %[val], %[tid]\n\t"
+   : [val] "=&r"(__rdtime.value), [tid] "=&r"(__rdtime.timeid));
+  return __rdtime;
+}
+
+extern __inline __rdtime_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__rdtimel_w(void) {
+  __rdtime_t __rdtime;
+  __asm__ volatile("rdtimel.w %[val], %[tid]\n\t"
+   : [val] "=&r"(__rdtime.value), [tid] "=&r"(__rdtime.timeid));
+  return __rdtime;
+}
+
 #if __loongarch_grlen == 64
 extern __inline int
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D139915: [Clang][LoongArch] Add intrinsic for asrtle, asrtgt, lddir, ldpte and cpucfg

2022-12-22 Thread Gong LingQin via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGaeb8f911b169: [Clang][LoongArch] Add intrinsic for asrtle, 
asrtgt, lddir, ldpte and cpucfg (authored by gonglingqin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139915/new/

https://reviews.llvm.org/D139915

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -15,6 +15,7 @@
 declare void @llvm.loongarch.iocsrwr.b(i32, i32)
 declare void @llvm.loongarch.iocsrwr.h(i32, i32)
 declare void @llvm.loongarch.iocsrwr.w(i32, i32)
+declare i32 @llvm.loongarch.cpucfg(i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -145,3 +146,13 @@
   tail call void @llvm.loongarch.iocsrwr.w(i32 %a, i32 %b)
   ret void
 }
+
+define i32 @cpucfg(i32 %a) {
+; CHECK-LABEL: cpucfg:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cpucfg $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.cpucfg(i32 %a)
+  ret i32 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -14,6 +14,10 @@
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i64)
+declare void @llvm.loongarch.ldpte.d(i64, i64)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -136,3 +140,43 @@
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtle_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:asrtle.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtgt_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:asrtgt.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i64 @lddir_d(i64 %a) {
+; CHECK-LABEL: lddir_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lddir $a0, $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i64 1)
+  ret i64 %0
+}
+
+define void @ldpte_d(i64 %a) {
+; CHECK-LABEL: ldpte_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ldpte $a0, 1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.ldpte.d(i64 %a, i64 1)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -13,6 +13,10 @@
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i32)
+declare void @llvm.loongarch.ldpte.d(i64, i32)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
@@ -104,3 +108,31 @@
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtle.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtgt.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i64 @lddir_d(i64 %a) {
+; CHECK: llvm.loongarch.lddir.d requires target: loongarch64
+entry:
+  %0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i32 1)
+  ret i64 %0
+}
+
+define void @ldpte_d(i64 %a) {
+; CHECK: llvm.loongarch.l

[PATCH] D139987: [Clang][LoongArch] Add intrinsic for rdtime_d, rdtimeh_w and rdtimel_w

2022-12-22 Thread Gong LingQin via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe726703c27c4: [Clang][LoongArch] Add intrinsic for rdtime_d, 
rdtimeh_w and rdtimel_w (authored by gonglingqin).

Changed prior to commit:
  https://reviews.llvm.org/D139987?vs=484466&id=484792#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139987/new/

https://reviews.llvm.org/D139987

Files:
  clang/lib/Headers/larchintrin.h
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c

Index: clang/test/CodeGen/LoongArch/intrinsic-la64.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -373,3 +373,23 @@
   unsigned int c = __builtin_loongarch_cpucfg(a);
   return 0;
 }
+
+// CHECK-LABEL: @rdtime_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect "rdtime.d $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// CHECK-NEXT:ret void
+//
+void rdtime_d() {
+  __rdtime_d();
+}
+
+// CHECK-LABEL: @rdtime(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// CHECK-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void rdtime() {
+  __rdtimeh_w();
+  __rdtimel_w();
+}
Index: clang/test/CodeGen/LoongArch/intrinsic-la32.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la32.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la32.c
@@ -166,3 +166,14 @@
   unsigned int c = __builtin_loongarch_cpucfg(a);
   return 0;
 }
+
+// LA32-LABEL: @rdtime(
+// LA32-NEXT:  entry:
+// LA32-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// LA32-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// LA32-NEXT:ret void
+//
+void rdtime() {
+  __rdtimeh_w();
+  __rdtimel_w();
+}
Index: clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
@@ -111,3 +111,7 @@
 void ldpte_d(long int a, int b) {
   __builtin_loongarch_ldpte_d(a, 1); // expected-error {{this builtin requires target: loongarch64}}
 }
+
+void rdtime_d() {
+  __rdtime_d(); // expected-error {{call to undeclared function '__rdtime_d'}}
+}
Index: clang/lib/Headers/larchintrin.h
===
--- clang/lib/Headers/larchintrin.h
+++ clang/lib/Headers/larchintrin.h
@@ -14,6 +14,46 @@
 extern "C" {
 #endif
 
+typedef struct rdtime {
+  unsigned int value;
+  unsigned int timeid;
+} __rdtime_t;
+
+#if __loongarch_grlen == 64
+typedef struct drdtime {
+  unsigned long dvalue;
+  unsigned long dtimeid;
+} __drdtime_t;
+
+extern __inline __drdtime_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__rdtime_d(void) {
+  __drdtime_t __drdtime;
+  __asm__ volatile(
+  "rdtime.d %[val], %[tid]\n\t"
+  : [val] "=&r"(__drdtime.dvalue), [tid] "=&r"(__drdtime.dtimeid));
+  return __drdtime;
+}
+#endif
+
+extern __inline __rdtime_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__rdtimeh_w(void) {
+  __rdtime_t __rdtime;
+  __asm__ volatile("rdtimeh.w %[val], %[tid]\n\t"
+   : [val] "=&r"(__rdtime.value), [tid] "=&r"(__rdtime.timeid));
+  return __rdtime;
+}
+
+extern __inline __rdtime_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__rdtimel_w(void) {
+  __rdtime_t __rdtime;
+  __asm__ volatile("rdtimel.w %[val], %[tid]\n\t"
+   : [val] "=&r"(__rdtime.value), [tid] "=&r"(__rdtime.timeid));
+  return __rdtime;
+}
+
 #if __loongarch_grlen == 64
 extern __inline int
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137316: [Clang][LoongArch] Implement __builtin_loongarch_crc_w_d_w builtin and add diagnostics

2022-11-03 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
Herald added a subscriber: hiraditya.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

This patch adds support to prevent __builtin_loongarch_crc_w_d_w from compiling
on loongarch32 in the front end and adds diagnostics accordingly.

Reference: 
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/loongarch/larchintrin.h#L175-L184

Depends on D136906 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137316

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+
+define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_d_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -0,0 +1,10 @@
+; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
+
+declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+
+define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.d.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
===
--- llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -55,6 +55,8 @@
 def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotr_w : SDNode<"LoongArchISD::ROTR_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotl_w : SDNode<"LoongArchISD::ROTL_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crc_w_d_w
+: SDNode<"LoongArchISD::CRC_W_D_W", SDT_LoongArchIntBinOpW>;
 def loongarch_bstrins
 : SDNode<"LoongArchISD::BSTRINS", SDT_LoongArchBStrIns>;
 def loongarch_bstrpick
@@ -1307,6 +1309,9 @@
 
 let Predicates = [IsLA64] in {
 def : Pat<(loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+
+// CRC Check Instructions
+def : PatGprGpr;
 } // Predicates = [IsLA64]
 
 /// Other pseudo-instructions
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.h
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -59,6 +59,9 @@
 
   // Intrinsic operations
   DBAR,
+
+  // CRC check operations
+  CRC_W_D_W
 };
 } // end namespace LoongArchISD
 
@@ -177,6 +180,7 @@
   SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -89,6 +89,7 @@
 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
 setOperationAction(ISD::CTLZ, MVT::i32, Custom);
 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
+setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom);
 if (Subtarget.hasBasicF() && !Subtarget.hasBasicD())
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
 if (Subtarget.hasBasicF())
@@ -113,6 +114,7 @@
 setOperationAction(ISD::BIT

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-11-06 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsLoongArch.td:39
+
+def int_loongarch_dbar : Intrinsic<[], [llvm_i32_ty], []>;
 } // TargetPrefix = "loongarch"

SixWeining wrote:
> Seems this arg is unnecessary because the defalut value is `[]`.
Thanks, I will modify it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136906/new/

https://reviews.llvm.org/D136906

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-11-06 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 473561.
gonglingqin added a comment.

Address @SixWeining's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136906/new/

https://reviews.llvm.org/D136906

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/module.modulemap
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/larchintrin.h
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+declare void @llvm.loongarch.dbar(i32)
+
+define void @foo() nounwind {
+; CHECK-LABEL: foo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:dbar 0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.dbar(i32 0)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -0,0 +1,10 @@
+; RUN: not llc --mtriple=loongarch64 --disable-verify < %s 2>&1 | FileCheck %s
+
+define void @foo(i32 %x) nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' must be a constant integer
+entry:
+  call void @llvm.loongarch.dbar(i32 %x)
+  ret void
+}
+
+declare void @llvm.loongarch.dbar(i32)
Index: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
===
--- llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -35,6 +35,8 @@
   SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3>
 ]>;
 
+def SDT_LoongArchDBAR : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
+
 // TODO: Add LoongArch specific DAG Nodes
 // Target-independent nodes, but with target-specific formats.
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
@@ -63,6 +65,8 @@
 def loongarch_bitrev_w : SDNode<"LoongArchISD::BITREV_W", SDTUnaryOp>;
 def loongarch_clzw : SDNode<"LoongArchISD::CLZ_W", SDTIntBitCountUnaryOp>;
 def loongarch_ctzw : SDNode<"LoongArchISD::CTZ_W", SDTIntBitCountUnaryOp>;
+def loongarch_dbar : SDNode<"LoongArchISD::DBAR", SDT_LoongArchDBAR,
+ [SDNPHasChain, SDNPSideEffect]>;
 
 //===--===//
 // Operand and SDNode transformation definitions.
@@ -130,7 +134,8 @@
   let ParserMatchClass = UImmAsmOperand<14>;
 }
 
-def uimm15 : Operand {
+def uimm15 : Operand,
+ ImmLeaf (Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<15>;
 }
 
@@ -1261,6 +1266,16 @@
   (PseudoAtomicLoadXor32 GPR:$incr, GPR:$addr)>;
 } // Predicates = [IsLA32]
 
+/// Intrinsics
+
+let Predicates = [IsLA32] in {
+def : Pat<(int_loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+} // Predicates = [IsLA32]
+
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+} // Predicates = [IsLA64]
+
 /// Other pseudo-instructions
 
 // Pessimistically assume the stack pointer will be clobbered
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.h
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -56,6 +56,9 @@
   REVB_2W,
   BITREV_4B,
   BITREV_W,
+
+  // Intrinsic operations
+  DBAR,
 };
 } // end namespace LoongArchISD
 
@@ -162,6 +165,7 @@
   SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -87,6 +87,7 @@
 setOperationAction(ISD::ROTL, MVT::i32, Custom);
 setOperationAction(ISD::CTTZ, MVT::i32, Custom);

[PATCH] D137316: [Clang][LoongArch] Implement __builtin_loongarch_crc_w_d_w builtin and add diagnostics

2022-11-06 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: llvm/include/llvm/IR/IntrinsicsLoongArch.td:54
+def int_loongarch_crc_w_d_w : Intrinsic<[llvm_i32_ty],
+[llvm_i64_ty, llvm_i32_ty], []>;
 } // TargetPrefix = "loongarch"

SixWeining wrote:
> Unnecessary.
Thanks, I will modify it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137316/new/

https://reviews.llvm.org/D137316

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137316: [Clang][LoongArch] Implement __builtin_loongarch_crc_w_d_w builtin and add diagnostics

2022-11-06 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 473564.
gonglingqin added a comment.

Address @SixWeining's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137316/new/

https://reviews.llvm.org/D137316

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+
+define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_d_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -0,0 +1,10 @@
+; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
+
+declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+
+define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.d.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
===
--- llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -55,6 +55,8 @@
 def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotr_w : SDNode<"LoongArchISD::ROTR_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotl_w : SDNode<"LoongArchISD::ROTL_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crc_w_d_w
+: SDNode<"LoongArchISD::CRC_W_D_W", SDT_LoongArchIntBinOpW>;
 def loongarch_bstrins
 : SDNode<"LoongArchISD::BSTRINS", SDT_LoongArchBStrIns>;
 def loongarch_bstrpick
@@ -1307,6 +1309,9 @@
 
 let Predicates = [IsLA64] in {
 def : Pat<(loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+
+// CRC Check Instructions
+def : PatGprGpr;
 } // Predicates = [IsLA64]
 
 /// Other pseudo-instructions
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.h
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -59,6 +59,9 @@
 
   // Intrinsic operations
   DBAR,
+
+  // CRC check operations
+  CRC_W_D_W
 };
 } // end namespace LoongArchISD
 
@@ -177,6 +180,7 @@
   SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -89,6 +89,7 @@
 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
 setOperationAction(ISD::CTLZ, MVT::i32, Custom);
 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
+setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom);
 if (Subtarget.hasBasicF() && !Subtarget.hasBasicD())
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
 if (Subtarget.hasBasicF())
@@ -113,6 +114,7 @@
 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
   } else {
 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
+setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
   }
 
   static const ISD::CondCode FPCCToExpand[] = {
@@ -209,6 +211,8 @@
 return lowerGlobalTLSAddress(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN:
 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
+

[PATCH] D137316: [Clang][LoongArch] Implement __builtin_loongarch_crc_w_d_w builtin and add diagnostics

2022-11-07 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: clang/lib/Basic/Targets/LoongArch.cpp:174
+const std::vector &FeaturesVec) const {
+
+  if (getTriple().getArch() == llvm::Triple::loongarch64)

SixWeining wrote:
> Delete blank line.
Thanks, I will delete it.



Comment at: clang/lib/Sema/SemaChecking.cpp:3677
+ CallExpr *TheCall) {
+
+  switch (BuiltinID) {

SixWeining wrote:
> Delete blank line.
Thanks, I will delete it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137316/new/

https://reviews.llvm.org/D137316

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137316: [Clang][LoongArch] Implement __builtin_loongarch_crc_w_d_w builtin and add diagnostics

2022-11-07 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 473620.
gonglingqin added a comment.

Delete blank line.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137316/new/

https://reviews.llvm.org/D137316

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+
+define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_d_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -0,0 +1,10 @@
+; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
+
+declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+
+define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.d.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
===
--- llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -55,6 +55,8 @@
 def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotr_w : SDNode<"LoongArchISD::ROTR_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotl_w : SDNode<"LoongArchISD::ROTL_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crc_w_d_w
+: SDNode<"LoongArchISD::CRC_W_D_W", SDT_LoongArchIntBinOpW>;
 def loongarch_bstrins
 : SDNode<"LoongArchISD::BSTRINS", SDT_LoongArchBStrIns>;
 def loongarch_bstrpick
@@ -1307,6 +1309,9 @@
 
 let Predicates = [IsLA64] in {
 def : Pat<(loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+
+// CRC Check Instructions
+def : PatGprGpr;
 } // Predicates = [IsLA64]
 
 /// Other pseudo-instructions
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.h
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -59,6 +59,9 @@
 
   // Intrinsic operations
   DBAR,
+
+  // CRC check operations
+  CRC_W_D_W
 };
 } // end namespace LoongArchISD
 
@@ -177,6 +180,7 @@
   SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -89,6 +89,7 @@
 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
 setOperationAction(ISD::CTLZ, MVT::i32, Custom);
 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
+setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom);
 if (Subtarget.hasBasicF() && !Subtarget.hasBasicD())
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
 if (Subtarget.hasBasicF())
@@ -113,6 +114,7 @@
 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
   } else {
 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
+setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
   }
 
   static const ISD::CondCode FPCCToExpand[] = {
@@ -209,6 +211,8 @@
 return lowerGlobalTLSAddress(Op, DAG);
   case ISD::INTRINSIC_WO_CHAIN:
 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
+  case ISD::I

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-11-08 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: llvm/test/CodeGen/LoongArch/intrinsic-error.ll:10
+
+declare void @llvm.loongarch.dbar(i32)

SixWeining wrote:
> It's better to add a test that immediate is out of range.
Thanks, I will add test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136906/new/

https://reviews.llvm.org/D136906

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-11-08 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 473909.
gonglingqin added a comment.

Add test cases to detect whether the immediate is out of range.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136906/new/

https://reviews.llvm.org/D136906

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/module.modulemap
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/larchintrin.h
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+declare void @llvm.loongarch.dbar(i32)
+
+define void @foo() nounwind {
+; CHECK-LABEL: foo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:dbar 0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.dbar(i32 0)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -0,0 +1,18 @@
+; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch64 --disable-verify < %s 2>&1 | FileCheck %s
+
+define void @dbar_not_constant(i32 %x) nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' must be a constant integer
+entry:
+  call void @llvm.loongarch.dbar(i32 %x)
+  ret void
+}
+
+define void @dbar_imm_out_of_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' out of range
+entry:
+  call void @llvm.loongarch.dbar(i32 32769)
+  ret void
+}
+
+declare void @llvm.loongarch.dbar(i32)
Index: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
===
--- llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -35,6 +35,8 @@
   SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3>
 ]>;
 
+def SDT_LoongArchDBAR : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
+
 // TODO: Add LoongArch specific DAG Nodes
 // Target-independent nodes, but with target-specific formats.
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
@@ -63,6 +65,8 @@
 def loongarch_bitrev_w : SDNode<"LoongArchISD::BITREV_W", SDTUnaryOp>;
 def loongarch_clzw : SDNode<"LoongArchISD::CLZ_W", SDTIntBitCountUnaryOp>;
 def loongarch_ctzw : SDNode<"LoongArchISD::CTZ_W", SDTIntBitCountUnaryOp>;
+def loongarch_dbar : SDNode<"LoongArchISD::DBAR", SDT_LoongArchDBAR,
+ [SDNPHasChain, SDNPSideEffect]>;
 
 //===--===//
 // Operand and SDNode transformation definitions.
@@ -130,7 +134,8 @@
   let ParserMatchClass = UImmAsmOperand<14>;
 }
 
-def uimm15 : Operand {
+def uimm15 : Operand,
+ ImmLeaf (Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<15>;
 }
 
@@ -1261,6 +1266,16 @@
   (PseudoAtomicLoadXor32 GPR:$incr, GPR:$addr)>;
 } // Predicates = [IsLA32]
 
+/// Intrinsics
+
+let Predicates = [IsLA32] in {
+def : Pat<(int_loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+} // Predicates = [IsLA32]
+
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+} // Predicates = [IsLA64]
+
 /// Other pseudo-instructions
 
 // Pessimistically assume the stack pointer will be clobbered
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.h
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -56,6 +56,9 @@
   REVB_2W,
   BITREV_4B,
   BITREV_W,
+
+  // Intrinsic operations
+  DBAR,
 };
 } // end namespace LoongArchISD
 
@@ -162,6 +165,7 @@
   SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
=

[PATCH] D136146: [Clang][LoongArch] Handle -march/-m{single,double,soft}-float/-mfpu options

2022-11-10 Thread Gong LingQin via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG135a9272a4c9: [Clang][LoongArch] Handle 
-march/-m{single,double,soft}-float/-mfpu options (authored by SixWeining, 
committed by gonglingqin).

Changed prior to commit:
  https://reviews.llvm.org/D136146?vs=474414&id=474471#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136146/new/

https://reviews.llvm.org/D136146

Files:
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Arch/LoongArch.cpp
  clang/lib/Driver/ToolChains/Arch/LoongArch.h
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/loongarch-default-features.c
  clang/test/Driver/loongarch-march-error.c
  clang/test/Driver/loongarch-march.c
  clang/test/Driver/loongarch-mdouble-float.c
  clang/test/Driver/loongarch-mfpu-error.c
  clang/test/Driver/loongarch-mfpu.c
  clang/test/Driver/loongarch-msingle-float.c
  clang/test/Driver/loongarch-msoft-float.c
  llvm/include/llvm/Support/LoongArchTargetParser.def
  llvm/include/llvm/Support/LoongArchTargetParser.h
  llvm/lib/Support/CMakeLists.txt
  llvm/lib/Support/LoongArchTargetParser.cpp

Index: llvm/lib/Support/LoongArchTargetParser.cpp
===
--- /dev/null
+++ llvm/lib/Support/LoongArchTargetParser.cpp
@@ -0,0 +1,53 @@
+//==-- LoongArch64TargetParser - Parser for LoongArch64 features --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements a target parser to recognise LoongArch hardware features
+// such as CPU/ARCH and extension names.
+//
+//===--===//
+
+#include "llvm/Support/LoongArchTargetParser.h"
+#include "llvm/ADT/StringSwitch.h"
+
+using namespace llvm;
+using namespace llvm::LoongArch;
+
+const FeatureInfo AllFeatures[] = {
+#define LOONGARCH_FEATURE(NAME, KIND) {NAME, KIND},
+#include "llvm/Support/LoongArchTargetParser.def"
+};
+
+const ArchInfo AllArchs[] = {
+#define LOONGARCH_ARCH(NAME, KIND, FEATURES)   \
+  {NAME, LoongArch::ArchKind::KIND, FEATURES},
+#include "llvm/Support/LoongArchTargetParser.def"
+};
+
+LoongArch::ArchKind LoongArch::parseArch(StringRef Arch) {
+  for (const auto A : AllArchs) {
+if (A.Name == Arch)
+  return A.Kind;
+  }
+
+  return LoongArch::ArchKind::AK_INVALID;
+}
+
+bool LoongArch::getArchFeatures(StringRef Arch,
+std::vector &Features) {
+  for (const auto A : AllArchs) {
+if (A.Name == Arch) {
+  for (const auto F : AllFeatures) {
+if ((A.Features & F.Kind) == F.Kind && F.Kind != FK_INVALID) {
+  Features.push_back(F.Name);
+}
+  }
+  return true;
+}
+  }
+  return false;
+}
Index: llvm/lib/Support/CMakeLists.txt
===
--- llvm/lib/Support/CMakeLists.txt
+++ llvm/lib/Support/CMakeLists.txt
@@ -187,6 +187,7 @@
   LineIterator.cpp
   Locale.cpp
   LockFileManager.cpp
+  LoongArchTargetParser.cpp
   LowLevelType.cpp
   ManagedStatic.cpp
   MathExtras.cpp
Index: llvm/include/llvm/Support/LoongArchTargetParser.h
===
--- /dev/null
+++ llvm/include/llvm/Support/LoongArchTargetParser.h
@@ -0,0 +1,74 @@
+//==-- LoongArch64TargetParser - Parser for LoongArch64 features --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// This file implements a target parser to recognise LoongArch hardware features
+// such as CPU/ARCH and extension names.
+//
+//===--===//
+
+#ifndef LLVM_SUPPORT_LOONGARCHTARGETPARSER_H
+#define LLVM_SUPPORT_LOONGARCHTARGETPARSER_H
+
+#include "llvm/ADT/Triple.h"
+#include 
+
+namespace llvm {
+class StringRef;
+
+namespace LoongArch {
+
+enum FeatureKind : uint32_t {
+  FK_INVALID = 0,
+  FK_NONE = 1,
+
+  // 64-bit ISA is available.
+  FK_64BIT = 1 << 1,
+
+  // Single-precision floating-point instructions are available.
+  FK_FP32 = 1 << 2,
+
+  // Double-precision floating-point instructions are available.
+  FK_FP64 = 1 << 3,
+
+  // Loongson SIMD Extension is available.
+  FK_LSX = 1 << 4,
+
+  // Loongson Advanced SIMD Extension is available.
+  FK_LASX = 1

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-11-10 Thread Gong LingQin via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG85f08c4197ae: [Clang][LoongArch] Implement 
__builtin_loongarch_dbar builtin (authored by gonglingqin).

Changed prior to commit:
  https://reviews.llvm.org/D136906?vs=473909&id=474473#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136906/new/

https://reviews.llvm.org/D136906

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/module.modulemap
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/larchintrin.h
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -0,0 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+declare void @llvm.loongarch.dbar(i32)
+
+define void @foo() nounwind {
+; CHECK-LABEL: foo:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:dbar 0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.dbar(i32 0)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -0,0 +1,18 @@
+; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch64 --disable-verify < %s 2>&1 | FileCheck %s
+
+define void @dbar_not_constant(i32 %x) nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' must be a constant integer
+entry:
+  call void @llvm.loongarch.dbar(i32 %x)
+  ret void
+}
+
+define void @dbar_imm_out_of_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' out of range
+entry:
+  call void @llvm.loongarch.dbar(i32 32769)
+  ret void
+}
+
+declare void @llvm.loongarch.dbar(i32)
Index: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
===
--- llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -35,6 +35,8 @@
   SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>, SDTCisSameAs<2, 3>
 ]>;
 
+def SDT_LoongArchDBAR : SDTypeProfile<0, 1, [SDTCisVT<0, GRLenVT>]>;
+
 // TODO: Add LoongArch specific DAG Nodes
 // Target-independent nodes, but with target-specific formats.
 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
@@ -63,6 +65,8 @@
 def loongarch_bitrev_w : SDNode<"LoongArchISD::BITREV_W", SDTUnaryOp>;
 def loongarch_clzw : SDNode<"LoongArchISD::CLZ_W", SDTIntBitCountUnaryOp>;
 def loongarch_ctzw : SDNode<"LoongArchISD::CTZ_W", SDTIntBitCountUnaryOp>;
+def loongarch_dbar : SDNode<"LoongArchISD::DBAR", SDT_LoongArchDBAR,
+ [SDNPHasChain, SDNPSideEffect]>;
 
 //===--===//
 // Operand and SDNode transformation definitions.
@@ -130,7 +134,8 @@
   let ParserMatchClass = UImmAsmOperand<14>;
 }
 
-def uimm15 : Operand {
+def uimm15 : Operand,
+ ImmLeaf (Imm);}]> {
   let ParserMatchClass = UImmAsmOperand<15>;
 }
 
@@ -1304,6 +1309,16 @@
   (PseudoAtomicLoadXor32 GPR:$incr, GPR:$addr)>;
 } // Predicates = [IsLA32]
 
+/// Intrinsics
+
+let Predicates = [IsLA32] in {
+def : Pat<(int_loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+} // Predicates = [IsLA32]
+
+let Predicates = [IsLA64] in {
+def : Pat<(loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+} // Predicates = [IsLA64]
+
 /// Other pseudo-instructions
 
 // Pessimistically assume the stack pointer will be clobbered
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.h
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -56,6 +56,9 @@
   REVB_2W,
   BITREV_4B,
   BITREV_W,
+
+  // Intrinsic operations
+  DBAR,
 };
 } // end namespace LoongArchISD
 
@@ -174,6 +177,7 @@
   SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const

[PATCH] D136413: [Clang][LoongArch] Define more LoongArch specific built-in macros

2022-11-10 Thread Gong LingQin via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG60e5cfe2a4eb: [Clang][LoongArch] Define more LoongArch 
specific built-in macros (authored by SixWeining, committed by gonglingqin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136413/new/

https://reviews.llvm.org/D136413

Files:
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/test/Preprocessor/init-loongarch.c

Index: clang/test/Preprocessor/init-loongarch.c
===
--- clang/test/Preprocessor/init-loongarch.c
+++ clang/test/Preprocessor/init-loongarch.c
@@ -322,6 +322,7 @@
 // LA32-LINUX: #define __gnu_linux__ 1
 // LA32-LINUX: #define __linux 1
 // LA32-LINUX: #define __linux__ 1
+// LA32-NOT: #define __loongarch64 1
 // LA32: #define __loongarch__ 1
 // LA32-LINUX: #define __unix 1
 // LA32-LINUX: #define __unix__ 1
@@ -634,8 +635,149 @@
 // LA64-LINUX: #define __gnu_linux__ 1
 // LA64-LINUX: #define __linux 1
 // LA64-LINUX: #define __linux__ 1
+// LA64: #define __loongarch64 1
 // LA64: #define __loongarch__ 1
 // LA64-LINUX: #define __unix 1
 // LA64-LINUX: #define __unix__ 1
 // LA64-LINUX: #define linux 1
 // LA64-LINUX: #define unix 1
+
+
+/// Check various macros prefixed with "__loongarch_" in different cases.
+/// "__loongarch__"" is not listed here as it has been checked above.
+
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32d -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32D %s
+// RUN: %clang --target=loongarch32 -mdouble-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32D %s
+// LA32-FPU64-ILP32D: __loongarch_double_float 1
+// LA32-FPU64-ILP32D-NEXT: __loongarch_frlen 64
+// LA32-FPU64-ILP32D-NEXT: __loongarch_grlen 32
+// LA32-FPU64-ILP32D-NEXT: __loongarch_hard_float 1
+// LA32-FPU64-ILP32D-NOT: __loongarch_lp64
+// LA32-FPU64-ILP32D-NOT: __loongarch_single_float
+// LA32-FPU64-ILP32D-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32f -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32F %s
+// LA32-FPU64-ILP32F-NOT: __loongarch_double_float
+// LA32-FPU64-ILP32F: __loongarch_frlen 64
+// LA32-FPU64-ILP32F-NEXT: __loongarch_grlen 32
+// LA32-FPU64-ILP32F-NEXT: __loongarch_hard_float 1
+// LA32-FPU64-ILP32F-NOT: __loongarch_lp64
+// LA32-FPU64-ILP32F-NEXT: __loongarch_single_float 1
+// LA32-FPU64-ILP32F-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -mfpu=64 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU64-ILP32S %s
+// LA32-FPU64-ILP32S-NOT: __loongarch_double_float
+// LA32-FPU64-ILP32S: __loongarch_frlen 64
+// LA32-FPU64-ILP32S-NEXT: __loongarch_grlen 32
+// LA32-FPU64-ILP32S-NOT: __loongarch_hard_float
+// LA32-FPU64-ILP32S-NOT: __loongarch_lp64
+// LA32-FPU64-ILP32S-NOT: __loongarch_single_float
+// LA32-FPU64-ILP32S-NEXT: __loongarch_soft_float 1
+
+// RUN: %clang --target=loongarch32 -mfpu=32 -mabi=ilp32f -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU32-ILP32F %s
+// RUN: %clang --target=loongarch32 -msingle-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU32-ILP32F %s
+// LA32-FPU32-ILP32F-NOT: __loongarch_double_float
+// LA32-FPU32-ILP32F: __loongarch_frlen 32
+// LA32-FPU32-ILP32F-NEXT: __loongarch_grlen 32
+// LA32-FPU32-ILP32F-NEXT: __loongarch_hard_float 1
+// LA32-FPU32-ILP32F-NOT: __loongarch_lp64
+// LA32-FPU32-ILP32F-NEXT: __loongarch_single_float 1
+// LA32-FPU32-ILP32F-NOT: __loongarch_soft_float
+
+// RUN: %clang --target=loongarch32 -mfpu=32 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU32-ILP32S %s
+// LA32-FPU32-ILP32S-NOT: __loongarch_double_float
+// LA32-FPU32-ILP32S: __loongarch_frlen 32
+// LA32-FPU32-ILP32S-NEXT: __loongarch_grlen 32
+// LA32-FPU32-ILP32S-NOT: __loongarch_hard_float
+// LA32-FPU32-ILP32S-NOT: __loongarch_lp64
+// LA32-FPU32-ILP32S-NOT: __loongarch_single_float
+// LA32-FPU32-ILP32S-NEXT: __loongarch_soft_float 1
+
+// RUN: %clang --target=loongarch32 -mfpu=0 -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU0-ILP32S %s
+// RUN: %clang --target=loongarch32 -mfpu=none -mabi=ilp32s -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU0-ILP32S %s
+// RUN: %clang --target=loongarch32 -msoft-float -x c -E -dM %s -o - \
+// RUN:   | grep __loongarch_ | FileCheck --check-prefix=LA32-FPU0-ILP32S %s
+// LA32-FPU0-ILP32S-NOT: __loongarch_double_float
+// LA32-FPU0-ILP32S: __loongarch_frlen 0
+// LA32-FPU0-ILP32S-NEXT: __loongarch_grlen 32
+// LA32-FPU0-ILP32S-NOT: __loongarch_hard_float
+// LA32-FPU0-ILP32S-NOT: __loongarch_lp

[PATCH] D137316: [Clang][LoongArch] Implement __builtin_loongarch_crc_w_d_w builtin and add diagnostics

2022-11-10 Thread Gong LingQin via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGda34aff90d2b: [Clang][LoongArch] Implement 
__builtin_loongarch_crc_w_d_w builtin and add… (authored by gonglingqin).

Changed prior to commit:
  https://reviews.llvm.org/D137316?vs=473620&id=474639#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137316/new/

https://reviews.llvm.org/D137316

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/LoongArch.cpp
  clang/lib/Basic/Targets/LoongArch.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -0,0 +1,13 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
+
+declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+
+define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_d_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -0,0 +1,10 @@
+; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
+
+declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+
+define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.d.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
===
--- llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -55,6 +55,8 @@
 def loongarch_srl_w : SDNode<"LoongArchISD::SRL_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotr_w : SDNode<"LoongArchISD::ROTR_W", SDT_LoongArchIntBinOpW>;
 def loongarch_rotl_w : SDNode<"LoongArchISD::ROTL_W", SDT_LoongArchIntBinOpW>;
+def loongarch_crc_w_d_w
+: SDNode<"LoongArchISD::CRC_W_D_W", SDT_LoongArchIntBinOpW>;
 def loongarch_bstrins
 : SDNode<"LoongArchISD::BSTRINS", SDT_LoongArchBStrIns>;
 def loongarch_bstrpick
@@ -1317,6 +1319,9 @@
 
 let Predicates = [IsLA64] in {
 def : Pat<(loongarch_dbar uimm15:$imm15), (DBAR uimm15:$imm15)>;
+
+// CRC Check Instructions
+def : PatGprGpr;
 } // Predicates = [IsLA64]
 
 /// Other pseudo-instructions
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.h
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -59,6 +59,9 @@
 
   // Intrinsic operations
   DBAR,
+
+  // CRC check operations
+  CRC_W_D_W
 };
 } // end namespace LoongArchISD
 
@@ -177,6 +180,7 @@
   SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+  SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Index: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
===
--- llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -90,6 +90,7 @@
 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
 setOperationAction(ISD::CTLZ, MVT::i32, Custom);
 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
+setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i32, Custom);
 if (Subtarget.hasBasicF() && !Subtarget.hasBasicD())
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
 if (Subtarget.hasBasicF())
@@ -114,6 +115,7 @@
 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal);
   } else {
 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
+setOperationAction(ISD:

[PATCH] D137809: [LoongArch] Add immediate operand validity check for __builtin_loongarch_dbar

2022-11-10 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay.
Herald added a subscriber: StephenFan.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137809

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c


Index: clang/test/CodeGen/LoongArch/intrinsic-error.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-error.c
+++ clang/test/CodeGen/LoongArch/intrinsic-error.c
@@ -6,3 +6,7 @@
 int crc_w_d_w(long int a, int b) {
   return __builtin_loongarch_crc_w_d_w(a, b); // expected-error {{this builtin 
requires target: loongarch64}}
 }
+
+void dbar() {
+  return __builtin_loongarch_dbar(32768); // expected-error {{argument value 
32768 is outside the valid range [0, 32767]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3683,6 +3683,9 @@
   diag::err_loongarch_builtin_requires_la64)
  << TheCall->getSourceRange();
 break;
+  case LoongArch::BI__builtin_loongarch_dbar:
+// Check if immediate is in [0, 32767]
+return SemaBuiltinConstantArgRange(TheCall, 0, 0, 32767);
   }
 
   return false;


Index: clang/test/CodeGen/LoongArch/intrinsic-error.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-error.c
+++ clang/test/CodeGen/LoongArch/intrinsic-error.c
@@ -6,3 +6,7 @@
 int crc_w_d_w(long int a, int b) {
   return __builtin_loongarch_crc_w_d_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
 }
+
+void dbar() {
+  return __builtin_loongarch_dbar(32768); // expected-error {{argument value 32768 is outside the valid range [0, 32767]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3683,6 +3683,9 @@
   diag::err_loongarch_builtin_requires_la64)
  << TheCall->getSourceRange();
 break;
+  case LoongArch::BI__builtin_loongarch_dbar:
+// Check if immediate is in [0, 32767]
+return SemaBuiltinConstantArgRange(TheCall, 0, 0, 32767);
   }
 
   return false;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137809: [LoongArch] Add immediate operand validity check for __builtin_loongarch_dbar

2022-11-14 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: clang/test/CodeGen/LoongArch/intrinsic-error.c:11
+void dbar() {
+  return __builtin_loongarch_dbar(32768); // expected-error {{argument value 
32768 is outside the valid range [0, 32767]}}
+}

SixWeining wrote:
> Also check lower bound.
Thanks, I will add test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137809/new/

https://reviews.llvm.org/D137809

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137809: [LoongArch] Add immediate operand validity check for __builtin_loongarch_dbar

2022-11-14 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 475333.
gonglingqin added a comment.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Add test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137809/new/

https://reviews.llvm.org/D137809

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll


Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -8,11 +8,18 @@
   ret void
 }
 
-define void @dbar_imm_out_of_range() nounwind {
+define void @dbar_imm_out_of_hi_range() nounwind {
 ; CHECK: argument to '__builtin_loongarch_dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 32769)
   ret void
 }
 
+define void @dbar_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' out of range
+entry:
+  call void @llvm.loongarch.dbar(i32 -1)
+  ret void
+}
+
 declare void @llvm.loongarch.dbar(i32)
Index: clang/test/CodeGen/LoongArch/intrinsic-error.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-error.c
+++ clang/test/CodeGen/LoongArch/intrinsic-error.c
@@ -6,3 +6,11 @@
 int crc_w_d_w(long int a, int b) {
   return __builtin_loongarch_crc_w_d_w(a, b); // expected-error {{this builtin 
requires target: loongarch64}}
 }
+
+void dbar_out_of_hi_range() {
+  return __builtin_loongarch_dbar(32768); // expected-error {{argument value 
32768 is outside the valid range [0, 32767]}}
+}
+
+void dbar_out_of_lo_range() {
+  return __builtin_loongarch_dbar(-1); // expected-error {{argument value 
4294967295 is outside the valid range [0, 32767]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3683,6 +3683,9 @@
   diag::err_loongarch_builtin_requires_la64)
  << TheCall->getSourceRange();
 break;
+  case LoongArch::BI__builtin_loongarch_dbar:
+// Check if immediate is in [0, 32767]
+return SemaBuiltinConstantArgRange(TheCall, 0, 0, 32767);
   }
 
   return false;


Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -8,11 +8,18 @@
   ret void
 }
 
-define void @dbar_imm_out_of_range() nounwind {
+define void @dbar_imm_out_of_hi_range() nounwind {
 ; CHECK: argument to '__builtin_loongarch_dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 32769)
   ret void
 }
 
+define void @dbar_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' out of range
+entry:
+  call void @llvm.loongarch.dbar(i32 -1)
+  ret void
+}
+
 declare void @llvm.loongarch.dbar(i32)
Index: clang/test/CodeGen/LoongArch/intrinsic-error.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-error.c
+++ clang/test/CodeGen/LoongArch/intrinsic-error.c
@@ -6,3 +6,11 @@
 int crc_w_d_w(long int a, int b) {
   return __builtin_loongarch_crc_w_d_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
 }
+
+void dbar_out_of_hi_range() {
+  return __builtin_loongarch_dbar(32768); // expected-error {{argument value 32768 is outside the valid range [0, 32767]}}
+}
+
+void dbar_out_of_lo_range() {
+  return __builtin_loongarch_dbar(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 32767]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3683,6 +3683,9 @@
   diag::err_loongarch_builtin_requires_la64)
  << TheCall->getSourceRange();
 break;
+  case LoongArch::BI__builtin_loongarch_dbar:
+// Check if immediate is in [0, 32767]
+return SemaBuiltinConstantArgRange(TheCall, 0, 0, 32767);
   }
 
   return false;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D137809: [LoongArch] Add immediate operand validity check for __builtin_loongarch_dbar

2022-11-15 Thread Gong LingQin via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGddbb21bdb579: [LoongArch] Add immediate operand validity 
check for __builtin_loongarch_dbar (authored by gonglingqin).

Changed prior to commit:
  https://reviews.llvm.org/D137809?vs=475333&id=475690#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137809/new/

https://reviews.llvm.org/D137809

Files:
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll


Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -8,11 +8,18 @@
   ret void
 }
 
-define void @dbar_imm_out_of_range() nounwind {
+define void @dbar_imm_out_of_hi_range() nounwind {
 ; CHECK: argument to '__builtin_loongarch_dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 32769)
   ret void
 }
 
+define void @dbar_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' out of range
+entry:
+  call void @llvm.loongarch.dbar(i32 -1)
+  ret void
+}
+
 declare void @llvm.loongarch.dbar(i32)
Index: clang/test/CodeGen/LoongArch/intrinsic-error.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-error.c
+++ clang/test/CodeGen/LoongArch/intrinsic-error.c
@@ -6,3 +6,11 @@
 int crc_w_d_w(long int a, int b) {
   return __builtin_loongarch_crc_w_d_w(a, b); // expected-error {{this builtin 
requires target: loongarch64}}
 }
+
+void dbar_out_of_hi_range() {
+  return __builtin_loongarch_dbar(32768); // expected-error {{argument value 
32768 is outside the valid range [0, 32767]}}
+}
+
+void dbar_out_of_lo_range() {
+  return __builtin_loongarch_dbar(-1); // expected-error {{argument value 
4294967295 is outside the valid range [0, 32767]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3685,6 +3685,9 @@
   diag::err_loongarch_builtin_requires_la64)
  << TheCall->getSourceRange();
 break;
+  case LoongArch::BI__builtin_loongarch_dbar:
+// Check if immediate is in [0, 32767].
+return SemaBuiltinConstantArgRange(TheCall, 0, 0, 32767);
   }
 
   return false;


Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -8,11 +8,18 @@
   ret void
 }
 
-define void @dbar_imm_out_of_range() nounwind {
+define void @dbar_imm_out_of_hi_range() nounwind {
 ; CHECK: argument to '__builtin_loongarch_dbar' out of range
 entry:
   call void @llvm.loongarch.dbar(i32 32769)
   ret void
 }
 
+define void @dbar_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_dbar' out of range
+entry:
+  call void @llvm.loongarch.dbar(i32 -1)
+  ret void
+}
+
 declare void @llvm.loongarch.dbar(i32)
Index: clang/test/CodeGen/LoongArch/intrinsic-error.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-error.c
+++ clang/test/CodeGen/LoongArch/intrinsic-error.c
@@ -6,3 +6,11 @@
 int crc_w_d_w(long int a, int b) {
   return __builtin_loongarch_crc_w_d_w(a, b); // expected-error {{this builtin requires target: loongarch64}}
 }
+
+void dbar_out_of_hi_range() {
+  return __builtin_loongarch_dbar(32768); // expected-error {{argument value 32768 is outside the valid range [0, 32767]}}
+}
+
+void dbar_out_of_lo_range() {
+  return __builtin_loongarch_dbar(-1); // expected-error {{argument value 4294967295 is outside the valid range [0, 32767]}}
+}
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3685,6 +3685,9 @@
   diag::err_loongarch_builtin_requires_la64)
  << TheCall->getSourceRange();
 break;
+  case LoongArch::BI__builtin_loongarch_dbar:
+// Check if immediate is in [0, 32767].
+return SemaBuiltinConstantArgRange(TheCall, 0, 0, 32767);
   }
 
   return false;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138094: [LoongArch] Add intrinsics for ibar, break and syscall

2022-11-15 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay, 
XiaodongLoong.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

Diagnostics for intrinsic input parameters have also been added.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138094

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -3,6 +3,9 @@
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -13,3 +16,33 @@
   call void @llvm.loongarch.dbar(i32 0)
   ret void
 }
+
+define void @ibar() nounwind {
+; CHECK-LABEL: ibar:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ibar 0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.ibar(i32 0)
+  ret void
+}
+
+define void @break() nounwind {
+; CHECK-LABEL: break:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:break 1
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.break(i32 1)
+  ret void
+}
+
+define void @syscall() nounwind {
+; CHECK-LABEL: syscall:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:syscall 1
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.syscall(i32 1)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -1,6 +1,11 @@
 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 ; RUN: not llc --mtriple=loongarch64 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
+
 define void @dbar_not_constant(i32 %x) nounwind {
 ; CHECK: argument to '__builtin_loongarch_dbar' must be a constant integer
 entry:
@@ -8,6 +13,27 @@
   ret void
 }
 
+define void @ibar(i32 %x) nounwind {
+; CHECK: argument to '__builtin_loongarch_ibar' must be a constant integer
+entry:
+  call void @llvm.loongarch.ibar(i32 %x)
+  ret void
+}
+
+define void @break(i32 %x) nounwind {
+; CHECK: argument to '__builtin_loongarch_break' must be a constant integer
+entry:
+  call void @llvm.loongarch.break(i32 %x)
+  ret void
+}
+
+define void @syscall(i32 %x) nounwind {
+; CHECK: argument to '__builtin_loongarch_syscall' must be a constant integer
+entry:
+  call void @llvm.loongarch.syscall(i32 %x)
+  ret void
+}
+
 define void @dbar_imm_out_of_hi_range() nounwind {
 ; CHECK: argument to '__builtin_loongarch_dbar' out of range
 entry:
@@ -22,4 +48,44 @@
   ret void
 }
 
-declare void @llvm.loongarch.dbar(i32)
+define void @ibar_imm_out_of_hi_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_ibar' out of range
+entry:
+  call void @llvm.loongarch.ibar(i32 32769)
+  ret void
+}
+
+define void @ibar_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_ibar' out of range
+entry:
+  call void @llvm.loongarch.ibar(i32 -1)
+  ret void
+}
+
+define void @break_imm_out_of_hi_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_break' out of range
+entry:
+  call void @llvm.loongarch.break(i32 32769)
+  ret void
+}
+
+define void @break_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_break' out of range
+entry:
+  call void @llvm.loongarch.break(i32 -1)
+  ret void
+}
+
+define void @syscall_imm_out_of_hi_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_syscall' out of range
+entry:
+  call void @llvm.loongarch.syscall(i32 32769)
+  ret void
+}
+
+define void @syscall_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_syscall' out of range
+entry:
+  call void @llvm.loongarch.syscall(i32 -1)
+  ret void
+}
Index: llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
===
--- llvm/lib/Target/LoongArch/LoongArchInstrInfo.

[PATCH] D138094: [LoongArch] Add intrinsics for ibar, break and syscall

2022-11-16 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: clang/include/clang/Basic/BuiltinsLoongArch.def:20-23
 TARGET_BUILTIN(__builtin_loongarch_dbar, "vIUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_ibar, "vIUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_break, "vIUi", "nc", "")
+TARGET_BUILTIN(__builtin_loongarch_syscall, "vIUi", "nc", "")

arsenm wrote:
> These all have I parameters but the underlying intrinsic wasn't marked with 
> immarg 
Thanks for checking, I'll add constraints.



Comment at: clang/test/CodeGen/LoongArch/intrinsic-error.c:21
+  __builtin_loongarch_ibar(-1); // expected-error {{argument value 4294967295 
is outside the valid range [0, 32767]}}
+}
+

arsenm wrote:
> Should also test non-constant cases 
Thanks, I'll add the test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138094/new/

https://reviews.llvm.org/D138094

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138094: [LoongArch] Add intrinsics for ibar, break and syscall

2022-11-16 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 475715.
gonglingqin added a comment.

Address @arsenm's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138094/new/

https://reviews.llvm.org/D138094

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -3,6 +3,9 @@
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -13,3 +16,33 @@
   call void @llvm.loongarch.dbar(i32 0)
   ret void
 }
+
+define void @ibar() nounwind {
+; CHECK-LABEL: ibar:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ibar 0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.ibar(i32 0)
+  ret void
+}
+
+define void @break() nounwind {
+; CHECK-LABEL: break:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:break 1
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.break(i32 1)
+  ret void
+}
+
+define void @syscall() nounwind {
+; CHECK-LABEL: syscall:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:syscall 1
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.syscall(i32 1)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
@@ -0,0 +1,35 @@
+; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
+
+declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
+
+define void @dbar_not_constant(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.dbar(i32 %x)
+  ret void
+}
+
+define void @ibar(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.ibar(i32 %x)
+  ret void
+}
+
+define void @break(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.break(i32 %x)
+  ret void
+}
+
+define void @syscall(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.syscall(i32 %x)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -1,12 +1,10 @@
-; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
-; RUN: not llc --mtriple=loongarch64 --disable-verify < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
 
-define void @dbar_not_constant(i32 %x) nounwind {
-; CHECK: argument to '__builtin_loongarch_dbar' must be a constant integer
-entry:
-  call void @llvm.loongarch.dbar(i32 %x)
-  ret void
-}
+declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
 
 define void @dbar_imm_out_of_hi_range() nounwind {
 ; CHECK: argument to '__builtin_loongarch_dbar' out of range
@@ -22,4 +20,44 @@
   ret void
 }
 
-declare void @llvm.loongarch.dbar(i32)
+define void @ibar_imm_out_of_hi_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_ibar' out of range
+entry:
+  call void @llvm.loongarch.ibar(i32 32769)
+  ret void
+}
+
+define void @ibar_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_ibar' out of range
+entry:
+  call void @llvm.loongarch.ibar(i32 -1)
+  ret void
+}
+
+define void @break_imm_out_of_hi_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_break' out of range
+entry:
+  call void @llvm.loongarch.break(i32 32769)
+  ret void
+}
+
+define void @break_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_break' out of range
+entry:
+  call void @llvm.loo

[PATCH] D138094: [LoongArch] Add intrinsics for ibar, break and syscall

2022-11-16 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:603
   case Intrinsic::loongarch_dbar: {
-SDValue Op0 = Op.getOperand(0);
-SDValue Op2 = Op.getOperand(2);
-if (!isa(Op2)) {
-  DAG.getContext()->emitError("argument to '__builtin_loongarch_dbar' must 
"
-  "be a constant integer");
-  return Op.getOperand(0);
-}
+Name = "__builtin_loongarch_dbar";
 unsigned Imm = cast(Op2)->getZExtValue();

SixWeining wrote:
> This string can be inlined into line 606. Then line 595 can be removed.
Thanks, I will modify it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138094/new/

https://reviews.llvm.org/D138094

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138094: [LoongArch] Add intrinsics for ibar, break and syscall

2022-11-16 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 475987.
gonglingqin added a comment.

Address @SixWeining's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138094/new/

https://reviews.llvm.org/D138094

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -3,6 +3,9 @@
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -13,3 +16,33 @@
   call void @llvm.loongarch.dbar(i32 0)
   ret void
 }
+
+define void @ibar() nounwind {
+; CHECK-LABEL: ibar:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ibar 0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.ibar(i32 0)
+  ret void
+}
+
+define void @break() nounwind {
+; CHECK-LABEL: break:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:break 1
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.break(i32 1)
+  ret void
+}
+
+define void @syscall() nounwind {
+; CHECK-LABEL: syscall:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:syscall 1
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.syscall(i32 1)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
@@ -0,0 +1,35 @@
+; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
+
+declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
+
+define void @dbar_not_constant(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.dbar(i32 %x)
+  ret void
+}
+
+define void @ibar(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.ibar(i32 %x)
+  ret void
+}
+
+define void @break(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.break(i32 %x)
+  ret void
+}
+
+define void @syscall(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.syscall(i32 %x)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -1,12 +1,10 @@
-; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
-; RUN: not llc --mtriple=loongarch64 --disable-verify < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
 
-define void @dbar_not_constant(i32 %x) nounwind {
-; CHECK: argument to '__builtin_loongarch_dbar' must be a constant integer
-entry:
-  call void @llvm.loongarch.dbar(i32 %x)
-  ret void
-}
+declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
 
 define void @dbar_imm_out_of_hi_range() nounwind {
 ; CHECK: argument to '__builtin_loongarch_dbar' out of range
@@ -22,4 +20,44 @@
   ret void
 }
 
-declare void @llvm.loongarch.dbar(i32)
+define void @ibar_imm_out_of_hi_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_ibar' out of range
+entry:
+  call void @llvm.loongarch.ibar(i32 32769)
+  ret void
+}
+
+define void @ibar_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_ibar' out of range
+entry:
+  call void @llvm.loongarch.ibar(i32 -1)
+  ret void
+}
+
+define void @break_imm_out_of_hi_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_break' out of range
+entry:
+  call void @llvm.loongarch.break(i32 32769)
+  ret void
+}
+
+define void @break_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_break' out of range
+entry:
+  call void @llvm

[PATCH] D138094: [LoongArch] Add intrinsics for ibar, break and syscall

2022-11-20 Thread Gong LingQin via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc2ec455f183d: [LoongArch] Add intrinsics for ibar, break and 
syscall (authored by gonglingqin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138094/new/

https://reviews.llvm.org/D138094

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -3,6 +3,9 @@
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
 declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -13,3 +16,33 @@
   call void @llvm.loongarch.dbar(i32 0)
   ret void
 }
+
+define void @ibar() nounwind {
+; CHECK-LABEL: ibar:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ibar 0
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.ibar(i32 0)
+  ret void
+}
+
+define void @break() nounwind {
+; CHECK-LABEL: break:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:break 1
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.break(i32 1)
+  ret void
+}
+
+define void @syscall() nounwind {
+; CHECK-LABEL: syscall:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:syscall 1
+; CHECK-NEXT:ret
+entry:
+  call void @llvm.loongarch.syscall(i32 1)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-not-constant-error.ll
@@ -0,0 +1,35 @@
+; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
+
+declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
+
+define void @dbar_not_constant(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.dbar(i32 %x)
+  ret void
+}
+
+define void @ibar(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.ibar(i32 %x)
+  ret void
+}
+
+define void @break(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.break(i32 %x)
+  ret void
+}
+
+define void @syscall(i32 %x) nounwind {
+; CHECK: immarg operand has non-immediate parameter
+entry:
+  call void @llvm.loongarch.syscall(i32 %x)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -1,12 +1,10 @@
-; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
-; RUN: not llc --mtriple=loongarch64 --disable-verify < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
 
-define void @dbar_not_constant(i32 %x) nounwind {
-; CHECK: argument to '__builtin_loongarch_dbar' must be a constant integer
-entry:
-  call void @llvm.loongarch.dbar(i32 %x)
-  ret void
-}
+declare void @llvm.loongarch.dbar(i32)
+declare void @llvm.loongarch.ibar(i32)
+declare void @llvm.loongarch.break(i32)
+declare void @llvm.loongarch.syscall(i32)
 
 define void @dbar_imm_out_of_hi_range() nounwind {
 ; CHECK: argument to '__builtin_loongarch_dbar' out of range
@@ -22,4 +20,44 @@
   ret void
 }
 
-declare void @llvm.loongarch.dbar(i32)
+define void @ibar_imm_out_of_hi_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_ibar' out of range
+entry:
+  call void @llvm.loongarch.ibar(i32 32769)
+  ret void
+}
+
+define void @ibar_imm_out_of_lo_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_ibar' out of range
+entry:
+  call void @llvm.loongarch.ibar(i32 -1)
+  ret void
+}
+
+define void @break_imm_out_of_hi_range() nounwind {
+; CHECK: argument to '__builtin_loongarch_break' out of range
+entry:
+  call void @llvm.loongarch.break(i32 32769)
+  ret void
+}
+
+define void @break_imm_out_of_lo_range() nounwind {
+; CHECK: ar

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-11-20 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added a comment.

In D136906#3940289 , 
@WowbaggersLiquidLunch wrote:

> Hi, this seems to be causing some problems when generating Xcode project.
>
> When I try to generate the Xcode project with the following command:
>
>   cmake -G "Xcode" -DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="X86" 
> -DLLVM_ENABLE_PROJECTS="clang" -DLLVM_OPTIMIZED_TABLEGEN=ON 
> -DLLVM_ENABLE_IDE=ON -DLLVM_CCACHE_BUILD=ON ../../llvm
>
> I get the following error:
>
>> CMake Error in /path/to/llvm-project/clang/lib/Headers/CMakeLists.txt:
>>
>>   The custom command generating
>>   
>> 
>> /path/to/llvm-project/build/Xcode-Debug/$(CONFIGURATION)$(EFFECTIVE_PLATFORM_NAME)/lib/clang/16/include/larchintrin.h
>>   
>>   is attached to multiple targets:
>>   
>> clang-resource-headers
>> loongarch-resource-headers
>>   
>>   but none of these is a common dependency of the other(s).  This is not
>>   allowed by the Xcode "new build system".
>>
>> CMake Error in /path/to/llvm-project/third-party/benchmark/CMakeLists.txt:
>>
>>   The custom command generating
>>   
>> 
>> /path/to/llvm-project/build/Xcode-Debug/$(CONFIGURATION)$(EFFECTIVE_PLATFORM_NAME)/lib/clang/16/include/larchintrin.h
>>   
>>   is attached to multiple targets:
>>   
>> clang-resource-headers
>> loongarch-resource-headers
>>   
>>   but none of these is a common dependency of the other(s).  This is not
>>   allowed by the Xcode "new build system".

Thank you for your input. Correct me if I'm wrong,  when I create a new build 
directory and execute the following command:

  cmake -G "Xcode" -DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="X86" 
-DLLVM_ENABLE_PROJECTS="clang" -DLLVM_OPTIMIZED_TABLEGEN=ON 
-DLLVM_ENABLE_IDE=ON -DLLVM_CCACHE_BUILD=ON ../../llvm

I get the following error:

  CMake Error: Could not create named generator Xcode

  Generators
Unix Makefiles   = Generates standard UNIX makefiles.
Ninja= Generates build.ninja files.
Watcom WMake = Generates Watcom WMake makefiles.
CodeBlocks - Ninja   = Generates CodeBlocks project files.
CodeBlocks - Unix Makefiles  = Generates CodeBlocks project files.
CodeLite - Ninja = Generates CodeLite project files.
CodeLite - Unix Makefiles= Generates CodeLite project files.
Sublime Text 2 - Ninja   = Generates Sublime Text 2 project files.
Sublime Text 2 - Unix Makefiles
 = Generates Sublime Text 2 project files.
Kate - Ninja = Generates Kate project files.
Kate - Unix Makefiles= Generates Kate project files.
Eclipse CDT4 - Ninja = Generates Eclipse CDT 4.0 project files.
Eclipse CDT4 - Unix Makefiles= Generates Eclipse CDT 4.0 project files.

But when I change `Xcode` to `Ninja`, no error output is generated.
Do you have any suggestions for reproducing the bugs you mentioned?

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136906/new/

https://reviews.llvm.org/D136906

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138403: [LoongArch] Fix issue on CMake Xcode build configuration

2022-11-21 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay, 
XiaodongLoong.
Herald added a subscriber: StephenFan.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add missing dependency for loongarch-resource-headers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138403

Files:
  clang/lib/Headers/CMakeLists.txt


Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -394,6 +394,7 @@
  "hexagon-resource-headers"
  "hip-resource-headers"
  "hlsl-resource-headers"
+ "loongarch-resource-headers"
  "mips-resource-headers"
  "ppc-resource-headers"
  "ppc-htm-resource-headers"


Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -394,6 +394,7 @@
  "hexagon-resource-headers"
  "hip-resource-headers"
  "hlsl-resource-headers"
+ "loongarch-resource-headers"
  "mips-resource-headers"
  "ppc-resource-headers"
  "ppc-htm-resource-headers"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-11-21 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added a comment.

In D136906#3940289 , 
@WowbaggersLiquidLunch wrote:

> Hi, this seems to be causing some problems when generating Xcode project.
>
> When I try to generate the Xcode project with the following command:
>
>   cmake -G "Xcode" -DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="X86" 
> -DLLVM_ENABLE_PROJECTS="clang" -DLLVM_OPTIMIZED_TABLEGEN=ON 
> -DLLVM_ENABLE_IDE=ON -DLLVM_CCACHE_BUILD=ON ../../llvm
>
> I get the following error:
>
>> CMake Error in /path/to/llvm-project/clang/lib/Headers/CMakeLists.txt:
>>
>>   The custom command generating
>>   
>> 
>> /path/to/llvm-project/build/Xcode-Debug/$(CONFIGURATION)$(EFFECTIVE_PLATFORM_NAME)/lib/clang/16/include/larchintrin.h
>>   
>>   is attached to multiple targets:
>>   
>> clang-resource-headers
>> loongarch-resource-headers
>>   
>>   but none of these is a common dependency of the other(s).  This is not
>>   allowed by the Xcode "new build system".
>>
>> CMake Error in /path/to/llvm-project/third-party/benchmark/CMakeLists.txt:
>>
>>   The custom command generating
>>   
>> 
>> /path/to/llvm-project/build/Xcode-Debug/$(CONFIGURATION)$(EFFECTIVE_PLATFORM_NAME)/lib/clang/16/include/larchintrin.h
>>   
>>   is attached to multiple targets:
>>   
>> clang-resource-headers
>> loongarch-resource-headers
>>   
>>   but none of these is a common dependency of the other(s).  This is not
>>   allowed by the Xcode "new build system".

I realized that it might be my environment that prevented me from repeating 
this problem. Can you use https://reviews.llvm.org/D138403 to solve this 
problem?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136906/new/

https://reviews.llvm.org/D136906

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-11-21 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added a comment.

In D136906#3940427 , 
@WowbaggersLiquidLunch wrote:

>> I get the following error:
>>
>>> CMake Error: Could not create named generator Xcode
>
> Sorry, I forgot to mention that Xcode is only available on macOS.
>
>> But when I change Xcode to Ninja, no error output is generated.
>
> Indeed. Ninja works fine for me as well. The problem is I kind of need both 
> Xcode and Ninja in my workflow (Xcode for editing, Ninja for building).
>
>> Do you have any suggestions for reproducing the bugs you mentioned?
>
> I think the following steps should be able to reproduce the error messages 
> I'm seeing (It's a bit long):
>
> 1. Install macOS 12.6 or newer. (I'm currently on 12.6, but newer versions 
> such as 12.6.1 and 13 (the latest) should produce the same error messages.)
>
> 2. Install Xcode 14.1 and/or the Xcode command line tools
>   - Xcode can be installed via this link 
> 
>  (generally recommended), or from the Mac App Store via this link 
> .
> - The first link downloads a `.xip` file which can take a long time to 
> decompress. This step can be sped up significantly by decompressing the file 
> using this tool .
>   - The command line tools can be installed via this link 
> ,
>  via the following commands, or by launching Xcode after it's installed. (I 
> don't remember it clearly, but I think you probably can skip this step and 
> have Homebrew install it for you in step 3)
>
> `sudo rm -rf /Library/Developer/CommandLineTools`
>
> `sudo xcode-select --install`
>
> 3. Install LLVM's dependencies 
>  via Homebrew
>   - First we need to install brew  using the following 
> command
>
> `/bin/bash -c "$(curl -fsSL 
> https://raw.githubusercontent.com/Homebrew/install/HEAD/install.sh)"`
>   - Then install Cmake and Python with `brew`. (I'm not sure if Python is 
> really needed)
>
> `brew install cmake python`
>
> 4. Clone LLVM and create the build directory.
> 5. Generate Xcode project using CMake.
>
>   `cmake -G "Xcode" -DCMAKE_BUILD_TYPE=Debug -DLLVM_TARGETS_TO_BUILD="X86" 
> -DLLVM_ENABLE_PROJECTS="clang" -DLLVM_OPTIMIZED_TABLEGEN=ON 
> -DLLVM_ENABLE_IDE=ON -DLLVM_CCACHE_BUILD=ON path/to/llvm`
>
>   Flags other than `-G "Xcode"` probably are optional for the purpose of 
> reproducing the error messages.

Thanks! Very nice to know.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136906/new/

https://reviews.llvm.org/D136906

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D136906: [Clang][LoongArch] Implement __builtin_loongarch_dbar builtin

2022-11-21 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added a comment.

In D136906#3940432 , 
@WowbaggersLiquidLunch wrote:

> In D136906#3940377 , @gonglingqin 
> wrote:
>
>> Can you use https://reviews.llvm.org/D138403 to solve this problem?
>
> Thanks for letting me know. I'll give it a try.

Thanks a lot!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136906/new/

https://reviews.llvm.org/D136906

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138418: [LoongArch] Add remaining intrinsics for CRC check instructions

2022-11-21 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay, 
XiaodongLoong.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

After D137316  implements the intrinsics of 
the first crc check instruction
and related diagnosis, this patch implements the intrinsics of all remaining
crc check instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138418

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -1,7 +1,41 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_d_w:
@@ -11,3 +45,39 @@
   %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i32 @crcc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_d_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -1,6 +1,34 @@
 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.h.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32

[PATCH] D138403: [LoongArch] Fix issue on CMake Xcode build configuration

2022-11-22 Thread Gong LingQin via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG0cf2286cb8f8: [LoongArch] Fix issue on CMake Xcode build 
configuration (authored by gonglingqin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138403/new/

https://reviews.llvm.org/D138403

Files:
  clang/lib/Headers/CMakeLists.txt


Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -394,6 +394,7 @@
  "hexagon-resource-headers"
  "hip-resource-headers"
  "hlsl-resource-headers"
+ "loongarch-resource-headers"
  "mips-resource-headers"
  "ppc-resource-headers"
  "ppc-htm-resource-headers"


Index: clang/lib/Headers/CMakeLists.txt
===
--- clang/lib/Headers/CMakeLists.txt
+++ clang/lib/Headers/CMakeLists.txt
@@ -394,6 +394,7 @@
  "hexagon-resource-headers"
  "hip-resource-headers"
  "hlsl-resource-headers"
+ "loongarch-resource-headers"
  "mips-resource-headers"
  "ppc-resource-headers"
  "ppc-htm-resource-headers"
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138418: [LoongArch] Add remaining intrinsics for CRC check instructions

2022-11-22 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 477363.
gonglingqin added a comment.

Address @SixWeining's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138418/new/

https://reviews.llvm.org/D138418

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -1,7 +1,41 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_d_w:
@@ -11,3 +45,39 @@
   %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i32 @crcc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_d_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -1,6 +1,34 @@
 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.h.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.w.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK: llvm.loongarch.crc.w.d.w requires target: loongarch64
@@ -8,3 +36,31 @@
   %r

[PATCH] D138418: [LoongArch] Add remaining intrinsics for CRC check instructions

2022-11-22 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:925
   llvm_unreachable("Unexpected Intrinsic.");
-case Intrinsic::loongarch_crc_w_d_w: {
-  Results.push_back(DAG.getNode(
-  ISD::TRUNCATE, DL, N->getValueType(0),
-  DAG.getNode(
-  LoongArchISD::CRC_W_D_W, DL, MVT::i64, N->getOperand(2),
-  DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3);
-  Results.push_back(N->getOperand(0));
-  break;
-}
+#define CRC_CASE_EXT_TWOOP(NAME, node) 
\
+  case Intrinsic::loongarch_##NAME: {  
\

SixWeining wrote:
> You could use uppercase to keep consistency.
Thanks, I will modify it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138418/new/

https://reviews.llvm.org/D138418

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138418: [LoongArch] Add remaining intrinsics for CRC check instructions

2022-11-22 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 477382.
gonglingqin added a comment.

Address @SixWeining's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138418/new/

https://reviews.llvm.org/D138418

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -1,7 +1,41 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_d_w:
@@ -11,3 +45,39 @@
   %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i32 @crcc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_d_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -1,6 +1,34 @@
 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.h.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.w.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK: llvm.loongarch.crc.w.d.w requires target: loongarch64
@@ -8,3 +36,31 @@
   %r

[PATCH] D138418: [LoongArch] Add remaining intrinsics for CRC check instructions

2022-11-22 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:925
   llvm_unreachable("Unexpected Intrinsic.");
-case Intrinsic::loongarch_crc_w_d_w: {
-  Results.push_back(DAG.getNode(
-  ISD::TRUNCATE, DL, N->getValueType(0),
-  DAG.getNode(
-  LoongArchISD::CRC_W_D_W, DL, MVT::i64, N->getOperand(2),
-  DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3);
-  Results.push_back(N->getOperand(0));
-  break;
-}
+#define CRC_CASE_EXT_TWOOP(NAME, NODE) 
\
+  case Intrinsic::loongarch_##NAME: {  
\

xen0n wrote:
> What's a "two op", are you meaning "binary op" instead?
Yes, thank you for your correction!



Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:942
+
+#define CRC_CASE_EXT_ONEOP(NAME, NODE) 
\
+  case Intrinsic::loongarch_##NAME: {  
\

xen0n wrote:
> Similarly, is this actually "unary op"?
Thanks a lot! I will modify it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138418/new/

https://reviews.llvm.org/D138418

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D138418: [LoongArch] Add remaining intrinsics for CRC check instructions

2022-11-22 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 477393.
gonglingqin added a comment.

Address @xen0n's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138418/new/

https://reviews.llvm.org/D138418

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -1,7 +1,41 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_d_w:
@@ -11,3 +45,39 @@
   %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i32 @crcc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_d_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -1,6 +1,34 @@
 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.h.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.w.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK: llvm.loongarch.crc.w.d.w requires target: loongarch64
@@ -8,3 +36,31 @@
   %res =

[PATCH] D138418: [LoongArch] Add remaining intrinsics for CRC check instructions

2022-11-30 Thread Gong LingQin via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG624401612c3a: [LoongArch] Add remaining intrinsics for CRC 
check instructions (authored by gonglingqin).

Changed prior to commit:
  https://reviews.llvm.org/D138418?vs=477393&id=479128#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138418/new/

https://reviews.llvm.org/D138418

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -1,7 +1,41 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
 
 define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_d_w:
@@ -11,3 +45,39 @@
   %res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i32 @crcc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_b_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.b.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_h_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.h.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_w_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.w.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.w.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crcc_w_d_w(i64 %a, i32 %b) nounwind {
+; CHECK-LABEL: crcc_w_d_w:
+; CHECK:   # %bb.0:
+; CHECK-NEXT:crcc.w.d.w $a0, $a0, $a1
+; CHECK-NEXT:ret
+  %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
+  ret i32 %res
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -1,6 +1,34 @@
 ; RUN: not llc --mtriple=loongarch32 --disable-verify < %s 2>&1 | FileCheck %s
 
+declare i32 @llvm.loongarch.crc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crc.w.d.w(i64, i32)
+declare i32 @llvm.loongarch.crcc.w.b.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
+declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+
+define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.h.w requires target: loongarch64
+entry:
+  %res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
+  ret i32 %res
+}
+
+define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
+; CHECK: llvm.loongarch.crc.w.w.w requires target: loongarch64

[PATCH] D139288: [Clang][LoongArch] Add intrinsic for csrrd, csrwr and csrxchg

2022-12-04 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay, 
XiaodongLoong.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

These intrinsics are required by Linux [1].

[1]: 
https://github.com/loongson/linux/blob/master/arch/loongarch/include/asm/loongarch.h


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139288

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error-la64.c
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -6,6 +6,9 @@
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
 declare void @llvm.loongarch.syscall(i32)
+declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
+declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
+declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -46,3 +49,33 @@
   call void @llvm.loongarch.syscall(i32 1)
   ret void
 }
+
+define i32 @csrrd_w() {
+; CHECK-LABEL: csrrd_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrrd $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrrd.w(i32 1)
+  ret i32 %0
+}
+
+define i32 @csrwr_w(i32 signext %a) {
+; CHECK-LABEL: csrwr_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrwr $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1)
+  ret i32 %0
+}
+
+define i32 @csrxchg_w(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: csrxchg_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrxchg $a0, $a1, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
+  ret i32 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -9,6 +9,9 @@
 declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
+declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
+declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -81,3 +84,33 @@
   %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i64 @csrrd_d() {
+; CHECK-LABEL: csrrd_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrrd $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrrd.d(i32 1)
+  ret i64 %0
+}
+
+define i64 @csrwr_d(i64 %a) {
+; CHECK-LABEL: csrwr_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrwr $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
+  ret i64 %0
+}
+
+define i64 @csrxchg_d(i64 %a, i64 %b) {
+; CHECK-LABEL: csrxchg_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrxchg $a0, $a1, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
+  ret i64 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
+
+declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
+declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
+declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
+
+define i64 @csrrd_d_imm_out_of_hi_range() nounwind {
+; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range
+entry:
+  %0 = call i64 @llvm.loongarch.csrrd.d(i32 16384)
+  ret i64 %0
+}
+
+define i64 @csrrd_d_imm_out_of_lo_range() nounwind {
+; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range

[PATCH] D139288: [Clang][LoongArch] Add intrinsic for csrrd, csrwr and csrxchg

2022-12-04 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added a comment.

In D139288#3969746 , @xen0n wrote:

> You'll also need the IOCSR intrinsics too for building Linux. Since they're 
> very similar to some of the CSR intrinsics you added here, do you plan to add 
> support for them later here or in a separate follow-up change?

Thanks for your reminding. The IOCSR intrinsics has been implemented and I will 
submit it later.




Comment at: clang/lib/Headers/larchintrin.h:84
+
+#ifdef __loongarch_grlen == 64
+#define __csrrd_d(/*ui14*/ _1) 
\

xen0n wrote:
> Did you actually test this? ;-)
Thank you for checking, I will modify it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139288/new/

https://reviews.llvm.org/D139288

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D139288: [Clang][LoongArch] Add intrinsic for csrrd, csrwr and csrxchg

2022-12-04 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 479967.
gonglingqin added a comment.

Address @xen0n's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139288/new/

https://reviews.llvm.org/D139288

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error-la64.c
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -6,6 +6,9 @@
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
 declare void @llvm.loongarch.syscall(i32)
+declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
+declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
+declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -46,3 +49,33 @@
   call void @llvm.loongarch.syscall(i32 1)
   ret void
 }
+
+define i32 @csrrd_w() {
+; CHECK-LABEL: csrrd_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrrd $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrrd.w(i32 1)
+  ret i32 %0
+}
+
+define i32 @csrwr_w(i32 signext %a) {
+; CHECK-LABEL: csrwr_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrwr $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1)
+  ret i32 %0
+}
+
+define i32 @csrxchg_w(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: csrxchg_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrxchg $a0, $a1, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
+  ret i32 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -9,6 +9,9 @@
 declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
+declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
+declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -81,3 +84,33 @@
   %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i64 @csrrd_d() {
+; CHECK-LABEL: csrrd_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrrd $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrrd.d(i32 1)
+  ret i64 %0
+}
+
+define i64 @csrwr_d(i64 %a) {
+; CHECK-LABEL: csrwr_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrwr $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
+  ret i64 %0
+}
+
+define i64 @csrxchg_d(i64 %a, i64 %b) {
+; CHECK-LABEL: csrxchg_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrxchg $a0, $a1, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
+  ret i64 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
+
+declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
+declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
+declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
+
+define i64 @csrrd_d_imm_out_of_hi_range() nounwind {
+; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range
+entry:
+  %0 = call i64 @llvm.loongarch.csrrd.d(i32 16384)
+  ret i64 %0
+}
+
+define i64 @csrrd_d_imm_out_of_lo_range() nounwind {
+; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range
+entry:
+  %0 = call i64 @llvm.loongarch.csrrd.d(i32 -1)
+  ret i64 %0
+}
+
+define i64 @csrwr_d_imm_out_of_hi_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.csrwr.d' out of range
+entry:
+  %0 = call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 16384)
+  ret i64 %0
+}
+
+define i64 @csrwr_d

[PATCH] D139288: [Clang][LoongArch] Add intrinsic for csrrd, csrwr and csrxchg

2022-12-04 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added inline comments.



Comment at: clang/lib/Headers/larchintrin.h:67-96
 #define __break(/*ui15*/ _1) __builtin_loongarch_break((_1))
 
 #define __dbar(/*ui15*/ _1) __builtin_loongarch_dbar((_1))
 
 #define __ibar(/*ui15*/ _1) __builtin_loongarch_ibar((_1))
 
 #define __syscall(/*ui15*/ _1) __builtin_loongarch_syscall((_1))

SixWeining wrote:
> It's better to add testcases for all these macros.
Thanks, I'll add all the macro test cases later.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139288/new/

https://reviews.llvm.org/D139288

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D139397: [LoongArch] Add testcases for privileged intrinsic macros

2022-12-06 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay, 
XiaodongLoong.
Herald added a subscriber: StephenFan.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add testcases calling macros to the implemented privileged intrinsics
as discussed in D139288 . The intrinsics 
involved include ibar, dbar,
break, syscall, and CRC check intrinsics.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139397

Files:
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  clang/test/CodeGen/LoongArch/intrinsic.c

Index: clang/test/CodeGen/LoongArch/intrinsic.c
===
--- clang/test/CodeGen/LoongArch/intrinsic.c
+++ clang/test/CodeGen/LoongArch/intrinsic.c
@@ -9,55 +9,67 @@
 // LA32-LABEL: @dbar(
 // LA32-NEXT:  entry:
 // LA32-NEXT:call void @llvm.loongarch.dbar(i32 0)
+// LA32-NEXT:call void @llvm.loongarch.dbar(i32 0)
 // LA32-NEXT:ret void
 //
 // LA64-LABEL: @dbar(
 // LA64-NEXT:  entry:
 // LA64-NEXT:call void @llvm.loongarch.dbar(i32 0)
+// LA64-NEXT:call void @llvm.loongarch.dbar(i32 0)
 // LA64-NEXT:ret void
 //
 void dbar() {
-  return __builtin_loongarch_dbar(0);
+  __dbar(0);
+  __builtin_loongarch_dbar(0);
 }
 
 // LA32-LABEL: @ibar(
 // LA32-NEXT:  entry:
 // LA32-NEXT:call void @llvm.loongarch.ibar(i32 0)
+// LA32-NEXT:call void @llvm.loongarch.ibar(i32 0)
 // LA32-NEXT:ret void
 //
 // LA64-LABEL: @ibar(
 // LA64-NEXT:  entry:
 // LA64-NEXT:call void @llvm.loongarch.ibar(i32 0)
+// LA64-NEXT:call void @llvm.loongarch.ibar(i32 0)
 // LA64-NEXT:ret void
 //
 void ibar() {
-  return __builtin_loongarch_ibar(0);
+  __ibar(0);
+  __builtin_loongarch_ibar(0);
 }
 
 // LA32-LABEL: @loongarch_break(
 // LA32-NEXT:  entry:
 // LA32-NEXT:call void @llvm.loongarch.break(i32 1)
+// LA32-NEXT:call void @llvm.loongarch.break(i32 1)
 // LA32-NEXT:ret void
 //
 // LA64-LABEL: @loongarch_break(
 // LA64-NEXT:  entry:
 // LA64-NEXT:call void @llvm.loongarch.break(i32 1)
+// LA64-NEXT:call void @llvm.loongarch.break(i32 1)
 // LA64-NEXT:ret void
 //
 void loongarch_break() {
+  __break(1);
   __builtin_loongarch_break(1);
 }
 
 // LA32-LABEL: @syscall(
 // LA32-NEXT:  entry:
 // LA32-NEXT:call void @llvm.loongarch.syscall(i32 1)
+// LA32-NEXT:call void @llvm.loongarch.syscall(i32 1)
 // LA32-NEXT:ret void
 //
 // LA64-LABEL: @syscall(
 // LA64-NEXT:  entry:
 // LA64-NEXT:call void @llvm.loongarch.syscall(i32 1)
+// LA64-NEXT:call void @llvm.loongarch.syscall(i32 1)
 // LA64-NEXT:ret void
 //
 void syscall() {
+  __syscall(1);
   __builtin_loongarch_syscall(1);
 }
Index: clang/test/CodeGen/LoongArch/intrinsic-la64.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -5,72 +5,104 @@
 
 // CHECK-LABEL: @crc_w_b_w(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.b.w(i32 [[A:%.*]], i32 [[B:%.*]])
-// CHECK-NEXT:ret i32 [[TMP0]]
+// CHECK-NEXT:[[TMP0:%.*]] = shl i32 [[A:%.*]], 24
+// CHECK-NEXT:[[CONV_I:%.*]] = ashr exact i32 [[TMP0]], 24
+// CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.crc.w.b.w(i32 [[CONV_I]], i32 [[B:%.*]])
+// CHECK-NEXT:[[TMP2:%.*]] = tail call i32 @llvm.loongarch.crc.w.b.w(i32 [[A]], i32 [[B]])
+// CHECK-NEXT:ret i32 0
 //
 int crc_w_b_w(int a, int b) {
-  return __builtin_loongarch_crc_w_b_w(a, b);
+  int c = __crc_w_b_w(a, b);
+  int d = __builtin_loongarch_crc_w_b_w(a, b);
+  return 0;
 }
 
 // CHECK-LABEL: @crc_w_h_w(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.h.w(i32 [[A:%.*]], i32 [[B:%.*]])
-// CHECK-NEXT:ret i32 [[TMP0]]
+// CHECK-NEXT:[[TMP0:%.*]] = shl i32 [[A:%.*]], 16
+// CHECK-NEXT:[[CONV_I:%.*]] = ashr exact i32 [[TMP0]], 16
+// CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.crc.w.h.w(i32 [[CONV_I]], i32 [[B:%.*]])
+// CHECK-NEXT:[[TMP2:%.*]] = tail call i32 @llvm.loongarch.crc.w.h.w(i32 [[A]], i32 [[B]])
+// CHECK-NEXT:ret i32 0
 //
 int crc_w_h_w(int a, int b) {
-  return __builtin_loongarch_crc_w_h_w(a, b);
+  int c = __crc_w_h_w(a, b);
+  int d = __builtin_loongarch_crc_w_h_w(a, b);
+  return 0;
 }
 
 // CHECK-LABEL: @crc_w_w_w(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.w.w(i32 [[A:%.*]], i32 [[B:%.*]])
-// CHECK-NEXT:ret i32 [[TMP0]]
+// CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.crc.w.w.w(i32 [[A]], i32 [[B]])
+// CHECK-NEXT:ret i32 0
 //
 int crc_w_w_w(int a, int b) {
-  return __builtin_loongarch_crc_w_w_w(a, b);
+  int c = __crc_w_w_w(a, b);
+  int d = __builtin_loongarch_crc_w_w

[PATCH] D139288: [Clang][LoongArch] Add intrinsic for csrrd, csrwr and csrxchg

2022-12-06 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 480371.
gonglingqin added a comment.

Add testcases for macros.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139288/new/

https://reviews.llvm.org/D139288

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error-la64.c
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -6,6 +6,9 @@
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
 declare void @llvm.loongarch.syscall(i32)
+declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
+declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
+declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -46,3 +49,33 @@
   call void @llvm.loongarch.syscall(i32 1)
   ret void
 }
+
+define i32 @csrrd_w() {
+; CHECK-LABEL: csrrd_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrrd $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrrd.w(i32 1)
+  ret i32 %0
+}
+
+define i32 @csrwr_w(i32 signext %a) {
+; CHECK-LABEL: csrwr_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrwr $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1)
+  ret i32 %0
+}
+
+define i32 @csrxchg_w(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: csrxchg_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrxchg $a0, $a1, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
+  ret i32 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -9,6 +9,9 @@
 declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
+declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
+declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -81,3 +84,33 @@
   %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i64 @csrrd_d() {
+; CHECK-LABEL: csrrd_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrrd $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrrd.d(i32 1)
+  ret i64 %0
+}
+
+define i64 @csrwr_d(i64 %a) {
+; CHECK-LABEL: csrwr_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrwr $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
+  ret i64 %0
+}
+
+define i64 @csrxchg_d(i64 %a, i64 %b) {
+; CHECK-LABEL: csrxchg_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrxchg $a0, $a1, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
+  ret i64 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
+
+declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
+declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
+declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
+
+define i64 @csrrd_d_imm_out_of_hi_range() nounwind {
+; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range
+entry:
+  %0 = call i64 @llvm.loongarch.csrrd.d(i32 16384)
+  ret i64 %0
+}
+
+define i64 @csrrd_d_imm_out_of_lo_range() nounwind {
+; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range
+entry:
+  %0 = call i64 @llvm.loongarch.csrrd.d(i32 -1)
+  ret i64 %0
+}
+
+define i64 @csrwr_d_imm_out_of_hi_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.csrwr.d' out of range
+entry:
+  %0 = call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 16384)
+  ret i64 %0
+}
+
+define i64 @csrwr_d_

[PATCH] D139288: [Clang][LoongArch] Add intrinsic for csrrd, csrwr and csrxchg

2022-12-07 Thread Gong LingQin via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG685bbe65f5c3: [Clang][LoongArch] Add intrinsic for csrrd, 
csrwr and csrxchg (authored by gonglingqin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139288/new/

https://reviews.llvm.org/D139288

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-error-la64.c
  clang/test/CodeGen/LoongArch/intrinsic-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  clang/test/CodeGen/LoongArch/intrinsic.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -6,6 +6,9 @@
 declare void @llvm.loongarch.ibar(i32)
 declare void @llvm.loongarch.break(i32)
 declare void @llvm.loongarch.syscall(i32)
+declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
+declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
+declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -46,3 +49,33 @@
   call void @llvm.loongarch.syscall(i32 1)
   ret void
 }
+
+define i32 @csrrd_w() {
+; CHECK-LABEL: csrrd_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrrd $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrrd.w(i32 1)
+  ret i32 %0
+}
+
+define i32 @csrwr_w(i32 signext %a) {
+; CHECK-LABEL: csrwr_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrwr $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 1)
+  ret i32 %0
+}
+
+define i32 @csrxchg_w(i32 signext %a, i32 signext %b) {
+; CHECK-LABEL: csrxchg_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrxchg $a0, $a1, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
+  ret i32 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -9,6 +9,9 @@
 declare i32 @llvm.loongarch.crcc.w.h.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.w.w(i32, i32)
 declare i32 @llvm.loongarch.crcc.w.d.w(i64, i32)
+declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
+declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
+declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -81,3 +84,33 @@
   %res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
   ret i32 %res
 }
+
+define i64 @csrrd_d() {
+; CHECK-LABEL: csrrd_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrrd $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrrd.d(i32 1)
+  ret i64 %0
+}
+
+define i64 @csrwr_d(i64 %a) {
+; CHECK-LABEL: csrwr_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrwr $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
+  ret i64 %0
+}
+
+define i64 @csrxchg_d(i64 %a, i64 %b) {
+; CHECK-LABEL: csrxchg_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:csrxchg $a0, $a1, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
+  ret i64 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
===
--- /dev/null
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
@@ -0,0 +1,48 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
+
+declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
+declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
+declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
+
+define i64 @csrrd_d_imm_out_of_hi_range() nounwind {
+; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range
+entry:
+  %0 = call i64 @llvm.loongarch.csrrd.d(i32 16384)
+  ret i64 %0
+}
+
+define i64 @csrrd_d_imm_out_of_lo_range() nounwind {
+; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range
+entry:
+  %0 = call i64 @llvm.loongarch.csrrd.d(i32 -1)
+  ret i64 %0
+}
+
+define i64 @csrwr_d_imm_out_of_hi_range(i64 %a) nounwind {
+; CHECK: argument to 'llvm.loongarch.csrwr.d' out of range
+entry:
+  %0 = ca

[PATCH] D139612: [Clang][LoongArch] Add intrinsic for iocsrrd and iocsrwr

2022-12-08 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay, 
XiaodongLoong.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

These intrinsics are required by Linux [1].

[1]: 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h#n240


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139612

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -9,6 +9,12 @@
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
 declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
+declare i32 @llvm.loongarch.iocsrrd.b(i32)
+declare i32 @llvm.loongarch.iocsrrd.h(i32)
+declare i32 @llvm.loongarch.iocsrrd.w(i32)
+declare void @llvm.loongarch.iocsrwr.b(i32, i32)
+declare void @llvm.loongarch.iocsrwr.h(i32, i32)
+declare void @llvm.loongarch.iocsrwr.w(i32, i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -79,3 +85,63 @@
   %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
   ret i32 %0
 }
+
+define i32 @iocsrrd_b(i32 %a) {
+; CHECK-LABEL: iocsrrd_b:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrrd.b $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.iocsrrd.b(i32 %a)
+  ret i32 %0
+}
+
+define i32 @iocsrrd_h(i32 %a) {
+; CHECK-LABEL: iocsrrd_h:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrrd.h $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.iocsrrd.h(i32 %a)
+  ret i32 %0
+}
+
+define i32 @iocsrrd_w(i32 %a) {
+; CHECK-LABEL: iocsrrd_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrrd.w $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.iocsrrd.w(i32 %a)
+  ret i32 %0
+}
+
+define void @iocsrwr_b(i32 %a, i32 %b) {
+; CHECK-LABEL: iocsrwr_b:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrwr.b $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.iocsrwr.b(i32 %a, i32 %b)
+  ret void
+}
+
+define void @iocsrwr_h(i32 %a, i32 %b) {
+; CHECK-LABEL: iocsrwr_h:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrwr.h $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.iocsrwr.h(i32 %a, i32 %b)
+  ret void
+}
+
+define void @iocsrwr_w(i32 %a, i32 %b) {
+; CHECK-LABEL: iocsrwr_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrwr.w $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.iocsrwr.w(i32 %a, i32 %b)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -12,6 +12,8 @@
 declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
 declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
+declare i64 @llvm.loongarch.iocsrrd.d(i32)
+declare void @llvm.loongarch.iocsrwr.d(i64, i32)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -114,3 +116,23 @@
   %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
   ret i64 %0
 }
+
+define i64 @iocsrrd_d(i32 %a) {
+; CHECK-LABEL: iocsrrd_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrrd.d $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.iocsrrd.d(i32 %a)
+  ret i64 %0
+}
+
+define void @iocsrwr_d(i64 %a, i32 signext %b) {
+; CHECK-LABEL: iocsrwr_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrwr.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -11,6 +11,8 @@
 declare i64 @llvm.loongarch.csrrd.d(i32 immar

[PATCH] D139397: [LoongArch] Add testcases for privileged intrinsic macros

2022-12-09 Thread Gong LingQin via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9a5e5402cf80: [LoongArch] Add testcases for privileged 
intrinsic macros (authored by gonglingqin).

Changed prior to commit:
  https://reviews.llvm.org/D139397?vs=480355&id=481814#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139397/new/

https://reviews.llvm.org/D139397

Files:
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c

Index: clang/test/CodeGen/LoongArch/intrinsic-la64.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -6,36 +6,44 @@
 // CHECK-LABEL: @dbar(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:tail call void @llvm.loongarch.dbar(i32 0)
+// CHECK-NEXT:tail call void @llvm.loongarch.dbar(i32 0)
 // CHECK-NEXT:ret void
 //
 void dbar() {
-  return __builtin_loongarch_dbar(0);
+  __dbar(0);
+  __builtin_loongarch_dbar(0);
 }
 
 // CHECK-LABEL: @ibar(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:tail call void @llvm.loongarch.ibar(i32 0)
+// CHECK-NEXT:tail call void @llvm.loongarch.ibar(i32 0)
 // CHECK-NEXT:ret void
 //
 void ibar() {
-  return __builtin_loongarch_ibar(0);
+  __ibar(0);
+  __builtin_loongarch_ibar(0);
 }
 
 // CHECK-LABEL: @loongarch_break(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:tail call void @llvm.loongarch.break(i32 1)
+// CHECK-NEXT:tail call void @llvm.loongarch.break(i32 1)
 // CHECK-NEXT:ret void
 //
 void loongarch_break() {
+  __break(1);
   __builtin_loongarch_break(1);
 }
 
 // CHECK-LABEL: @syscall(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:tail call void @llvm.loongarch.syscall(i32 1)
+// CHECK-NEXT:tail call void @llvm.loongarch.syscall(i32 1)
 // CHECK-NEXT:ret void
 //
 void syscall() {
+  __syscall(1);
   __builtin_loongarch_syscall(1);
 }
 
@@ -77,74 +85,106 @@
 
 // CHECK-LABEL: @crc_w_b_w(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.b.w(i32 [[A:%.*]], i32 [[B:%.*]])
-// CHECK-NEXT:ret i32 [[TMP0]]
+// CHECK-NEXT:[[TMP0:%.*]] = shl i32 [[A:%.*]], 24
+// CHECK-NEXT:[[CONV_I:%.*]] = ashr exact i32 [[TMP0]], 24
+// CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.crc.w.b.w(i32 [[CONV_I]], i32 [[B:%.*]])
+// CHECK-NEXT:[[TMP2:%.*]] = tail call i32 @llvm.loongarch.crc.w.b.w(i32 [[A]], i32 [[B]])
+// CHECK-NEXT:ret i32 0
 //
 int crc_w_b_w(int a, int b) {
-  return __builtin_loongarch_crc_w_b_w(a, b);
+  int c = __crc_w_b_w(a, b);
+  int d = __builtin_loongarch_crc_w_b_w(a, b);
+  return 0;
 }
 
 // CHECK-LABEL: @crc_w_h_w(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.h.w(i32 [[A:%.*]], i32 [[B:%.*]])
-// CHECK-NEXT:ret i32 [[TMP0]]
+// CHECK-NEXT:[[TMP0:%.*]] = shl i32 [[A:%.*]], 16
+// CHECK-NEXT:[[CONV_I:%.*]] = ashr exact i32 [[TMP0]], 16
+// CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.crc.w.h.w(i32 [[CONV_I]], i32 [[B:%.*]])
+// CHECK-NEXT:[[TMP2:%.*]] = tail call i32 @llvm.loongarch.crc.w.h.w(i32 [[A]], i32 [[B]])
+// CHECK-NEXT:ret i32 0
 //
 int crc_w_h_w(int a, int b) {
-  return __builtin_loongarch_crc_w_h_w(a, b);
+  int c = __crc_w_h_w(a, b);
+  int d = __builtin_loongarch_crc_w_h_w(a, b);
+  return 0;
 }
 
 // CHECK-LABEL: @crc_w_w_w(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.w.w(i32 [[A:%.*]], i32 [[B:%.*]])
-// CHECK-NEXT:ret i32 [[TMP0]]
+// CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.crc.w.w.w(i32 [[A]], i32 [[B]])
+// CHECK-NEXT:ret i32 0
 //
 int crc_w_w_w(int a, int b) {
-  return __builtin_loongarch_crc_w_w_w(a, b);
+  int c = __crc_w_w_w(a, b);
+  int d = __builtin_loongarch_crc_w_w_w(a, b);
+  return 0;
 }
 
 // CHECK-LABEL: @crc_w_d_w(
 // CHECK-NEXT:  entry:
 // CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.crc.w.d.w(i64 [[A:%.*]], i32 [[B:%.*]])
-// CHECK-NEXT:ret i32 [[TMP0]]
+// CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.crc.w.d.w(i64 [[A]], i32 [[B]])
+// CHECK-NEXT:ret i32 0
 //
 int crc_w_d_w(long int a, int b) {
-  return __builtin_loongarch_crc_w_d_w(a, b);
+  int c = __crc_w_d_w(a, b);
+  int d = __builtin_loongarch_crc_w_d_w(a, b);
+  return 0;
 }
 
 // CHECK-LABEL: @crcc_w_b_w(
 // CHECK-NEXT:  entry:
-// CHECK-NEXT:[[TMP0:%.*]] = tail call i32 @llvm.loongarch.crcc.w.b.w(i32 [[A:%.*]], i32 [[B:%.*]])
-// CHECK-NEXT:ret i32 [[TMP0]]
+// CHECK-NEXT:[[TMP0:%.*]] = shl i32 [[A:%.*]], 24
+// CHECK-NEXT:[[CONV_I:%.*]] = ashr exact i32 [[TMP0]], 24
+// CHECK-NEXT:[[TMP1:%.*]] = tail call i32 @llvm.loongarch.crcc.w.b.w(i32 [[CONV_I]], i32 [[B:%.*]])
+// CHECK-NEXT:[[TMP2:%.*]] = tail call i32 @llvm.loongarch.crcc.w.b.w(i32 [[A]], i32 [[B]])

[PATCH] D139612: [Clang][LoongArch] Add intrinsic for iocsrrd and iocsrwr

2022-12-09 Thread Gong LingQin via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG048612050a2f: [Clang][LoongArch] Add intrinsic for iocsrrd 
and iocsrwr (authored by gonglingqin).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139612/new/

https://reviews.llvm.org/D139612

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -9,6 +9,12 @@
 declare i32 @llvm.loongarch.csrrd.w(i32 immarg)
 declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
 declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
+declare i32 @llvm.loongarch.iocsrrd.b(i32)
+declare i32 @llvm.loongarch.iocsrrd.h(i32)
+declare i32 @llvm.loongarch.iocsrrd.w(i32)
+declare void @llvm.loongarch.iocsrwr.b(i32, i32)
+declare void @llvm.loongarch.iocsrwr.h(i32, i32)
+declare void @llvm.loongarch.iocsrwr.w(i32, i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -79,3 +85,63 @@
   %0 = tail call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 1)
   ret i32 %0
 }
+
+define i32 @iocsrrd_b(i32 %a) {
+; CHECK-LABEL: iocsrrd_b:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrrd.b $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.iocsrrd.b(i32 %a)
+  ret i32 %0
+}
+
+define i32 @iocsrrd_h(i32 %a) {
+; CHECK-LABEL: iocsrrd_h:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrrd.h $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.iocsrrd.h(i32 %a)
+  ret i32 %0
+}
+
+define i32 @iocsrrd_w(i32 %a) {
+; CHECK-LABEL: iocsrrd_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrrd.w $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.iocsrrd.w(i32 %a)
+  ret i32 %0
+}
+
+define void @iocsrwr_b(i32 %a, i32 %b) {
+; CHECK-LABEL: iocsrwr_b:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrwr.b $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.iocsrwr.b(i32 %a, i32 %b)
+  ret void
+}
+
+define void @iocsrwr_h(i32 %a, i32 %b) {
+; CHECK-LABEL: iocsrwr_h:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrwr.h $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.iocsrwr.h(i32 %a, i32 %b)
+  ret void
+}
+
+define void @iocsrwr_w(i32 %a, i32 %b) {
+; CHECK-LABEL: iocsrwr_w:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrwr.w $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.iocsrwr.w(i32 %a, i32 %b)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -12,6 +12,8 @@
 declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
 declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
+declare i64 @llvm.loongarch.iocsrrd.d(i32)
+declare void @llvm.loongarch.iocsrwr.d(i64, i32)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -114,3 +116,23 @@
   %0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
   ret i64 %0
 }
+
+define i64 @iocsrrd_d(i32 %a) {
+; CHECK-LABEL: iocsrrd_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrrd.d $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.iocsrrd.d(i32 %a)
+  ret i64 %0
+}
+
+define void @iocsrwr_d(i64 %a, i32 signext %b) {
+; CHECK-LABEL: iocsrwr_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:iocsrwr.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -11,6 +11,8 @@
 declare i64 @llvm.loongarch.csrrd.d(i32 immarg)
 declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
+declare i64 @llvm.loongarch.iocsrrd.d(i32)
+declare void @llvm.loongarch.ioc

[PATCH] D139915: [Clang][LoongArch] Add intrinsic for asrtle, asrtgt, lddir, ldpte and cpucfg

2022-12-12 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay, 
XiaodongLoong.
Herald added subscribers: StephenFan, hiraditya.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added projects: clang, LLVM.
Herald added subscribers: llvm-commits, cfe-commits.

These intrinsics are required by Linux [1].

[1]: 
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/loongarch/include/asm/loongarch.h#n59


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139915

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -15,6 +15,7 @@
 declare void @llvm.loongarch.iocsrwr.b(i32, i32)
 declare void @llvm.loongarch.iocsrwr.h(i32, i32)
 declare void @llvm.loongarch.iocsrwr.w(i32, i32)
+declare i32 @llvm.loongarch.cpucfg(i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -145,3 +146,13 @@
   tail call void @llvm.loongarch.iocsrwr.w(i32 %a, i32 %b)
   ret void
 }
+
+define i32 @cpucfg(i32 %a) {
+; CHECK-LABEL: cpucfg:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cpucfg $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.cpucfg(i32 %a)
+  ret i32 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -14,6 +14,10 @@
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i64)
+declare void @llvm.loongarch.ldpte.d(i64, i64)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -136,3 +140,43 @@
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtle_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:asrtle.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtgt_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:asrtgt.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i64 @lddir_d(i64 %a) {
+; CHECK-LABEL: lddir_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lddir $a0, $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i64 1)
+  ret i64 %0
+}
+
+define void @ldpte_d(i64 %a) {
+; CHECK-LABEL: ldpte_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ldpte $a0, 1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.ldpte.d(i64 %a, i64 1)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -13,6 +13,10 @@
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i32)
+declare void @llvm.loongarch.ldpte.d(i64, i32)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
@@ -104,3 +108,31 @@
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtle.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtgt.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i

[PATCH] D139915: [Clang][LoongArch] Add intrinsic for asrtle, asrtgt, lddir, ldpte and cpucfg

2022-12-12 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin added a comment.

In D139915#3991089 , @xen0n wrote:

> Linux only requires `__cpucfg` among the ones you just added. Please amend 
> the patch summary so it's more accurate.
>
> Otherwise LGTM, thanks!

Thanks for your review, I will modify the summary.




Comment at: llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp:797
+ASRT_LE_GT_CASE(asrtle_d)
+ASRT_LE_GT_CASE(asrtgt_d)
+  case Intrinsic::loongarch_ldpte_d: {

xen0n wrote:
> `#undef ASRT_LE_GT_CASE` afterwards?
Thanks! I will modify it. And there are other similar problems in this file, 
which I will modify later.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139915/new/

https://reviews.llvm.org/D139915

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D139915: [Clang][LoongArch] Add intrinsic for asrtle, asrtgt, lddir, ldpte and cpucfg

2022-12-12 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin updated this revision to Diff 482372.
gonglingqin added a comment.

Address @xen0n's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139915/new/

https://reviews.llvm.org/D139915

Files:
  clang/include/clang/Basic/BuiltinsLoongArch.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/larchintrin.h
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c
  llvm/include/llvm/IR/IntrinsicsLoongArch.td
  llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
  llvm/lib/Target/LoongArch/LoongArchISelLowering.h
  llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
  llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
  llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
  llvm/test/CodeGen/LoongArch/intrinsic.ll

Index: llvm/test/CodeGen/LoongArch/intrinsic.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic.ll
@@ -15,6 +15,7 @@
 declare void @llvm.loongarch.iocsrwr.b(i32, i32)
 declare void @llvm.loongarch.iocsrwr.h(i32, i32)
 declare void @llvm.loongarch.iocsrwr.w(i32, i32)
+declare i32 @llvm.loongarch.cpucfg(i32)
 
 define void @foo() nounwind {
 ; CHECK-LABEL: foo:
@@ -145,3 +146,13 @@
   tail call void @llvm.loongarch.iocsrwr.w(i32 %a, i32 %b)
   ret void
 }
+
+define i32 @cpucfg(i32 %a) {
+; CHECK-LABEL: cpucfg:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:cpucfg $a0, $a0
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i32 @llvm.loongarch.cpucfg(i32 %a)
+  ret i32 %0
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la64.ll
@@ -14,6 +14,10 @@
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i64)
+declare void @llvm.loongarch.ldpte.d(i64, i64)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK-LABEL: crc_w_b_w:
@@ -136,3 +140,43 @@
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtle_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:asrtle.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK-LABEL: asrtgt_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:asrtgt.d $a0, $a1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i64 @lddir_d(i64 %a) {
+; CHECK-LABEL: lddir_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:lddir $a0, $a0, 1
+; CHECK-NEXT:ret
+entry:
+  %0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i64 1)
+  ret i64 %0
+}
+
+define void @ldpte_d(i64 %a) {
+; CHECK-LABEL: ldpte_d:
+; CHECK:   # %bb.0: # %entry
+; CHECK-NEXT:ldpte $a0, 1
+; CHECK-NEXT:ret
+entry:
+  tail call void @llvm.loongarch.ldpte.d(i64 %a, i64 1)
+  ret void
+}
Index: llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
===
--- llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -13,6 +13,10 @@
 declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
 declare i64 @llvm.loongarch.iocsrrd.d(i32)
 declare void @llvm.loongarch.iocsrwr.d(i64, i32)
+declare void @llvm.loongarch.asrtle.d(i64, i64)
+declare void @llvm.loongarch.asrtgt.d(i64, i64)
+declare i64 @llvm.loongarch.lddir.d(i64, i32)
+declare void @llvm.loongarch.ldpte.d(i64, i32)
 
 define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
 ; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
@@ -104,3 +108,31 @@
   tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
   ret void
 }
+
+define void @asrtle_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtle.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
+  ret void
+}
+
+define void @asrtgt_d(i64 %a, i64 %b) {
+; CHECK: llvm.loongarch.asrtgt.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
+  ret void
+}
+
+define i64 @lddir_d(i64 %a) {
+; CHECK: llvm.loongarch.lddir.d requires target: loongarch64
+entry:
+  %0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i32 1)
+  ret i64 %0
+}
+
+define void @ldpte_d(i64 %a) {
+; CHECK: llvm.loongarch.ldpte.d requires target: loongarch64
+entry:
+  tail call void @llvm.loongarch.ldpte.d(i64 %a, i32 1)
+

[PATCH] D139987: [Clang][LoongArch] Add intrinsic for rdtime_d, rdtimeh_w and rdtimel_w

2022-12-13 Thread Gong LingQin via Phabricator via cfe-commits

gonglingqin created this revision.
gonglingqin added reviewers: xen0n, xry111, SixWeining, wangleiat, MaskRay, 
XiaodongLoong.
Herald added a subscriber: StephenFan.
Herald added a project: All.
gonglingqin requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Add these intrinsics to keep consistent with GCC [1].

[1]: 
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/loongarch/larchintrin.h#L33


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139987

Files:
  clang/lib/Headers/larchintrin.h
  clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
  clang/test/CodeGen/LoongArch/intrinsic-la32.c
  clang/test/CodeGen/LoongArch/intrinsic-la64.c

Index: clang/test/CodeGen/LoongArch/intrinsic-la64.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la64.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la64.c
@@ -316,3 +316,23 @@
   __iocsrwr_d(a, b);
   __builtin_loongarch_iocsrwr_d(a, b);
 }
+
+// CHECK-LABEL: @rdtime_d(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call { i64, i64 } asm sideeffect "rdtime.d $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// CHECK-NEXT:ret void
+//
+void rdtime_d() {
+  __rdtime_d();
+}
+
+// CHECK-LABEL: @rdtime(
+// CHECK-NEXT:  entry:
+// CHECK-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// CHECK-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !4
+// CHECK-NEXT:ret void
+//
+void rdtime() {
+  __rdtimeh_w();
+  __rdtimel_w();
+}
Index: clang/test/CodeGen/LoongArch/intrinsic-la32.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la32.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la32.c
@@ -154,3 +154,14 @@
   __iocsrwr_w(a, b);
   __builtin_loongarch_iocsrwr_w(a, b);
 }
+
+// LA32-LABEL: @rdtime(
+// LA32-NEXT:  entry:
+// LA32-NEXT:[[TMP0:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimeh.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1:[0-9]+]], !srcloc !2
+// LA32-NEXT:[[TMP1:%.*]] = tail call { i32, i32 } asm sideeffect "rdtimel.w $0, $1\0A\09", "=&r,=&r"() #[[ATTR1]], !srcloc !3
+// LA32-NEXT:ret void
+//
+void rdtime() {
+  __rdtimeh_w();
+  __rdtimel_w();
+}
Index: clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
===
--- clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
+++ clang/test/CodeGen/LoongArch/intrinsic-la32-error.c
@@ -95,3 +95,7 @@
 void iocsrwr_d(unsigned long int a, unsigned int b) {
   __builtin_loongarch_iocsrwr_d(a, b); // expected-error {{this builtin requires target: loongarch64}}
 }
+
+void rdtime_d() {
+  __rdtime_d(); // expected-error {{call to undeclared function '__rdtime_d'}}
+}
Index: clang/lib/Headers/larchintrin.h
===
--- clang/lib/Headers/larchintrin.h
+++ clang/lib/Headers/larchintrin.h
@@ -14,6 +14,46 @@
 extern "C" {
 #endif
 
+typedef struct drdtime {
+  unsigned long dvalue;
+  unsigned long dtimeid;
+} __drdtime_t;
+
+typedef struct rdtime {
+  unsigned int value;
+  unsigned int timeid;
+} __rdtime_t;
+
+#if __loongarch_grlen == 64
+extern __inline __drdtime_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__rdtime_d(void) {
+  __drdtime_t __drdtime;
+  __asm__ volatile(
+  "rdtime.d %[val], %[tid]\n\t"
+  : [val] "=&r"(__drdtime.dvalue), [tid] "=&r"(__drdtime.dtimeid));
+  return __drdtime;
+}
+#endif
+
+extern __inline __rdtime_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__rdtimeh_w(void) {
+  __rdtime_t __rdtime;
+  __asm__ volatile("rdtimeh.w %[val], %[tid]\n\t"
+   : [val] "=&r"(__rdtime.value), [tid] "=&r"(__rdtime.timeid));
+  return __rdtime;
+}
+
+extern __inline __rdtime_t
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+__rdtimel_w(void) {
+  __rdtime_t __rdtime;
+  __asm__ volatile("rdtimel.w %[val], %[tid]\n\t"
+   : [val] "=&r"(__rdtime.value), [tid] "=&r"(__rdtime.timeid));
+  return __rdtime;
+}
+
 #if __loongarch_grlen == 64
 extern __inline int
 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

57 matches

Mail list logo