r334116 - [PATCH 2/2] [test] Add support for Samsung Exynos M4 (NFC)

2018-06-06 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Wed Jun  6 11:58:01 2018
New Revision: 334116

URL: http://llvm.org/viewvc/llvm-project?rev=334116&view=rev
Log:
[PATCH 2/2] [test] Add support for Samsung Exynos M4 (NFC)

Add test cases for Exynos M4.

Modified:
cfe/trunk/test/CodeGen/arm-target-features.c
cfe/trunk/test/Driver/aarch64-cpus.c
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Preprocessor/aarch64-target-features.c
cfe/trunk/test/Preprocessor/arm-target-features.c

Modified: cfe/trunk/test/CodeGen/arm-target-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-target-features.c?rev=334116&r1=334115&r2=334116&view=diff
==
--- cfe/trunk/test/CodeGen/arm-target-features.c (original)
+++ cfe/trunk/test/CodeGen/arm-target-features.c Wed Jun  6 11:58:01 2018
@@ -28,6 +28,7 @@
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m1 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m2 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m3 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m4 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // CHECK-BASIC-V8: 
"target-features"="+armv8-a,+crc,+crypto,+dsp,+fp-armv8,+hwdiv,+hwdiv-arm,+neon,+thumb-mode"
 
 // RUN: %clang_cc1 -triple armv8-linux-gnueabi -target-cpu cortex-a53 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8-ARM

Modified: cfe/trunk/test/Driver/aarch64-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=334116&r1=334115&r2=334116&view=diff
==
--- cfe/trunk/test/Driver/aarch64-cpus.c (original)
+++ cfe/trunk/test/Driver/aarch64-cpus.c Wed Jun  6 11:58:01 2018
@@ -155,6 +155,15 @@
 // M3: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m3"
 // M3-TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic"
 
+// RUN: %clang -target aarch64_be -mcpu=exynos-m4 -### -c %s 2>&1 | FileCheck 
-check-prefix=M4 %s
+// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m4 -### -c %s 2>&1 | 
FileCheck -check-prefix=M4 %s
+// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m4 -### -c %s 2>&1 
| FileCheck -check-prefix=M4 %s
+// RUN: %clang -target aarch64_be -mtune=exynos-m4 -### -c %s 2>&1 | FileCheck 
-check-prefix=M4-TUNE %s
+// RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m4 -### -c %s 2>&1 | 
FileCheck -check-prefix=M4-TUNE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m4 -### -c %s 
2>&1 | FileCheck -check-prefix=M4-TUNE %s
+// M4: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m4"
+// M4-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
+
 // RUN: %clang -target arm64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M1-TUNE %s
@@ -176,6 +185,13 @@
 // ARM64-M3: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m3"
 // ARM64-M3-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
 
+// RUN: %clang -target arm64 -mcpu=exynos-m4 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M4 %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m4 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M4 %s
+// RUN: %clang -target arm64 -mtune=exynos-m4 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M4-TUNE %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=exynos-m4 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-M4-TUNE %s
+// ARM64-M4: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m4"
+// ARM64-M4-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
+
 // RUN: %clang -target aarch64 -mcpu=falkor -### -c %s 2>&1 | FileCheck 
-check-prefix=FALKOR %s
 // RUN: %clang -target aarch64 -mlittle-endian -mcpu=falkor -### -c %s 2>&1 | 
FileCheck -check-prefix=FALKOR %s
 // RUN: %clang -target aarch64 -mtune=falkor -### -c %s 2>&1 | FileCheck 
-check-prefix=FALKOR-TUNE %s
@@ -308,6 +324,15 @@
 // M3-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m3"
 // M3-BE-TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" 
"generic"
 
+// RUN: %clang -target aarch64_be -mcpu=exynos-m4 -### -c %s 2>&1 | FileCheck 
-check-prefix=M4-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m4 -### -c %s 2>&1 | 
FileCheck -check-prefix=M4-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m4 -### -c %s 2>&1 
| FileCheck -check-

r350954 - [test] Update support for Exynos M4 (NFC)

2019-01-11 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Fri Jan 11 10:54:41 2019
New Revision: 350954

URL: http://llvm.org/viewvc/llvm-project?rev=350954&view=rev
Log:
[test] Update support for Exynos M4 (NFC)

Update test cases for Exynos M4.

Modified:
cfe/trunk/test/CodeGen/arm-target-features.c
cfe/trunk/test/Driver/aarch64-cpus.c
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Preprocessor/aarch64-target-features.c

Modified: cfe/trunk/test/CodeGen/arm-target-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-target-features.c?rev=350954&r1=350953&r2=350954&view=diff
==
--- cfe/trunk/test/CodeGen/arm-target-features.c (original)
+++ cfe/trunk/test/CodeGen/arm-target-features.c Fri Jan 11 10:54:41 2019
@@ -28,9 +28,11 @@
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m1 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m2 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m3 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
-// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m4 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // CHECK-BASIC-V8: 
"target-features"="+armv8-a,+crc,+crypto,+dsp,+fp-armv8,+hwdiv,+hwdiv-arm,+neon,+thumb-mode"
 
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m4 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V82
+// CHECK-BASIC-V82: 
"target-features"="+armv8.2-a,+crc,+crypto,+dotprod,+dsp,+fp-armv8,+hwdiv,+hwdiv-arm,+neon,+ras,+thumb-mode"
+
 // RUN: %clang_cc1 -triple armv8-linux-gnueabi -target-cpu cortex-a53 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8-ARM
 // CHECK-BASIC-V8-ARM: 
"target-features"="+armv8-a,+crc,+crypto,+dsp,+fp-armv8,+hwdiv,+hwdiv-arm,+neon,-thumb-mode"
 

Modified: cfe/trunk/test/Driver/aarch64-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=350954&r1=350953&r2=350954&view=diff
==
--- cfe/trunk/test/Driver/aarch64-cpus.c (original)
+++ cfe/trunk/test/Driver/aarch64-cpus.c Fri Jan 11 10:54:41 2019
@@ -169,8 +169,9 @@
 // RUN: %clang -target aarch64_be -mtune=exynos-m4 -### -c %s 2>&1 | FileCheck 
-check-prefix=M4-TUNE %s
 // RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m4 -### -c %s 2>&1 | 
FileCheck -check-prefix=M4-TUNE %s
 // RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m4 -### -c %s 
2>&1 | FileCheck -check-prefix=M4-TUNE %s
-// M4: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m4"
+// M4: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m4" 
"-target-feature" "+v8.2a"
 // M4-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
+// M4-TUNE-NOT: "+v8.2a"
 
 // RUN: %clang -target arm64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M1 %s
@@ -197,8 +198,9 @@
 // RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m4 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M4 %s
 // RUN: %clang -target arm64 -mtune=exynos-m4 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M4-TUNE %s
 // RUN: %clang -target arm64 -mlittle-endian -mtune=exynos-m4 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-M4-TUNE %s
-// ARM64-M4: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m4"
+// ARM64-M4: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m4" 
"-target-feature" "+v8.2a"
 // ARM64-M4-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
+// ARM64-M4-TUNE-NOT: "+v8.2a"
 
 // RUN: %clang -target aarch64 -mcpu=falkor -### -c %s 2>&1 | FileCheck 
-check-prefix=FALKOR %s
 // RUN: %clang -target aarch64 -mlittle-endian -mcpu=falkor -### -c %s 2>&1 | 
FileCheck -check-prefix=FALKOR %s
@@ -338,8 +340,9 @@
 // RUN: %clang -target aarch64_be -mtune=exynos-m4 -### -c %s 2>&1 | FileCheck 
-check-prefix=M4-BE-TUNE %s
 // RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m4 -### -c %s 2>&1 | 
FileCheck -check-prefix=M4-BE-TUNE %s
 // RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m4 -### -c %s 
2>&1 | FileCheck -check-prefix=M4-BE-TUNE %s
-// M4-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m4"
+// M4-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m4" 
"-target-feature" "+v8.2a"
 // M4-BE-TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" 
"generic"
+// M4-BE-TUNE-NOT: "+v8.2a"
 
 // RUN: %clang -target aarch64_be -mcpu=thunderx2t99 -### -c %s 2>&1 | 
FileCheck -check-prefix=THUNDERX2T99-BE %s
 // RUN: %clang -target aarch64 -mbig-endian -mcpu=thunderx2t99 -### -c %s

r356794 - [clang] Add support for Exynos M5 (NFC)

2019-03-22 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Fri Mar 22 11:44:09 2019
New Revision: 356794

URL: http://llvm.org/viewvc/llvm-project?rev=356794&view=rev
Log:
[clang] Add support for Exynos M5 (NFC)

Add Exynos M5 test cases.

Modified:
cfe/trunk/test/CodeGen/arm-target-features.c
cfe/trunk/test/Driver/aarch64-cpus.c
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Preprocessor/aarch64-target-features.c
cfe/trunk/test/Preprocessor/arm-target-features.c

Modified: cfe/trunk/test/CodeGen/arm-target-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-target-features.c?rev=356794&r1=356793&r2=356794&view=diff
==
--- cfe/trunk/test/CodeGen/arm-target-features.c (original)
+++ cfe/trunk/test/CodeGen/arm-target-features.c Fri Mar 22 11:44:09 2019
@@ -31,6 +31,7 @@
 // CHECK-BASIC-V8: 
"target-features"="+armv8-a,+crc,+crypto,+dsp,+fp-armv8,+hwdiv,+hwdiv-arm,+neon,+thumb-mode"
 
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m4 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V82
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m5 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V82
 // CHECK-BASIC-V82: 
"target-features"="+armv8.2-a,+crc,+crypto,+dotprod,+dsp,+fp-armv8,+hwdiv,+hwdiv-arm,+neon,+ras,+thumb-mode"
 
 // RUN: %clang_cc1 -triple armv8-linux-gnueabi -target-cpu cortex-a53 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8-ARM

Modified: cfe/trunk/test/Driver/aarch64-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=356794&r1=356793&r2=356794&view=diff
==
--- cfe/trunk/test/Driver/aarch64-cpus.c (original)
+++ cfe/trunk/test/Driver/aarch64-cpus.c Fri Mar 22 11:44:09 2019
@@ -189,6 +189,16 @@
 // M4-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
 // M4-TUNE-NOT: "+v8.2a"
 
+// RUN: %clang -target aarch64_be -mcpu=exynos-m5 -### -c %s 2>&1 | FileCheck 
-check-prefix=M5 %s
+// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m5 -### -c %s 2>&1 | 
FileCheck -check-prefix=M5 %s
+// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m5 -### -c %s 2>&1 
| FileCheck -check-prefix=M5 %s
+// RUN: %clang -target aarch64_be -mtune=exynos-m5 -### -c %s 2>&1 | FileCheck 
-check-prefix=M5-TUNE %s
+// RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m5 -### -c %s 2>&1 | 
FileCheck -check-prefix=M5-TUNE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m5 -### -c %s 
2>&1 | FileCheck -check-prefix=M5-TUNE %s
+// M5: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m5" 
"-target-feature" "+v8.2a"
+// M5-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic"
+// M5-TUNE-NOT: "+v8.2a"
+
 // RUN: %clang -target arm64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M1-TUNE %s
@@ -218,6 +228,14 @@
 // ARM64-M4-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
 // ARM64-M4-TUNE-NOT: "+v8.2a"
 
+// RUN: %clang -target arm64 -mcpu=exynos-m5 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M5 %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m5 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M5 %s
+// RUN: %clang -target arm64 -mtune=exynos-m5 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M5-TUNE %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=exynos-m5 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-M5-TUNE %s
+// ARM64-M5: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m5" 
"-target-feature" "+v8.2a"
+// ARM64-M5-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic"
+// ARM64-M5-TUNE-NOT: "+v8.2a"
+
 // RUN: %clang -target aarch64 -mcpu=falkor -### -c %s 2>&1 | FileCheck 
-check-prefix=FALKOR %s
 // RUN: %clang -target aarch64 -mlittle-endian -mcpu=falkor -### -c %s 2>&1 | 
FileCheck -check-prefix=FALKOR %s
 // RUN: %clang -target aarch64 -mtune=falkor -### -c %s 2>&1 | FileCheck 
-check-prefix=FALKOR-TUNE %s
@@ -360,6 +378,16 @@
 // M4-BE-TUNE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" 
"generic"
 // M4-BE-TUNE-NOT: "+v8.2a"
 
+// RUN: %clang -target aarch64_be -mcpu=exynos-m5 -### -c %s 2>&1 | FileCheck 
-check-prefix=M5-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m5 -### -c %s 2>&1 | 
FileCheck -check-prefix=M5-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m5 -### -c %s 2>&1 
| FileCheck -check-prefix=M5-BE %s
+// RUN: %clang -target aarch64_be -mtune=exynos-m5 -### -c %s 2>&1 | FileCheck 
-check-prefix=M5-BE-TUNE %s
+// RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m5 -### -c %s 2>

r356920 - [clang] Remove cmake warning message (NFC)

2019-03-25 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Mon Mar 25 09:38:48 2019
New Revision: 356920

URL: http://llvm.org/viewvc/llvm-project?rev=356920&view=rev
Log:
[clang] Remove cmake warning message (NFC)

Recognize an empty string for CLANG_DEFAULT_UNWINDLIB as a valid option.

Modified:
cfe/trunk/CMakeLists.txt

Modified: cfe/trunk/CMakeLists.txt
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/CMakeLists.txt?rev=356920&r1=356919&r2=356920&view=diff
==
--- cfe/trunk/CMakeLists.txt (original)
+++ cfe/trunk/CMakeLists.txt Mon Mar 25 09:38:48 2019
@@ -276,7 +276,8 @@ if (CLANG_DEFAULT_UNWINDLIB STREQUAL "")
   endif()
 endif()
 
-if (NOT(CLANG_DEFAULT_UNWINDLIB STREQUAL "none" OR
+if (NOT(CLANG_DEFAULT_UNWINDLIB STREQUAL "" OR
+CLANG_DEFAULT_UNWINDLIB STREQUAL "none" OR
 CLANG_DEFAULT_UNWINDLIB STREQUAL "libgcc" OR
 CLANG_DEFAULT_UNWINDLIB STREQUAL "libunwind"))
   message(WARNING "Resetting default unwindlib to use platform default")


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r357638 - [IR] Create new method in `Function` class (NFC)

2019-04-03 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Wed Apr  3 14:27:03 2019
New Revision: 357638

URL: http://llvm.org/viewvc/llvm-project?rev=357638&view=rev
Log:
[IR] Create new method in `Function` class (NFC)

Create method `optForNone()` testing for the function level equivalent of
`-O0` and refactor appropriately.

Differential revision: https://reviews.llvm.org/D59852

Modified:
cfe/trunk/lib/CodeGen/CGCall.cpp

Modified: cfe/trunk/lib/CodeGen/CGCall.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGCall.cpp?rev=357638&r1=357637&r2=357638&view=diff
==
--- cfe/trunk/lib/CodeGen/CGCall.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGCall.cpp Wed Apr  3 14:27:03 2019
@@ -1809,8 +1809,7 @@ void CodeGenModule::ConstructDefaultFnAt
 
 void CodeGenModule::AddDefaultFnAttrs(llvm::Function &F) {
   llvm::AttrBuilder FuncAttrs;
-  ConstructDefaultFnAttrList(F.getName(),
- F.hasFnAttribute(llvm::Attribute::OptimizeNone),
+  ConstructDefaultFnAttrList(F.getName(), F.optForNone(),
  /* AttrOnCallsite = */ false, FuncAttrs);
   F.addAttributes(llvm::AttributeList::FunctionIndex, FuncAttrs);
 }


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r357731 - [IR] Refactor attribute methods in Function class (NFC)

2019-04-04 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Thu Apr  4 15:40:06 2019
New Revision: 357731

URL: http://llvm.org/viewvc/llvm-project?rev=357731&view=rev
Log:
[IR] Refactor attribute methods in Function class (NFC)

Rename the functions that query the optimization kind attributes.

Differential revision: https://reviews.llvm.org/D60287

Modified:
cfe/trunk/lib/CodeGen/CGCall.cpp

Modified: cfe/trunk/lib/CodeGen/CGCall.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGCall.cpp?rev=357731&r1=357730&r2=357731&view=diff
==
--- cfe/trunk/lib/CodeGen/CGCall.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGCall.cpp Thu Apr  4 15:40:06 2019
@@ -1809,7 +1809,7 @@ void CodeGenModule::ConstructDefaultFnAt
 
 void CodeGenModule::AddDefaultFnAttrs(llvm::Function &F) {
   llvm::AttrBuilder FuncAttrs;
-  ConstructDefaultFnAttrList(F.getName(), F.optForNone(),
+  ConstructDefaultFnAttrList(F.getName(), F.hasOptNone(),
  /* AttrOnCallsite = */ false, FuncAttrs);
   F.addAttributes(llvm::AttributeList::FunctionIndex, FuncAttrs);
 }


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[clang] a000580 - [RISCV] Update driver tests

2020-09-25 Thread Evandro Menezes via cfe-commits 

Author: Evandro Menezes
Date: 2020-09-25T18:36:53-05:00
New Revision: a000580a89718a1ff27a3129e34367b9a3fa1730

URL: 
https://github.com/llvm/llvm-project/commit/a000580a89718a1ff27a3129e34367b9a3fa1730
DIFF: 
https://github.com/llvm/llvm-project/commit/a000580a89718a1ff27a3129e34367b9a3fa1730.diff

LOG: [RISCV] Update driver tests

Add the RISC-V Bullet core to the driver tests.

Added: 


Modified: 
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c

Removed: 




diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index c6281a0b6433..c22f6cce2cf6 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -1,11 +1,18 @@
 // Check target CPUs are correctly passed.
 
-// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck 
-check-prefix=MCPU-ROCKETCHIP32 %s
-// MCPU-ROCKETCHIP32: "-nostdsysteminc" "-target-cpu" "rocket-rv32"
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck 
-check-prefix=MCPU-ROCKET32 %s
+// MCPU-ROCKET32: "-nostdsysteminc" "-target-cpu" "rocket-rv32"
 
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck 
-check-prefix=MCPU-ROCKETCHIP64 %s
-// MCPU-ROCKETCHIP64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
-// MCPU-ROCKETCHIP64: "-target-feature" "+64bit"
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck 
-check-prefix=MCPU-ROCKET64 %s
+// MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
+// MCPU-ROCKET64: "-target-feature" "+64bit"
+
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=bullet-rv32 | FileCheck 
-check-prefix=MCPU-BULLET32 %s
+// MCPU-BULLET32: "-nostdsysteminc" "-target-cpu" "bullet-rv32"
+
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=bullet-rv64 | FileCheck 
-check-prefix=MCPU-BULLET64 %s
+// MCPU-BULLET64: "-nostdsysteminc" "-target-cpu" "bullet-rv64"
+// MCPU-BULLET64: "-target-feature" "+64bit"
 
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck 
-check-prefix=MCPU-SIFIVE-U54 %s

diff  --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index 546ab6341f97..efcecbbc4726 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -191,8 +191,8 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-e31
+// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, 
bullet-rv32, sifive-e31
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-u54
+// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
bullet-rv64, sifive-u54



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[clang] a0a8f83 - [PATCH] Fix typo (NFC)

2020-10-02 Thread Evandro Menezes via cfe-commits 

Author: Evandro Menezes
Date: 2020-10-02T21:19:14-05:00
New Revision: a0a8f83718454186686f9c11db72408cc36482e3

URL: 
https://github.com/llvm/llvm-project/commit/a0a8f83718454186686f9c11db72408cc36482e3
DIFF: 
https://github.com/llvm/llvm-project/commit/a0a8f83718454186686f9c11db72408cc36482e3.diff

LOG: [PATCH] Fix typo (NFC)

Added: 


Modified: 
clang/test/Driver/riscv-cpus.c

Removed: 




diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index c22f6cce2cf6..15cd212e4fb4 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -28,7 +28,7 @@
 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
 // MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"
 
-// march overwirte mcpu's default march
+// march overwrite mcpu's default march
 // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc 
| FileCheck -check-prefix=MCPU-MARCH %s
 // MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" 
"+m" "-target-feature" "+c"
 // MCPU-MARCH: "-target-abi" "ilp32"



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[clang] 5d6d8a2 - [RISCV] Add SiFive cores to the CPU option

2020-10-05 Thread Evandro Menezes via cfe-commits 

Author: Evandro Menezes
Date: 2020-10-05T15:50:57-05:00
New Revision: 5d6d8a2769b3a91fd65b125c2cda64ea27a894bf

URL: 
https://github.com/llvm/llvm-project/commit/5d6d8a2769b3a91fd65b125c2cda64ea27a894bf
DIFF: 
https://github.com/llvm/llvm-project/commit/5d6d8a2769b3a91fd65b125c2cda64ea27a894bf.diff

LOG: [RISCV] Add SiFive cores to the CPU option

Add the SiFive cores E76 and U74 using the SiFive 7 series microarchitecture.

Differential Revision: https://reviews.llvm.org/D88759

Added: 


Modified: 
clang/test/Driver/riscv-cpus.c
clang/test/Misc/target-invalid-cpu-note.c
llvm/include/llvm/Support/RISCVTargetParser.def
llvm/lib/Target/RISCV/RISCV.td

Removed: 




diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 15cd212e4fb4..2bd0b26f3caf 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -7,12 +7,12 @@
 // MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64"
 // MCPU-ROCKET64: "-target-feature" "+64bit"
 
-// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=bullet-rv32 | FileCheck 
-check-prefix=MCPU-BULLET32 %s
-// MCPU-BULLET32: "-nostdsysteminc" "-target-cpu" "bullet-rv32"
+// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-7-rv32 | FileCheck 
-check-prefix=MCPU-SIFIVE7-32 %s
+// MCPU-SIFIVE7-32: "-nostdsysteminc" "-target-cpu" "sifive-7-rv32"
 
-// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=bullet-rv64 | FileCheck 
-check-prefix=MCPU-BULLET64 %s
-// MCPU-BULLET64: "-nostdsysteminc" "-target-cpu" "bullet-rv64"
-// MCPU-BULLET64: "-target-feature" "+64bit"
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-7-rv64 | FileCheck 
-check-prefix=MCPU-SIFIVE7-64 %s
+// MCPU-SIFIVE7-64: "-nostdsysteminc" "-target-cpu" "sifive-7-rv64"
+// MCPU-SIFIVE7-64: "-target-feature" "+64bit"
 
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck 
-check-prefix=MCPU-SIFIVE-U54 %s
@@ -28,6 +28,20 @@
 // MCPU-ABI-SIFIVE-U54: "-target-feature" "+c" "-target-feature" "+64bit"
 // MCPU-ABI-SIFIVE-U54: "-target-abi" "lp64"
 
+// mcpu with default march
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | FileCheck 
-check-prefix=MCPU-SIFIVE-E76 %s
+// MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76"
+// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-E76: "-target-feature" "+c"
+// MCPU-SIFIVE-E76: "-target-abi" "lp64d"
+
+// mcpu with mabi option
+// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s
+// MCPU-ABI-SIFIVE-U74: "-nostdsysteminc" "-target-cpu" "sifive-u74"
+// MCPU-ABI-SIFIVE-U74: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-ABI-SIFIVE-U74: "-target-feature" "+c" "-target-feature" "+64bit"
+// MCPU-ABI-SIFIVE-U74: "-target-abi" "lp64"
+
 // march overwrite mcpu's default march
 // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=sifive-e31 -march=rv32imc 
| FileCheck -check-prefix=MCPU-MARCH %s
 // MCPU-MARCH: "-nostdsysteminc" "-target-cpu" "sifive-e31" "-target-feature" 
"+m" "-target-feature" "+c"

diff  --git a/clang/test/Misc/target-invalid-cpu-note.c 
b/clang/test/Misc/target-invalid-cpu-note.c
index efcecbbc4726..309cb637c0c5 100644
--- a/clang/test/Misc/target-invalid-cpu-note.c
+++ b/clang/test/Misc/target-invalid-cpu-note.c
@@ -191,8 +191,8 @@
 
 // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV32
 // RISCV32: error: unknown target CPU 'not-a-cpu'
-// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, 
bullet-rv32, sifive-e31
+// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, 
sifive-7-rv32, sifive-e31, sifive-e76
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 
2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
bullet-rv64, sifive-u54
+// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, 
sifive-7-rv64, sifive-u54, sifive-u74

diff  --git a/llvm/include/llvm/Support/RISCVTargetParser.def 
b/llvm/include/llvm/Support/RISCVTargetParser.def
index e6003a4fdebb..a63874fa5dd0 100644
--- a/llvm/include/llvm/Support/RISCVTargetParser.def
+++ b/llvm/include/llvm/Support/RISCVTargetParser.def
@@ -7,9 +7,11 @@ PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
 PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
 PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
 PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
-PROC(BULLET_RV32, {"bullet-rv32"}, FK_NONE, {""})
-PROC(BULLET_RV64, {"bullet-rv64"}, FK_64BIT, {""})
+PROC(BULLET_RV32, {"sifive-7-rv3

[clang] a48d480 - [RISCV] Fix broken test

2020-10-05 Thread Evandro Menezes via cfe-commits 

Author: Evandro Menezes
Date: 2020-10-05T19:28:31-05:00
New Revision: a48d480e1f7ebc5d5f93507fe1f519496621e259

URL: 
https://github.com/llvm/llvm-project/commit/a48d480e1f7ebc5d5f93507fe1f519496621e259
DIFF: 
https://github.com/llvm/llvm-project/commit/a48d480e1f7ebc5d5f93507fe1f519496621e259.diff

LOG: [RISCV] Fix broken test

Fix test for the SiFive E76 core.

This patch fixes the issue introduced by the commit 5d6d8a2769.

Added: 


Modified: 
clang/test/Driver/riscv-cpus.c
llvm/include/llvm/Support/RISCVTargetParser.def

Removed: 




diff  --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c
index 2bd0b26f3caf..d551529f7827 100644
--- a/clang/test/Driver/riscv-cpus.c
+++ b/clang/test/Driver/riscv-cpus.c
@@ -31,9 +31,9 @@
 // mcpu with default march
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-e76 | FileCheck 
-check-prefix=MCPU-SIFIVE-E76 %s
 // MCPU-SIFIVE-E76: "-nostdsysteminc" "-target-cpu" "sifive-e76"
-// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SIFIVE-E76: "-target-feature" "+m" "-target-feature" "+a" 
"-target-feature" "+f"
 // MCPU-SIFIVE-E76: "-target-feature" "+c"
-// MCPU-SIFIVE-E76: "-target-abi" "lp64d"
+// MCPU-SIFIVE-E76: "-target-abi" "ilp32"
 
 // mcpu with mabi option
 // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u74 -mabi=lp64 | 
FileCheck -check-prefix=MCPU-ABI-SIFIVE-U74 %s

diff  --git a/llvm/include/llvm/Support/RISCVTargetParser.def 
b/llvm/include/llvm/Support/RISCVTargetParser.def
index a63874fa5dd0..53eebcf328d3 100644
--- a/llvm/include/llvm/Support/RISCVTargetParser.def
+++ b/llvm/include/llvm/Support/RISCVTargetParser.def
@@ -7,8 +7,8 @@ PROC(GENERIC_RV32, {"generic-rv32"}, FK_NONE, {""})
 PROC(GENERIC_RV64, {"generic-rv64"}, FK_64BIT, {""})
 PROC(ROCKET_RV32, {"rocket-rv32"}, FK_NONE, {""})
 PROC(ROCKET_RV64, {"rocket-rv64"}, FK_64BIT, {""})
-PROC(BULLET_RV32, {"sifive-7-rv32"}, FK_NONE, {""})
-PROC(BULLET_RV64, {"sifive-7-rv64"}, FK_64BIT, {""})
+PROC(SIFIVE_732, {"sifive-7-rv32"}, FK_NONE, {""})
+PROC(SIFIVE_764, {"sifive-7-rv64"}, FK_64BIT, {""})
 PROC(SIFIVE_E31, {"sifive-e31"}, FK_NONE, {"rv32imac"})
 PROC(SIFIVE_U54, {"sifive-u54"}, FK_64BIT, {"rv64gc"})
 PROC(SIFIVE_E76, {"sifive-e76"}, FK_NONE, {"rv32imafc"})



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r289614 - Add support for Samsung Exynos M3 (NFC)

2016-12-13 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Tue Dec 13 17:31:57 2016
New Revision: 289614

URL: http://llvm.org/viewvc/llvm-project?rev=289614&view=rev
Log:
Add support for Samsung Exynos M3 (NFC)

Modified:
cfe/trunk/test/CodeGen/arm-target-features.c
cfe/trunk/test/Driver/aarch64-cpus.c
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Preprocessor/aarch64-target-features.c

Modified: cfe/trunk/test/CodeGen/arm-target-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-target-features.c?rev=289614&r1=289613&r2=289614&view=diff
==
--- cfe/trunk/test/CodeGen/arm-target-features.c (original)
+++ cfe/trunk/test/CodeGen/arm-target-features.c Tue Dec 13 17:31:57 2016
@@ -30,6 +30,7 @@
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a73 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m1 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m2 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m3 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // CHECK-BASIC-V8: 
"target-features"="+crc,+crypto,+dsp,+fp-armv8,+hwdiv,+hwdiv-arm,+neon"
 
 

Modified: cfe/trunk/test/Driver/aarch64-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=289614&r1=289613&r2=289614&view=diff
==
--- cfe/trunk/test/Driver/aarch64-cpus.c (original)
+++ cfe/trunk/test/Driver/aarch64-cpus.c Tue Dec 13 17:31:57 2016
@@ -104,6 +104,14 @@
 // RUN: %clang -target aarch64_be -mlittle-endian -mtune=exynos-m2 -### -c %s 
2>&1 | FileCheck -check-prefix=M2 %s
 // M2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "exynos-m2"
 
+// RUN: %clang -target aarch64_be -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck 
-check-prefix=M3 %s
+// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 | 
FileCheck -check-prefix=M3 %s
+// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 
| FileCheck -check-prefix=M3 %s
+// RUN: %clang -target aarch64_be -mtune=exynos-m3 -### -c %s 2>&1 | FileCheck 
-check-prefix=M3 %s
+// RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m3 -### -c %s 2>&1 | 
FileCheck -check-prefix=M3 %s
+// RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m3 -### -c %s 
2>&1 | FileCheck -check-prefix=M3 %s
+// M3: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m3"
+
 // RUN: %clang -target arm64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M1 %s
@@ -116,6 +124,12 @@
 // RUN: %clang -target arm64 -mlittle-endian -mtune=exynos-m2 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-M2 %s
 // ARM64-M2: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m2"
 
+// RUN: %clang -target arm64 -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M3 %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m3 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M3 %s
+// RUN: %clang -target arm64 -mtune=exynos-m3 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M3 %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=exynos-m3 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-M3 %s
+// ARM64-M3: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m3"
+
 // RUN: %clang -target aarch64 -mcpu=falkor -### -c %s 2>&1 | FileCheck 
-check-prefix=FALKOR %s
 // RUN: %clang -target aarch64 -mlittle-endian -mcpu=falkor -### -c %s 2>&1 | 
FileCheck -check-prefix=FALKOR %s
 // RUN: %clang -target aarch64 -mtune=falkor -### -c %s 2>&1 | FileCheck 
-check-prefix=FALKOR %s
@@ -215,6 +229,14 @@
 // RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m2 -### -c %s 
2>&1 | FileCheck -check-prefix=M2-BE %s
 // M2-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m2"
 
+// RUN: %clang -target aarch64_be -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck 
-check-prefix=M3-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 | 
FileCheck -check-prefix=M3-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 
| FileCheck -check-prefix=M3-BE %s
+// RUN: %clang -target aarch64_be -mtune=exynos-m3 -### -c %s 2>&1 | FileCheck 
-check-prefix=M3-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m3 -### -c %s 2>&1 | 
FileCheck -check-prefix=M3-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m3 -### -c %s 
2>&1 | FileCheck -check-prefix=M3-B

r277365 - [AArch64] Add support for Samsung Exynos M2 (NFC).

2016-08-01 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Mon Aug  1 13:39:55 2016
New Revision: 277365

URL: http://llvm.org/viewvc/llvm-project?rev=277365&view=rev
Log:
[AArch64] Add support for Samsung Exynos M2 (NFC).

Modified:
cfe/trunk/test/CodeGen/arm-target-features.c
cfe/trunk/test/Driver/aarch64-cpus.c
cfe/trunk/test/Driver/arm-cortex-cpus.c
cfe/trunk/test/Preprocessor/aarch64-target-features.c

Modified: cfe/trunk/test/CodeGen/arm-target-features.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-target-features.c?rev=277365&r1=277364&r2=277365&view=diff
==
--- cfe/trunk/test/CodeGen/arm-target-features.c (original)
+++ cfe/trunk/test/CodeGen/arm-target-features.c Mon Aug  1 13:39:55 2016
@@ -29,6 +29,7 @@
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a72 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a73 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m1 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu exynos-m2 
-emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-BASIC-V8
 // CHECK-BASIC-V8: 
"target-features"="+crc,+crypto,+dsp,+fp-armv8,+hwdiv,+hwdiv-arm,+neon"
 
 

Modified: cfe/trunk/test/Driver/aarch64-cpus.c
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-cpus.c?rev=277365&r1=277364&r2=277365&view=diff
==
--- cfe/trunk/test/Driver/aarch64-cpus.c (original)
+++ cfe/trunk/test/Driver/aarch64-cpus.c Mon Aug  1 13:39:55 2016
@@ -96,12 +96,26 @@
 // RUN: %clang -target aarch64_be -mlittle-endian -mtune=exynos-m1 -### -c %s 
2>&1 | FileCheck -check-prefix=M1 %s
 // M1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "exynos-m1"
 
+// RUN: %clang -target aarch64 -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck 
-check-prefix=M2 %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=exynos-m2 -### -c %s 2>&1 
| FileCheck -check-prefix=M2 %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=exynos-m2 -### -c %s 
2>&1 | FileCheck -check-prefix=M2 %s
+// RUN: %clang -target aarch64 -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck 
-check-prefix=M2 %s
+// RUN: %clang -target aarch64 -mlittle-endian -mtune=exynos-m2 -### -c %s 
2>&1 | FileCheck -check-prefix=M2 %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mtune=exynos-m2 -### -c %s 
2>&1 | FileCheck -check-prefix=M2 %s
+// M2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "exynos-m2"
+
 // RUN: %clang -target arm64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m1 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mtune=exynos-m1 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M1 %s
 // RUN: %clang -target arm64 -mlittle-endian -mtune=exynos-m1 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-M1 %s
 // ARM64-M1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m1"
 
+// RUN: %clang -target arm64 -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M2 %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=exynos-m2 -### -c %s 2>&1 | 
FileCheck -check-prefix=ARM64-M2 %s
+// RUN: %clang -target arm64 -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck 
-check-prefix=ARM64-M2 %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=exynos-m2 -### -c %s 2>&1 
| FileCheck -check-prefix=ARM64-M2 %s
+// ARM64-M2: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "exynos-m2"
+
 // RUN: %clang -target aarch64 -mcpu=kryo -### -c %s 2>&1 | FileCheck 
-check-prefix=KRYO %s
 // RUN: %clang -target aarch64 -mlittle-endian -mcpu=kryo -### -c %s 2>&1 | 
FileCheck -check-prefix=KRYO %s
 // RUN: %clang -target aarch64 -mtune=kryo -### -c %s 2>&1 | FileCheck 
-check-prefix=KRYO %s
@@ -181,6 +195,14 @@
 // RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m1 -### -c %s 
2>&1 | FileCheck -check-prefix=M1-BE %s
 // M1-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "exynos-m1"
 
+// RUN: %clang -target aarch64_be -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck 
-check-prefix=M2-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m2 -### -c %s 2>&1 | 
FileCheck -check-prefix=M2-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m2 -### -c %s 2>&1 
| FileCheck -check-prefix=M2-BE %s
+// RUN: %clang -target aarch64_be -mtune=exynos-m2 -### -c %s 2>&1 | FileCheck 
-check-prefix=M2-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -mtune=exynos-m2 -### -c %s 2>&1 | 
FileCheck -check-prefix=M2-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mtune=exynos-m2 -### -c %s 
2>&1 | FileCheck -check-prefix=M2-BE %s
+// M2-BE: "-c

[libcxx] r272401 - [streambuf] Added call to traits_type::copy to common case in xsgetn()

2016-06-10 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Fri Jun 10 11:00:29 2016
New Revision: 272401

URL: http://llvm.org/viewvc/llvm-project?rev=272401&view=rev
Log:
[streambuf] Added call to traits_type::copy to common case in xsgetn()

Patch by Laman Sole , Sebastian Pop
, Aditya Kumar 

Differential Revision: http://reviews.llvm.org/D21103

Modified:
libcxx/trunk/include/streambuf

Modified: libcxx/trunk/include/streambuf
URL: 
http://llvm.org/viewvc/llvm-project/libcxx/trunk/include/streambuf?rev=272401&r1=272400&r2=272401&view=diff
==
--- libcxx/trunk/include/streambuf (original)
+++ libcxx/trunk/include/streambuf Fri Jun 10 11:00:29 2016
@@ -495,12 +495,22 @@ basic_streambuf<_CharT, _Traits>::xsgetn
 const int_type __eof = traits_type::eof();
 int_type __c;
 streamsize __i = 0;
-for (;__i < __n; ++__i, ++__s)
+while(__i < __n)
 {
 if (__ninp_ < __einp_)
-*__s = *__ninp_++;
+{
+const streamsize __len = _VSTD::min(__einp_ - __ninp_, __n - __i);
+traits_type::copy(__s, __ninp_, __len);
+__s +=  __len;
+__i +=  __len;
+this->gbump(__len);
+}
 else if ((__c = uflow()) != __eof)
+{
 *__s = traits_type::to_char_type(__c);
+++__s;
+++__i;
+}
 else
 break;
 }


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r273280 - [AArch64] Change the preferred alignment for char and short to word alignment

2016-06-21 Thread Evandro Menezes via cfe-commits 
Author: evandro
Date: Tue Jun 21 10:55:29 2016
New Revision: 273280

URL: http://llvm.org/viewvc/llvm-project?rev=273280&view=rev
Log:
[AArch64] Change the preferred alignment for char and short to word alignment

Differential Revision: http://reviews.llvm.org/D21414

Modified:
cfe/trunk/lib/Basic/Targets.cpp

Modified: cfe/trunk/lib/Basic/Targets.cpp
URL: 
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets.cpp?rev=273280&r1=273279&r2=273280&view=diff
==
--- cfe/trunk/lib/Basic/Targets.cpp (original)
+++ cfe/trunk/lib/Basic/Targets.cpp Tue Jun 21 10:55:29 2016
@@ -5994,7 +5994,7 @@ class AArch64leTargetInfo : public AArch
 if (getTriple().isOSBinFormatMachO())
   resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128");
 else
-  resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128");
+  resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
   }
 
 public:
@@ -6012,7 +6012,7 @@ public:
 class AArch64beTargetInfo : public AArch64TargetInfo {
   void setDataLayout() override {
 assert(!getTriple().isOSBinFormatMachO());
-resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128");
+resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128");
   }
 
 public:


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