Author: Evandro Menezes Date: 2020-09-25T18:36:53-05:00 New Revision: a000580a89718a1ff27a3129e34367b9a3fa1730
URL: https://github.com/llvm/llvm-project/commit/a000580a89718a1ff27a3129e34367b9a3fa1730 DIFF: https://github.com/llvm/llvm-project/commit/a000580a89718a1ff27a3129e34367b9a3fa1730.diff LOG: [RISCV] Update driver tests Add the RISC-V Bullet core to the driver tests. Added: Modified: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note.c Removed: ################################################################################ diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index c6281a0b6433..c22f6cce2cf6 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -1,11 +1,18 @@ // Check target CPUs are correctly passed. -// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=MCPU-ROCKETCHIP32 %s -// MCPU-ROCKETCHIP32: "-nostdsysteminc" "-target-cpu" "rocket-rv32" +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rocket-rv32 | FileCheck -check-prefix=MCPU-ROCKET32 %s +// MCPU-ROCKET32: "-nostdsysteminc" "-target-cpu" "rocket-rv32" -// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck -check-prefix=MCPU-ROCKETCHIP64 %s -// MCPU-ROCKETCHIP64: "-nostdsysteminc" "-target-cpu" "rocket-rv64" -// MCPU-ROCKETCHIP64: "-target-feature" "+64bit" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=rocket-rv64 | FileCheck -check-prefix=MCPU-ROCKET64 %s +// MCPU-ROCKET64: "-nostdsysteminc" "-target-cpu" "rocket-rv64" +// MCPU-ROCKET64: "-target-feature" "+64bit" + +// RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=bullet-rv32 | FileCheck -check-prefix=MCPU-BULLET32 %s +// MCPU-BULLET32: "-nostdsysteminc" "-target-cpu" "bullet-rv32" + +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=bullet-rv64 | FileCheck -check-prefix=MCPU-BULLET64 %s +// MCPU-BULLET64: "-nostdsysteminc" "-target-cpu" "bullet-rv64" +// MCPU-BULLET64: "-target-feature" "+64bit" // mcpu with default march // RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-u54 | FileCheck -check-prefix=MCPU-SIFIVE-U54 %s diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 546ab6341f97..efcecbbc4726 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -191,8 +191,8 @@ // RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32 // RISCV32: error: unknown target CPU 'not-a-cpu' -// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e31 +// RISCV32: note: valid target CPU values are: generic-rv32, rocket-rv32, bullet-rv32, sifive-e31 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64 // RISCV64: error: unknown target CPU 'not-a-cpu' -// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-u54 +// RISCV64: note: valid target CPU values are: generic-rv64, rocket-rv64, bullet-rv64, sifive-u54 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
