r341475 - Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89
Author: dnsampaio Date: Wed Sep 5 07:56:21 2018 New Revision: 341475 URL: http://llvm.org/viewvc/llvm-project?rev=341475&view=rev Log: Fix arm_neon.h and arm_fp16.h generation for compiling with std=c89 Summary: The inline attribute is not valid for C standard 89. Replace the argument in the generation of header files with __inline, as well adding tests for both header files. Reviewers: pbarrio, SjoerdMeijer, javed.absar, t.p.northover Subscribers: t.p.northover, kristof.beyls, chrib, cfe-commits Differential Revision: https://reviews.llvm.org/D51683 test/Headers/arm-fp16-header.c test/Headers/arm-neon-header.c utils/TableGen/NeonEmitter.cpp Added: cfe/trunk/test/Headers/arm-fp16-header.c Modified: cfe/trunk/test/Headers/arm-neon-header.c cfe/trunk/utils/TableGen/NeonEmitter.cpp Added: cfe/trunk/test/Headers/arm-fp16-header.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Headers/arm-fp16-header.c?rev=341475&view=auto == --- cfe/trunk/test/Headers/arm-fp16-header.c (added) +++ cfe/trunk/test/Headers/arm-fp16-header.c Wed Sep 5 07:56:21 2018 @@ -0,0 +1,19 @@ +// RUN: %clang -fsyntax-only -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c89 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c99 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c11 -xc %s + +// RUN: %clang -fsyntax-only -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c89 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c99 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c11 -xc %s + +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++98 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++11 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++14 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++17 -xc++ %s + +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c++98 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c++11 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c++14 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c++17 -xc++ %s + +#include Modified: cfe/trunk/test/Headers/arm-neon-header.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Headers/arm-neon-header.c?rev=341475&r1=341474&r2=341475&view=diff == --- cfe/trunk/test/Headers/arm-neon-header.c (original) +++ cfe/trunk/test/Headers/arm-neon-header.c Wed Sep 5 07:56:21 2018 @@ -2,4 +2,23 @@ // RUN: %clang_cc1 -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -fno-lax-vector-conversions -ffreestanding %s // RUN: %clang_cc1 -x c++ -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -Wvector-conversions -ffreestanding %s +// RUN: %clang -fsyntax-only -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c89 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c99 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c11 -xc %s + +// RUN: %clang -fsyntax-only -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c89 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c99 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c11 -xc %s + +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++98 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++11 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++14 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++17 -xc++ %s + +// RUN: %cl
r341548 - Fix march triple used test from rL341475
Author: dnsampaio Date: Thu Sep 6 07:13:10 2018 New Revision: 341548 URL: http://llvm.org/viewvc/llvm-project?rev=341548&view=rev Log: Fix march triple used test from rL341475 Change the march triple of test files, possible fixing test failures due rL341475 Modified: cfe/trunk/test/Headers/arm-fp16-header.c cfe/trunk/test/Headers/arm-neon-header.c Modified: cfe/trunk/test/Headers/arm-fp16-header.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Headers/arm-fp16-header.c?rev=341548&r1=341547&r2=341548&view=diff == --- cfe/trunk/test/Headers/arm-fp16-header.c (original) +++ cfe/trunk/test/Headers/arm-fp16-header.c Thu Sep 6 07:13:10 2018 @@ -1,19 +1,19 @@ -// RUN: %clang -fsyntax-only -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c89 -xc %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c99 -xc %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c11 -xc %s +// RUN: %clang -fsyntax-only -ffreestanding --target=aarch64-none-eabi -march=armv8.2-a+fp16 -std=c89 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-none-eabi -march=armv8.2-a+fp16 -std=c99 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-none-eabi -march=armv8.2-a+fp16 -std=c11 -xc %s -// RUN: %clang -fsyntax-only -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c89 -xc %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c99 -xc %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c11 -xc %s +// RUN: %clang -fsyntax-only -ffreestanding --target=aarch64_be-none-eabi -march=armv8.2-a+fp16 -std=c89 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64_be-none-eabi -march=armv8.2-a+fp16 -std=c99 -xc %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64_be-none-eabi -march=armv8.2-a+fp16 -std=c11 -xc %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++98 -xc++ %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++11 -xc++ %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++14 -xc++ %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-arm-none-eabi -march=armv8.2-a+fp16 -std=c++17 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-none-eabi -march=armv8.2-a+fp16 -std=c++98 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-none-eabi -march=armv8.2-a+fp16 -std=c++11 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-none-eabi -march=armv8.2-a+fp16 -std=c++14 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-none-eabi -march=armv8.2-a+fp16 -std=c++17 -xc++ %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c++98 -xc++ %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c++11 -xc++ %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c++14 -xc++ %s -// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64-armeb-none-eabi -march=armv8.2-a+fp16 -std=c++17 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64_be-none-eabi -march=armv8.2-a+fp16 -std=c++98 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64_be-none-eabi -march=armv8.2-a+fp16 -std=c++11 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64_be-none-eabi -march=armv8.2-a+fp16 -std=c++14 -xc++ %s +// RUN: %clang -fsyntax-only -Wall -Werror -ffreestanding --target=aarch64_be-none-eabi -march=armv8.2-a+fp16 -std=c++17 -xc++ %s #include Modified: cfe/trunk/test/Headers/arm-neon-header.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Headers/arm-neon-header.c?rev=341548&r1=341547&r2=341548&view=diff == --- cfe/trunk/test/Headers/arm-neon-header.c (original) +++ cfe/trunk/test/Headers/arm-neon-header.c Thu Sep 6 07:13:10 2018 @@ -2,23 +2,22 @@ // RUN: %clang_cc1 -triple thumbv7-apple-darwin10 -target-cpu cortex-a8 -fsyntax-only -fno-lax-vector-conversions -ffreestanding %s // RUN: %clang_cc1 -x c++ -triple thumbv7-apple-darwin10
r341644 - Replaces __inline by __inline__ / C89 compatible
Author: dnsampaio
Date: Fri Sep 7 02:37:27 2018
New Revision: 341644
URL: http://llvm.org/viewvc/llvm-project?rev=341644&view=rev
Log:
Replaces __inline by __inline__ / C89 compatible
Modified:
cfe/trunk/utils/TableGen/NeonEmitter.cpp
Modified: cfe/trunk/utils/TableGen/NeonEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/utils/TableGen/NeonEmitter.cpp?rev=341644&r1=341643&r2=341644&view=diff
==
--- cfe/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ cfe/trunk/utils/TableGen/NeonEmitter.cpp Fri Sep 7 02:37:27 2018
@@ -2409,7 +2409,7 @@ void NeonEmitter::run(raw_ostream &OS) {
OS << "#endif\n";
OS << "\n";
- OS << "#define __ai static __inline __attribute__((__always_inline__, "
+ OS << "#define __ai static __inline__ __attribute__((__always_inline__, "
"__nodebug__))\n\n";
SmallVector Defs;
@@ -2518,7 +2518,7 @@ void NeonEmitter::runFP16(raw_ostream &O
OS << "typedef __fp16 float16_t;\n";
- OS << "#define __ai static __inline __attribute__((__always_inline__, "
+ OS << "#define __ai static __inline__ __attribute__((__always_inline__, "
"__nodebug__))\n\n";
SmallVector Defs;
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r352203 - [NFC][Clang] Add driver tests for sb and predres
Author: dnsampaio Date: Fri Jan 25 06:57:22 2019 New Revision: 352203 URL: http://llvm.org/viewvc/llvm-project?rev=352203&view=rev Log: [NFC][Clang] Add driver tests for sb and predres Add tests that arguments for enabling/disabling sb and predres are correctly being or not passed by the driver. Differential Revision: https://reviews.llvm.org/D57060 Added: cfe/trunk/test/Driver/aarch64-predres.c cfe/trunk/test/Driver/arm-sb.c Added: cfe/trunk/test/Driver/aarch64-predres.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-predres.c?rev=352203&view=auto == --- cfe/trunk/test/Driver/aarch64-predres.c (added) +++ cfe/trunk/test/Driver/aarch64-predres.c Fri Jan 25 06:57:22 2019 @@ -0,0 +1,11 @@ +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+predres %s 2>&1 | FileCheck %s +// CHECK: "-target-feature" "+predres" +// CHECK-NOT: "-target-feature" "-predres" + +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+nopredres %s 2>&1 | FileCheck %s --check-prefix=NOPR +// NOPR: "-target-feature" "-predres" +// NOPR-NOT: "-target-feature" "+predres" + +// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENT +// ABSENT-NOT: "-target-feature" "+predres" +// ABSENT-NOT: "-target-feature" "-predres" Added: cfe/trunk/test/Driver/arm-sb.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-sb.c?rev=352203&view=auto == --- cfe/trunk/test/Driver/arm-sb.c (added) +++ cfe/trunk/test/Driver/arm-sb.c Fri Jan 25 06:57:22 2019 @@ -0,0 +1,14 @@ +// RUN: %clang -### -target arm-none-none-eabi -march=armv8a+sb %s 2>&1 | FileCheck %s +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8a+sb %s 2>&1 | FileCheck %s +// CHECK: "-target-feature" "+sb" +// CHECK-NOT: "-target-feature" "-sb" + +// RUN: %clang -### -target arm-none-none-eabi -march=armv8.5a+nosb %s 2>&1 | FileCheck %s --check-prefix=NOSB +// RUN: %clang -### -target aarch64-none-none-eabi -march=armv8.5a+nosb %s 2>&1 | FileCheck %s --check-prefix=NOSB +// NOSB: "-target-feature" "-sb" +// NOSB-NOT: "-target-feature" "+sb" + +// RUN: %clang -### -target arm-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENT +// RUN: %clang -### -target aarch64-none-none-eabi %s 2>&1 | FileCheck %s --check-prefix=ABSENT +// ABSENT-NOT: "-target-feature" "+sb" +// ABSENT-NOT: "-target-feature" "-sb" ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r346303 - [NFC][Clang][Aarch64] Add missing test file
Author: dnsampaio
Date: Wed Nov 7 03:42:02 2018
New Revision: 346303
URL: http://llvm.org/viewvc/llvm-project?rev=346303&view=rev
Log:
[NFC][Clang][Aarch64] Add missing test file
The commit rL345273 by @LukeCheeseman has a missing test file,
see https://reviews.llvm.org/D51429
This patch adds the missing test file.
Patch by Luke Cheeseman
Differential revision: https://reviews.llvm.org/D54148
Added:
cfe/trunk/test/Driver/aarch64-security-options.c
Added: cfe/trunk/test/Driver/aarch64-security-options.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/aarch64-security-options.c?rev=346303&view=auto
==
--- cfe/trunk/test/Driver/aarch64-security-options.c (added)
+++ cfe/trunk/test/Driver/aarch64-security-options.c Wed Nov 7 03:42:02 2018
@@ -0,0 +1,54 @@
+// Check the -msign-return-address= option, which has a required argument to
+// select scope.
+// RUN: %clang -target aarch64--none-eabi -c %s -###
-msign-return-address=none 2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-OFF --check-prefix=KEY-A
--check-prefix=BTE-OFF
+
+// RUN: %clang -target aarch64--none-eabi -c %s -###
-msign-return-address=non-leaf 2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-NON-LEAF --check-prefix=KEY-A
--check-prefix=BTE-OFF
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=all
2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-ALL --check-prefix=KEY-A
--check-prefix=BTE-OFF
+
+// Check that the -msign-return-address= option can also accept the signing key
+// to use.
+
+// RUN: %clang -target aarch64--none-eabi -c %s -###
-msign-return-address=non-leaf 2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-NON-LEAF --check-prefix=KEY-B
--check-prefix=BTE-OFF
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=all
2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-ALL --check-prefix=KEY-B
--check-prefix=BTE-OFF
+
+// -mbranch-protection with standard
+// RUN: %clang -target aarch64--none-eabi -c %s -###
-mbranch-protection=standard2>&1 | \
+// RUN: FileCheck %s --check-prefix=RA-NON-LEAF --check-prefix=KEY-A
--check-prefix=BTE-ON
+
+// If the -msign-return-address and -mbranch-protection are both used, the
+// right-most one controls return address signing.
+// RUN: %clang -target aarch64--none-eabi -c %s -###
-msign-return-address=non-leaf -mbranch-protection=none 2>&1 | \
+// RUN: FileCheck %s --check-prefix=CONFLICT
+
+// RUN: %clang -target aarch64--none-eabi -c %s -###
-mbranch-protection=pac-ret -msign-return-address=none 2>&1 | \
+// RUN: FileCheck %s --check-prefix=CONFLICT
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -msign-return-address=foo
2>&1 | \
+// RUN: FileCheck %s --check-prefix=BAD-RA-PROTECTION
+
+// RUN: %clang -target aarch64--none-eabi -c %s -### -mbranch-protection=bar
2>&1 | \
+// RUN: FileCheck %s --check-prefix=BAD-BP-PROTECTION
+
+// RA-OFF: "-msign-return-address=none"
+// RA-NON-LEAF: "-msign-return-address=non-leaf"
+// RA-ALL: "-msign-return-address=all"
+
+// KEY-A: "-msign-return-address-key=a_key"
+
+// BTE-OFF-NOT: "-mbranch-target-enforce"
+// BTE-ON: "-mbranch-target-enforce"
+
+// CONFLICT: "-msign-return-address=none"
+
+// BAD-RA-PROTECTION: invalid branch protection option 'foo' in
'-msign-return-address={{.*}}'
+// BAD-BP-PROTECTION: invalid branch protection option 'bar' in
'-mbranch-protection={{.*}}'
+
+// BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in
'-mbranch-protection={{.*}}'
+// BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in
'-mbranch-protection={{.*}}'
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r358276 - [Aarch64] Add v8.2-a half precision element extract intrinsics
Author: dnsampaio
Date: Fri Apr 12 03:43:48 2019
New Revision: 358276
URL: http://llvm.org/viewvc/llvm-project?rev=358276&view=rev
Log:
[Aarch64] Add v8.2-a half precision element extract intrinsics
Summary:
Implements the intrinsics define on the ACLE to extract half precision fp
scalar elements from float16x4_t and float16x8_t vector types.
a.k.a:
vduph_lane_f16
vduph_laneq_f16
Reviewers: pablooliveira, olista01, LukeGeeson, DavidSpickett
Reviewed By: DavidSpickett
Subscribers: DavidSpickett, javed.absar, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D60272
Modified:
cfe/trunk/lib/CodeGen/CGBuiltin.cpp
cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
Modified: cfe/trunk/lib/CodeGen/CGBuiltin.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGBuiltin.cpp?rev=358276&r1=358275&r2=358276&view=diff
==
--- cfe/trunk/lib/CodeGen/CGBuiltin.cpp (original)
+++ cfe/trunk/lib/CodeGen/CGBuiltin.cpp Fri Apr 12 03:43:48 2019
@@ -7847,6 +7847,14 @@ Value *CodeGenFunction::EmitAArch64Built
: Intrinsic::aarch64_neon_sqsub;
return EmitNeonCall(CGM.getIntrinsic(AccInt, Int64Ty), Ops, "vqdmlXl");
}
+ case NEON::BI__builtin_neon_vduph_lane_f16: {
+return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)),
+"vget_lane");
+ }
+ case NEON::BI__builtin_neon_vduph_laneq_f16: {
+return Builder.CreateExtractElement(Ops[0], EmitScalarExpr(E->getArg(1)),
+"vgetq_lane");
+ }
}
llvm::VectorType *VTy = GetNeonType(this, Type);
Modified: cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c?rev=358276&r1=358275&r2=358276&view=diff
==
--- cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c (original)
+++ cfe/trunk/test/CodeGen/aarch64-v8.2a-neon-intrinsics.c Fri Apr 12 03:43:48
2019
@@ -1618,3 +1618,16 @@ float16x8_t test_vtrn2q_f16(float16x8_t
return vtrn2q_f16(a, b);
}
+// CHECK-LABEL: @test_vduph_laneq_f16(
+// CHECK:[[V:%.*]] = extractelement <8 x half> [[V2:%.*]], i32 7
+// CHECK-NEXT: ret half [[V]]
+float16_t test_vduph_laneq_f16(float16x8_t vec) {
+ return vduph_laneq_f16(vec, 7);
+}
+
+// CHECK-LABEL: @test_vduph_lane_f16(
+// CHECK:[[V:%.*]] = extractelement <4 x half> [[V2:%.*]], i32 3
+// CHECK-NEXT: ret half [[V]]
+float16_t test_vduph_lane_f16(float16x4_t vec) {
+ return vduph_lane_f16(vec, 3);
+}
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r360324 - [ARM] Fix the extensions implied by a cpu name
Author: dnsampaio
Date: Thu May 9 03:24:36 2019
New Revision: 360324
URL: http://llvm.org/viewvc/llvm-project?rev=360324&view=rev
Log:
[ARM] Fix the extensions implied by a cpu name
Summary:
When using `clang -mcpu=CPUNAME+FEATURELIST`,
the implied features defined by CPUNAME are
not obtained, as the entire string is passed.
This fixes that by spiting the cpuname
string in the first `+`, if any.
For example, when using
```clang -### --target=arm-arm-none-eabi -march=armv7-a -mcpu=cortex-a8+nocrc```
the intrinsic
```"target-feature" "+dsp"```
implied by `cortex-a8` is missing.
Reviewers: keith.walker.arm, DavidSpickett, carwil
Reviewed By: DavidSpickett
Subscribers: javed.absar, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D61668
Modified:
cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
cfe/trunk/test/Driver/arm-cortex-cpus.c
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp?rev=360324&r1=360323&r2=360324&view=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp Thu May 9 03:24:36 2019
@@ -88,6 +88,7 @@ static bool DecodeARMFeatures(const Driv
static void DecodeARMFeaturesFromCPU(const Driver &D, StringRef CPU,
std::vector &Features) {
+ CPU = CPU.split("+").first;
if (CPU != "generic") {
llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(CPU);
unsigned Extension = llvm::ARM::getDefaultExtensions(CPU, ArchKind);
@@ -350,11 +351,9 @@ void arm::getARMTargetFeatures(const Too
D.Diag(clang::diag::warn_drv_unused_argument)
<< CPUArg->getAsString(Args);
CPUName = StringRef(WaCPU->getValue()).substr(6);
-checkARMCPUName(D, WaCPU, Args, CPUName, ArchName, Features, Triple);
- } else if (CPUArg) {
+CPUArg = WaCPU;
+ } else if (CPUArg)
CPUName = CPUArg->getValue();
-checkARMCPUName(D, CPUArg, Args, CPUName, ArchName, Features, Triple);
- }
// Add CPU features for generic CPUs
if (CPUName == "native") {
@@ -367,6 +366,8 @@ void arm::getARMTargetFeatures(const Too
DecodeARMFeaturesFromCPU(D, CPUName, Features);
}
+ if (CPUArg)
+checkARMCPUName(D, CPUArg, Args, CPUName, ArchName, Features, Triple);
// Honor -mfpu=. ClangAs gives preference to -Wa,-mfpu=.
const Arg *FPUArg = Args.getLastArg(options::OPT_mfpu_EQ);
if (WaFPU) {
Modified: cfe/trunk/test/Driver/arm-cortex-cpus.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-cortex-cpus.c?rev=360324&r1=360323&r2=360324&view=diff
==
--- cfe/trunk/test/Driver/arm-cortex-cpus.c (original)
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c Thu May 9 03:24:36 2019
@@ -340,30 +340,31 @@
// RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+fp16 -### -c %s 2>&1
| FileCheck --check-prefix CHECK-CORTEX-A53-FP16 %s
// RUN: %clang -target armv8a-linux-eabi -mcpu=cortex-a53+nofp16 -### -c %s
2>&1 | FileCheck --check-prefix CHECK-CORTEX-A53-NOFP16 %s
// CHECK-CORTEX-A53-FP16: "-cc1" {{.*}}"-target-cpu" "cortex-a53"
{{.*}}"-target-feature" "+fullfp16"
-// CHECK-CORTEX-A53-FP16-NOT: "-target-feature" "{{[+-]}}fp16fml"
-// CHECK-CORTEX-A53-NOFP16: "-cc1" {{.*}}"-target-cpu" "cortex-a53"
{{.*}}"-target-feature" "-fullfp16" "-target-feature" "-fp16fml"
+// CHECK-CORTEX-A53-FP16-NOT: "-target-feature" "+fp16fml"
+// CHECK-CORTEX-A53-NOFP16-NOT: "+fullfp16"
+// CHECK-CORTEX-A53-NOFP16-NOT: "+fp16fml"
// RUN: %clang -target armv8a-linux-eabi -march=armv8-a -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-NOFP16FML %s
-// CHECK-V8A-NOFP16FML-NOT: "-target-feature" "{{[+-]}}fp16fml"
-// CHECK-V8A-NOFP16FML-NOT: "-target-feature" "{{[+-]}}fullfp16"
+// CHECK-V8A-NOFP16FML-NOT: "-target-feature" "+fp16fml"
+// CHECK-V8A-NOFP16FML-NOT: "-target-feature" "+fullfp16"
// RUN: %clang -target armv8a-linux-eabi -march=armv8-a+fp16 -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V8A-FP16 %s
-// CHECK-V8A-FP16-NOT: "-target-feature" "{{[+-]}}fp16fml"
+// CHECK-V8A-FP16-NOT: "-target-feature" "+fp16fml"
// CHECK-V8A-FP16: "-target-feature" "+fullfp16"
-// CHECK-V8A-FP16-NOT: "-target-feature" "{{[+-]}}fp16fml"
+// CHECK-V8A-FP16-NOT: "-target-feature" "+fp16fml"
// CHECK-V8A-FP16-SAME: {{$}}
// RUN: %clang -target armv8a-linux-eabi -march=armv8-a+fp16fml -### -c %s
2>&1 | FileCheck -check-prefix=CHECK-V8A-FP16FML %s
// CHECK-V8A-FP16FML: "-target-feature" "+fp16fml" "-target-feature"
"+fullfp16"
// RUN: %clang -target armv8a-linux-eabi -march=armv8.2-a -### -c %s 2>&1 |
FileCheck -check-prefix=CHECK-V82A-NOFP16FML %s
-// CHECK-V82A-NOFP16FML-NOT: "-target-feature" "{{[+-]}}fp16fml"
-// CHECK-V82A-NOFP16FML-NOT: "-target-feature" "{{[+-]}}fullfp16"
+// CHECK-V82A-NOFP1
r360329 - [FIX] Change test to read file instead
Author: dnsampaio
Date: Thu May 9 04:23:00 2019
New Revision: 360329
URL: http://llvm.org/viewvc/llvm-project?rev=360329&view=rev
Log:
[FIX] Change test to read file instead
This should fix the test file failing in
windows by reading the file it self instead
of stdin, from 543913c3b41f
Modified:
cfe/trunk/test/Driver/arm-cortex-cpus.c
Modified: cfe/trunk/test/Driver/arm-cortex-cpus.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-cortex-cpus.c?rev=360329&r1=360328&r2=360329&view=diff
==
--- cfe/trunk/test/Driver/arm-cortex-cpus.c (original)
+++ cfe/trunk/test/Driver/arm-cortex-cpus.c Thu May 9 04:23:00 2019
@@ -856,5 +856,5 @@
// CHECK-CASE-INSENSITIVE-V6T2-THUMB: "-cc1"{{.*}} "-triple" "thumbv6t2-{{.*}}
"-target-cpu" "arm1156t2-s"
// == Check that the correct PROCESSOR features are added when
used -mcpu=PROCESSOR+FEATURESLIST
-// RUN: %clang -### --target=arm-arm-none-eabi -march=armv7-a
-mcpu=cortex-a8+nocrc -x c -S -o - - <<< "" 2>&1 | FileCheck
-check-prefix=A8FEATURES %s
+// RUN: %clang -### --target=arm-arm-none-eabi -march=armv7-a
-mcpu=cortex-a8+nocrc -c %s 2>&1 | FileCheck -check-prefix=A8FEATURES %s
// A8FEATURES: "-target-feature" "+dsp"
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r368288 - [ARM] Set default alignment to 64bits
Author: dnsampaio
Date: Thu Aug 8 05:50:36 2019
New Revision: 368288
URL: http://llvm.org/viewvc/llvm-project?rev=368288&view=rev
Log:
[ARM] Set default alignment to 64bits
Summary:
The maximum alignment used by ARM arch
is 64bits, not 128.
This could cause overaligned memory
access for 128 bit neon vector that
have unpredictable behaviour.
This fixes: https://bugs.llvm.org/show_bug.cgi?id=42668
Reviewers: ostannard, dmgreen, srhines, danalbert, pirama, peter.smith
Reviewed By: pirama, peter.smith
Subscribers: phosek, thegameg, thakis, llvm-commits, carwil, peter.smith,
javed.absar, kristof.beyls, cfe-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D65000
Added:
cfe/trunk/test/CodeGenCXX/ARM/
cfe/trunk/test/CodeGenCXX/ARM/exception-alignment.cpp
Modified:
cfe/trunk/lib/Basic/Targets/ARM.cpp
cfe/trunk/test/SemaCXX/warn-overaligned-type-thrown.cpp
Modified: cfe/trunk/lib/Basic/Targets/ARM.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Basic/Targets/ARM.cpp?rev=368288&r1=368287&r2=368288&view=diff
==
--- cfe/trunk/lib/Basic/Targets/ARM.cpp (original)
+++ cfe/trunk/lib/Basic/Targets/ARM.cpp Thu Aug 8 05:50:36 2019
@@ -309,8 +309,9 @@ ARMTargetInfo::ARMTargetInfo(const llvm:
setAtomic();
// Maximum alignment for ARM NEON data types should be 64-bits (AAPCS)
+ // as well the default alignment
if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android))
-MaxVectorAlign = 64;
+DefaultAlignForAttributeAligned = MaxVectorAlign = 64;
// Do force alignment of members that follow zero length bitfields. If
// the alignment of the zero-length bitfield is greater than the member
Added: cfe/trunk/test/CodeGenCXX/ARM/exception-alignment.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGenCXX/ARM/exception-alignment.cpp?rev=368288&view=auto
==
--- cfe/trunk/test/CodeGenCXX/ARM/exception-alignment.cpp (added)
+++ cfe/trunk/test/CodeGenCXX/ARM/exception-alignment.cpp Thu Aug 8 05:50:36
2019
@@ -0,0 +1,21 @@
+// Bug: https://bugs.llvm.org/show_bug.cgi?id=42668
+// REQUIRES: arm-registered-target
+
+// RUN: %clang_cc1 -triple armv8-arm-none-eabi -emit-llvm -target-cpu generic
-Os -fcxx-exceptions -o - -x c++ %s | FileCheck --check-prefixes=CHECK,A8 %s
+// RUN: %clang_cc1 -triple armv8-unknown-linux-android -emit-llvm -target-cpu
generic -Os -fcxx-exceptions -o - -x c++ %s | FileCheck
--check-prefixes=CHECK,A16 %s
+
+// CHECK: [[E:%[A-z0-9]+]] = tail call i8* @__cxa_allocate_exception
+// CHECK-NEXT: [[BC:%[A-z0-9]+]] = bitcast i8* [[E]] to <2 x i64>*
+// A8-NEXT: store <2 x i64> , <2 x i64>* [[BC]], align 8
+// A16-NEXT: store <2 x i64> , <2 x i64>* [[BC]], align 16
+#include
+
+int main(void) {
+ try {
+throw vld1q_u64(((const uint64_t[2]){1, 2}));
+ } catch (uint64x2_t exc) {
+return 0;
+ }
+ return 1;
+}
+
Modified: cfe/trunk/test/SemaCXX/warn-overaligned-type-thrown.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/SemaCXX/warn-overaligned-type-thrown.cpp?rev=368288&r1=368287&r2=368288&view=diff
==
--- cfe/trunk/test/SemaCXX/warn-overaligned-type-thrown.cpp (original)
+++ cfe/trunk/test/SemaCXX/warn-overaligned-type-thrown.cpp Thu Aug 8 05:50:36
2019
@@ -2,11 +2,12 @@
// RUN: %clang_cc1 -triple arm64-apple-ios10 -verify -fsyntax-only -std=c++11
-fcxx-exceptions -fexceptions -DUNDERALIGNED %s
// RUN: %clang_cc1 -triple arm64-apple-tvos10 -verify -fsyntax-only -std=c++11
-fcxx-exceptions -fexceptions -DUNDERALIGNED %s
// RUN: %clang_cc1 -triple arm64-apple-watchos4 -verify -fsyntax-only
-std=c++11 -fcxx-exceptions -fexceptions -DUNDERALIGNED %s
+// RUN: %clang_cc1 -triple arm-linux-gnueabi -verify -fsyntax-only -std=c++11
-fcxx-exceptions -fexceptions -DUNDERALIGNED %s
// RUN: %clang_cc1 -triple x86_64-apple-macosx10.14 -verify -fsyntax-only
-std=c++11 -fcxx-exceptions -fexceptions %s
// RUN: %clang_cc1 -triple arm64-apple-ios12 -verify -fsyntax-only -std=c++11
-fcxx-exceptions -fexceptions %s
// RUN: %clang_cc1 -triple arm64-apple-tvos12 -verify -fsyntax-only -std=c++11
-fcxx-exceptions -fexceptions %s
// RUN: %clang_cc1 -triple arm64-apple-watchos5 -verify -fsyntax-only
-std=c++11 -fcxx-exceptions -fexceptions %s
-// RUN: %clang_cc1 -triple arm-linux-gnueabi -verify -fsyntax-only -std=c++11
-fcxx-exceptions -fexceptions %s
+// RUN: %clang_cc1 -triple arm-linux-androideabi -verify -fsyntax-only
-std=c++11 -fcxx-exceptions -fexceptions %s
// RUN: %clang_cc1 -triple aarch64-linux-gnueabi -verify -fsyntax-only
-std=c++11 -fcxx-exceptions -fexceptions %s
// RUN: %clang_cc1 -triple mipsel-linux-gnu -verify -fsyntax-only -std=c++11
-fcxx-exceptions -fexceptions %s
// RUN: %clang_cc1 -triple mips64el-linux-gnu -verify -fsyntax-only -s
r368301 - [FIX][NFC] Update clang sema test
Author: dnsampaio
Date: Thu Aug 8 07:45:42 2019
New Revision: 368301
URL: http://llvm.org/viewvc/llvm-project?rev=368301&view=rev
Log:
[FIX][NFC] Update clang sema test
Try to fix Sema test for default alignment for when
compiling to ARM, but not to android, due
r9427aa2d543b
Modified:
cfe/trunk/test/Sema/struct-packed-align.c
Modified: cfe/trunk/test/Sema/struct-packed-align.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Sema/struct-packed-align.c?rev=368301&r1=368300&r2=368301&view=diff
==
--- cfe/trunk/test/Sema/struct-packed-align.c (original)
+++ cfe/trunk/test/Sema/struct-packed-align.c Thu Aug 8 07:45:42 2019
@@ -59,7 +59,7 @@ extern int e2[__alignof(struct as1) == 8
struct __attribute__((aligned)) as1_2 {
char c;
};
-#ifdef __s390x__
+#if ( defined(__s390x__) || ( defined (__ARM_32BIT_STATE) && !
defined(__ANDROID__) ) )
extern int e1_2[sizeof(struct as1_2) == 8 ? 1 : -1];
extern int e2_2[__alignof(struct as1_2) == 8 ? 1 : -1];
#else
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r365298 - [AArch64] Fix vsqadd scalar intrinsics operands
Author: dnsampaio
Date: Mon Jul 8 01:35:05 2019
New Revision: 365298
URL: http://llvm.org/viewvc/llvm-project?rev=365298&view=rev
Log:
[AArch64] Fix vsqadd scalar intrinsics operands
Summary:
Change the vsqadd scalar instrinsics to have the second argument as signed
values, not unsigned,
accordingly to
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics
The existing unsigned argument can cause faulty code as negative float to
unsigned conversion is
undefined, which llvm/clang optimizes away.
Reviewers: LukeCheeseman, john.brawn
Reviewed By: john.brawn
Subscribers: john.brawn, javed.absar, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D64239
Added:
cfe/trunk/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c
Modified:
cfe/trunk/include/clang/Basic/arm_neon.td
cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
Modified: cfe/trunk/include/clang/Basic/arm_neon.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=365298&r1=365297&r2=365298&view=diff
==
--- cfe/trunk/include/clang/Basic/arm_neon.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon.td Mon Jul 8 01:35:05 2019
@@ -1337,7 +1337,7 @@ def SCALAR_SUQADD : SInst<"vuqadd", "sss
// Scalar Unsigned Saturating Accumulated of Signed Value
-def SCALAR_USQADD : SInst<"vsqadd", "sss", "SUcSUsSUiSUl">;
+def SCALAR_USQADD : SInst<"vsqadd", "ss$", "SUcSUsSUiSUl">;
// Signed Saturating Doubling Multiply-Add Long
Modified: cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=365298&r1=365297&r2=365298&view=diff
==
--- cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c (original)
+++ cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Mon Jul 8 01:35:05 2019
@@ -13913,7 +13913,7 @@ int64_t test_vuqaddd_s64(int64_t a, int6
// CHECK: [[VSQADDB_U8_I:%.*]] = call <8 x i8>
@llvm.aarch64.neon.usqadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
// CHECK: [[TMP2:%.*]] = extractelement <8 x i8> [[VSQADDB_U8_I]], i64 0
// CHECK: ret i8 [[TMP2]]
-uint8_t test_vsqaddb_u8(uint8_t a, uint8_t b) {
+uint8_t test_vsqaddb_u8(uint8_t a, int8_t b) {
return (uint8_t)vsqaddb_u8(a, b);
}
@@ -13923,21 +13923,21 @@ uint8_t test_vsqaddb_u8(uint8_t a, uint8
// CHECK: [[VSQADDH_U16_I:%.*]] = call <4 x i16>
@llvm.aarch64.neon.usqadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
// CHECK: [[TMP2:%.*]] = extractelement <4 x i16> [[VSQADDH_U16_I]], i64 0
// CHECK: ret i16 [[TMP2]]
-uint16_t test_vsqaddh_u16(uint16_t a, uint16_t b) {
+uint16_t test_vsqaddh_u16(uint16_t a, int16_t b) {
return (uint16_t)vsqaddh_u16(a, b);
}
// CHECK-LABEL: @test_vsqadds_u32(
// CHECK: [[VSQADDS_U32_I:%.*]] = call i32 @llvm.aarch64.neon.usqadd.i32(i32
%a, i32 %b)
// CHECK: ret i32 [[VSQADDS_U32_I]]
-uint32_t test_vsqadds_u32(uint32_t a, uint32_t b) {
+uint32_t test_vsqadds_u32(uint32_t a, int32_t b) {
return (uint32_t)vsqadds_u32(a, b);
}
// CHECK-LABEL: @test_vsqaddd_u64(
// CHECK: [[VSQADDD_U64_I:%.*]] = call i64 @llvm.aarch64.neon.usqadd.i64(i64
%a, i64 %b)
// CHECK: ret i64 [[VSQADDD_U64_I]]
-uint64_t test_vsqaddd_u64(uint64_t a, uint64_t b) {
+uint64_t test_vsqaddd_u64(uint64_t a, int64_t b) {
return (uint64_t)vsqaddd_u64(a, b);
}
Added: cfe/trunk/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c?rev=365298&view=auto
==
--- cfe/trunk/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c (added)
+++ cfe/trunk/test/CodeGen/aarch64-neon-vsqadd-float-conversion.c Mon Jul 8
01:35:05 2019
@@ -0,0 +1,49 @@
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
+// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg -dce \
+// RUN: | FileCheck %s
+
+#include
+
+// Check float conversion is accepted for int argument
+uint8_t test_vsqaddb_u8(){
+ return vsqaddb_u8(1, -1.0f);
+}
+
+uint16_t test_vsqaddh_u16() {
+ return vsqaddh_u16(1, -1.0f);
+}
+
+uint32_t test_vsqadds_u32() {
+ return vsqadds_u32(1, -1.0f);
+}
+
+uint64_t test_vsqaddd_u64() {
+ return vsqaddd_u64(1, -1.0f);
+}
+
+// CHECK-LABEL: @test_vsqaddb_u8()
+// CHECK: entry:
+// CHECK-NEXT: [[T0:%.*]] = insertelement <8 x i8> undef, i8 1, i64 0
+// CHECK-NEXT: [[T1:%.*]] = insertelement <8 x i8> undef, i8 -1, i64 0
+// CHECK-NEXT: [[V:%.*]] = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x
i8> [[T0]], <8 x i8> [[T1]])
+// CHECK-NEXT: [[R:%.*]] = ex
r365300 - [AArch64] Fix scalar vuqadd intrinsics operands
Author: dnsampaio
Date: Mon Jul 8 01:47:47 2019
New Revision: 365300
URL: http://llvm.org/viewvc/llvm-project?rev=365300&view=rev
Log:
[AArch64] Fix scalar vuqadd intrinsics operands
Summary:
Change the vuqadd scalar instrinsics to have the second argument as unsigned
values, not signed,
accordingly to
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics
So now the compiler correctly warns that a undefined negative float conversion
is being done.
Reviewers: LukeCheeseman, john.brawn
Reviewed By: john.brawn
Subscribers: john.brawn, javed.absar, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D64242
Added:
cfe/trunk/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c
Modified:
cfe/trunk/include/clang/Basic/arm_neon.td
cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
Modified: cfe/trunk/include/clang/Basic/arm_neon.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=365300&r1=365299&r2=365300&view=diff
==
--- cfe/trunk/include/clang/Basic/arm_neon.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon.td Mon Jul 8 01:47:47 2019
@@ -1333,7 +1333,7 @@ def SCALAR_SQNEG : SInst<"vqneg", "ss",
// Scalar Signed Saturating Accumulated of Unsigned Value
-def SCALAR_SUQADD : SInst<"vuqadd", "sss", "ScSsSiSl">;
+def SCALAR_SUQADD : SInst<"vuqadd", "ssb", "ScSsSiSl">;
// Scalar Unsigned Saturating Accumulated of Signed Value
Modified: cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=365300&r1=365299&r2=365300&view=diff
==
--- cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c (original)
+++ cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Mon Jul 8 01:47:47 2019
@@ -13879,7 +13879,7 @@ int64_t test_vqnegd_s64(int64_t a) {
// CHECK: [[VUQADDB_S8_I:%.*]] = call <8 x i8>
@llvm.aarch64.neon.suqadd.v8i8(<8 x i8> [[TMP0]], <8 x i8> [[TMP1]])
// CHECK: [[TMP2:%.*]] = extractelement <8 x i8> [[VUQADDB_S8_I]], i64 0
// CHECK: ret i8 [[TMP2]]
-int8_t test_vuqaddb_s8(int8_t a, int8_t b) {
+int8_t test_vuqaddb_s8(int8_t a, uint8_t b) {
return (int8_t)vuqaddb_s8(a, b);
}
@@ -13889,21 +13889,21 @@ int8_t test_vuqaddb_s8(int8_t a, int8_t
// CHECK: [[VUQADDH_S16_I:%.*]] = call <4 x i16>
@llvm.aarch64.neon.suqadd.v4i16(<4 x i16> [[TMP0]], <4 x i16> [[TMP1]])
// CHECK: [[TMP2:%.*]] = extractelement <4 x i16> [[VUQADDH_S16_I]], i64 0
// CHECK: ret i16 [[TMP2]]
-int16_t test_vuqaddh_s16(int16_t a, int16_t b) {
+int16_t test_vuqaddh_s16(int16_t a, uint16_t b) {
return (int16_t)vuqaddh_s16(a, b);
}
// CHECK-LABEL: @test_vuqadds_s32(
// CHECK: [[VUQADDS_S32_I:%.*]] = call i32 @llvm.aarch64.neon.suqadd.i32(i32
%a, i32 %b)
// CHECK: ret i32 [[VUQADDS_S32_I]]
-int32_t test_vuqadds_s32(int32_t a, int32_t b) {
+int32_t test_vuqadds_s32(int32_t a, uint32_t b) {
return (int32_t)vuqadds_s32(a, b);
}
// CHECK-LABEL: @test_vuqaddd_s64(
// CHECK: [[VUQADDD_S64_I:%.*]] = call i64 @llvm.aarch64.neon.suqadd.i64(i64
%a, i64 %b)
// CHECK: ret i64 [[VUQADDD_S64_I]]
-int64_t test_vuqaddd_s64(int64_t a, int64_t b) {
+int64_t test_vuqaddd_s64(int64_t a, uint64_t b) {
return (int64_t)vuqaddd_s64(a, b);
}
Added: cfe/trunk/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c?rev=365300&view=auto
==
--- cfe/trunk/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c
(added)
+++ cfe/trunk/test/CodeGen/aarch64-neon-vuqadd-float-conversion-warning.c Mon
Jul 8 01:47:47 2019
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon \
+// RUN: -S -disable-O0-optnone -emit-llvm -o - %s 2>&1 | FileCheck %s
+
+#include
+
+// Check float conversion is not accepted for unsigned int argument
+int8_t test_vuqaddb_s8(){
+ return vuqaddb_s8(1, -1.0f);
+}
+
+int16_t test_vuqaddh_s16() {
+ return vuqaddh_s16(1, -1.0f);
+}
+
+int32_t test_vuqadds_s32() {
+ return vuqadds_s32(1, -1.0f);
+}
+
+int64_t test_vuqaddd_s64() {
+ return vuqaddd_s64(1, -1.0f);
+}
+// CHECK: warning: implicit conversion of out of range value from 'float' to
'uint8_t' (aka 'unsigned char') is undefined
+// CHECK: warning: implicit conversion of out of range value from 'float' to
'uint16_t' (aka 'unsigned short') is undefined
+// CHECK: warning: implicit conversion of out of range value from 'float' to
'uint32_t' (aka 'unsigned int') is undefined
+// CHECK: wa
r365598 - [NFC][AArch64] Fix vector vqtb[lx][1-4]_s8 operand
Author: dnsampaio
Date: Wed Jul 10 01:16:49 2019
New Revision: 365598
URL: http://llvm.org/viewvc/llvm-project?rev=365598&view=rev
Log:
[NFC][AArch64] Fix vector vqtb[lx][1-4]_s8 operand
Summary:
Change the vqtb[lx][1-4]_s8 instrinsics to have the last argument as vector of
unsigned valuse, not
signed, accordingly to
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics
Reviewers: LukeCheeseman, DavidSpickett
Reviewed By: DavidSpickett
Subscribers: DavidSpickett, javed.absar, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D64243
Modified:
cfe/trunk/include/clang/Basic/arm_neon.td
cfe/trunk/test/CodeGen/aarch64-neon-tbl.c
Modified: cfe/trunk/include/clang/Basic/arm_neon.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=365598&r1=365597&r2=365598&view=diff
==
--- cfe/trunk/include/clang/Basic/arm_neon.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon.td Wed Jul 10 01:16:49 2019
@@ -1070,16 +1070,16 @@ def VUZP2 : SOpInst<"vuzp2", "ddd",
// Table lookup
let InstName = "vtbl" in {
-def VQTBL1_A64 : WInst<"vqtbl1", "djt", "UccPcQUcQcQPc">;
-def VQTBL2_A64 : WInst<"vqtbl2", "dBt", "UccPcQUcQcQPc">;
-def VQTBL3_A64 : WInst<"vqtbl3", "dCt", "UccPcQUcQcQPc">;
-def VQTBL4_A64 : WInst<"vqtbl4", "dDt", "UccPcQUcQcQPc">;
+def VQTBL1_A64 : WInst<"vqtbl1", "dju", "UccPcQUcQcQPc">;
+def VQTBL2_A64 : WInst<"vqtbl2", "dBu", "UccPcQUcQcQPc">;
+def VQTBL3_A64 : WInst<"vqtbl3", "dCu", "UccPcQUcQcQPc">;
+def VQTBL4_A64 : WInst<"vqtbl4", "dDu", "UccPcQUcQcQPc">;
}
let InstName = "vtbx" in {
-def VQTBX1_A64 : WInst<"vqtbx1", "ddjt", "UccPcQUcQcQPc">;
-def VQTBX2_A64 : WInst<"vqtbx2", "ddBt", "UccPcQUcQcQPc">;
-def VQTBX3_A64 : WInst<"vqtbx3", "ddCt", "UccPcQUcQcQPc">;
-def VQTBX4_A64 : WInst<"vqtbx4", "ddDt", "UccPcQUcQcQPc">;
+def VQTBX1_A64 : WInst<"vqtbx1", "ddju", "UccPcQUcQcQPc">;
+def VQTBX2_A64 : WInst<"vqtbx2", "ddBu", "UccPcQUcQcQPc">;
+def VQTBX3_A64 : WInst<"vqtbx3", "ddCu", "UccPcQUcQcQPc">;
+def VQTBX4_A64 : WInst<"vqtbx4", "ddDu", "UccPcQUcQcQPc">;
}
Modified: cfe/trunk/test/CodeGen/aarch64-neon-tbl.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-tbl.c?rev=365598&r1=365597&r2=365598&view=diff
==
--- cfe/trunk/test/CodeGen/aarch64-neon-tbl.c (original)
+++ cfe/trunk/test/CodeGen/aarch64-neon-tbl.c Wed Jul 10 01:16:49 2019
@@ -16,7 +16,7 @@ int8x8_t test_vtbl1_s8(int8x8_t a, int8x
// CHECK-LABEL: define <8 x i8> @test_vqtbl1_s8(<16 x i8> %a, <8 x i8> %b) #1 {
// CHECK: [[VTBL1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x
i8> %a, <8 x i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL1_I]]
-int8x8_t test_vqtbl1_s8(int8x16_t a, int8x8_t b) {
+int8x8_t test_vqtbl1_s8(int8x16_t a, uint8x8_t b) {
return vqtbl1_s8(a, b);
}
@@ -59,7 +59,7 @@ int8x8_t test_vtbl2_s8(int8x8x2_t a, int
// CHECK: [[TMP2:%.*]] = load <16 x i8>, <16 x i8>* [[ARRAYIDX2_I]], align 16
// CHECK: [[VTBL2_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl2.v8i8(<16 x
i8> [[TMP1]], <16 x i8> [[TMP2]], <8 x i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL2_I]]
-int8x8_t test_vqtbl2_s8(int8x16x2_t a, int8x8_t b) {
+int8x8_t test_vqtbl2_s8(int8x16x2_t a, uint8x8_t b) {
return vqtbl2_s8(a, b);
}
@@ -109,7 +109,7 @@ int8x8_t test_vtbl3_s8(int8x8x3_t a, int
// CHECK: [[TMP3:%.*]] = load <16 x i8>, <16 x i8>* [[ARRAYIDX4_I]], align 16
// CHECK: [[VTBL3_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl3.v8i8(<16 x
i8> [[TMP1]], <16 x i8> [[TMP2]], <16 x i8> [[TMP3]], <8 x i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL3_I]]
-int8x8_t test_vqtbl3_s8(int8x16x3_t a, int8x8_t b) {
+int8x8_t test_vqtbl3_s8(int8x16x3_t a, uint8x8_t b) {
return vqtbl3_s8(a, b);
}
@@ -165,7 +165,7 @@ int8x8_t test_vtbl4_s8(int8x8x4_t a, int
// CHECK: [[TMP4:%.*]] = load <16 x i8>, <16 x i8>* [[ARRAYIDX6_I]], align 16
// CHECK: [[VTBL4_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl4.v8i8(<16 x
i8> [[TMP1]], <16 x i8> [[TMP2]], <16 x i8> [[TMP3]], <16 x i8> [[TMP4]], <8 x
i8> %b) #3
// CHECK: ret <8 x i8> [[VTBL4_I]]
-int8x8_t test_vqtbl4_s8(int8x16x4_t a, int8x8_t b) {
+int8x8_t test_vqtbl4_s8(int8x16x4_t a, uint8x8_t b) {
return vqtbl4_s8(a, b);
}
@@ -348,7 +348,7 @@ int8x8_t test_vtbx4_s8(int8x8_t a, int8x
// CHECK-LABEL: define <8 x i8> @test_vqtbx1_s8(<8 x i8> %a, <16 x i8> %b, <8
x i8> %c) #1 {
// CHECK: [[VTBX1_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbx1.v8i8(<8 x
i8> %a, <16 x i8> %b, <8 x i8> %c) #3
// CHECK: ret <8 x i8> [[VTBX1_I]]
-int8x8_t test_vqtbx1_s8(int8x8_t a, int8x16_t b, int8x8_t c) {
+int8x8_t test_vqtbx1_s8(int8x8_t
r365608 - [NFC][AArch64] Fix vector vsqadd intrinsics operands
Author: dnsampaio Date: Wed Jul 10 02:58:03 2019 New Revision: 365608 URL: http://llvm.org/viewvc/llvm-project?rev=365608&view=rev Log: [NFC][AArch64] Fix vector vsqadd intrinsics operands Summary: Change the vsqadd vector instrinsics to have the second argument as signed values, not unsigned, accordingly to https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics Reviewers: LukeCheeseman, ostannard Reviewed By: ostannard Subscribers: javed.absar, kristof.beyls, cfe-commits Tags: #clang Differential Revision: https://reviews.llvm.org/D64210 Modified: cfe/trunk/include/clang/Basic/arm_neon.td Modified: cfe/trunk/include/clang/Basic/arm_neon.td URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=365608&r1=365607&r2=365608&view=diff == --- cfe/trunk/include/clang/Basic/arm_neon.td (original) +++ cfe/trunk/include/clang/Basic/arm_neon.td Wed Jul 10 02:58:03 2019 @@ -707,7 +707,7 @@ def SUQADD : SInst<"vuqadd", "ddd", "csi // Unsigned Saturating Accumulated of Signed Value -def USQADD : SInst<"vsqadd", "ddd", "UcUsUiUlQUcQUsQUiQUl">; +def USQADD : SInst<"vsqadd", "ddx", "UcUsUiUlQUcQUsQUiQUl">; // Reciprocal/Sqrt ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
r365609 - [AArch64] Fix vector vuqadd intrinsics operands
Author: dnsampaio
Date: Wed Jul 10 02:58:51 2019
New Revision: 365609
URL: http://llvm.org/viewvc/llvm-project?rev=365609&view=rev
Log:
[AArch64] Fix vector vuqadd intrinsics operands
Summary:
Change the vuqadd vector instrinsics to have the second argument as unsigned
values, not signed,
accordingly to
https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics
Reviewers: LukeCheeseman, ostannard
Reviewed By: ostannard
Subscribers: javed.absar, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D64211
Modified:
cfe/trunk/include/clang/Basic/arm_neon.td
cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
Modified: cfe/trunk/include/clang/Basic/arm_neon.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/arm_neon.td?rev=365609&r1=365608&r2=365609&view=diff
==
--- cfe/trunk/include/clang/Basic/arm_neon.td (original)
+++ cfe/trunk/include/clang/Basic/arm_neon.td Wed Jul 10 02:58:51 2019
@@ -703,7 +703,7 @@ def QNEG : SInst<"vqneg", "dd", "lQl">
// Signed Saturating Accumulated of Unsigned Value
-def SUQADD : SInst<"vuqadd", "ddd", "csilQcQsQiQl">;
+def SUQADD : SInst<"vuqadd", "ddu", "csilQcQsQiQl">;
// Unsigned Saturating Accumulated of Signed Value
Modified: cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c?rev=365609&r1=365608&r2=365609&view=diff
==
--- cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c (original)
+++ cfe/trunk/test/CodeGen/aarch64-neon-intrinsics.c Wed Jul 10 02:58:51 2019
@@ -17528,6 +17528,50 @@ float64_t test_vabdd_f64(float64_t a, fl
return vabdd_f64(a, b);
}
+// CHECK-LABEL: @test_vuqaddq_s8(
+// CHECK: entry:
+// CHECK-NEXT: [[V:%.*]] = call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16
x i8> %a, <16 x i8> %b)
+// CHECK-NEXT: ret <16 x i8> [[V]]
+int8x16_t test_vuqaddq_s8(int8x16_t a, uint8x16_t b) {
+ return vuqaddq_s8(a, b);
+}
+
+// CHECK-LABEL: @test_vuqaddq_s32(
+// CHECK: [[V:%.*]] = call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32>
%a, <4 x i32> %b)
+// CHECK-NEXT: ret <4 x i32> [[V]]
+int32x4_t test_vuqaddq_s32(int32x4_t a, uint32x4_t b) {
+ return vuqaddq_s32(a, b);
+}
+
+// CHECK-LABEL: @test_vuqaddq_s64(
+// CHECK: [[V:%.*]] = call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64>
%a, <2 x i64> %b)
+// CHECK-NEXT: ret <2 x i64> [[V]]
+int64x2_t test_vuqaddq_s64(int64x2_t a, uint64x2_t b) {
+ return vuqaddq_s64(a, b);
+}
+
+// CHECK-LABEL: @test_vuqaddq_s16(
+// CHECK: [[V:%.*]] = call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16>
%a, <8 x i16> %b)
+// CHECK-NEXT: ret <8 x i16> [[V]]
+int16x8_t test_vuqaddq_s16(int16x8_t a, uint16x8_t b) {
+ return vuqaddq_s16(a, b);
+}
+
+// CHECK-LABEL: @test_vuqadd_s8(
+// CHECK: entry:
+// CHECK-NEXT: [[V:%.*]] = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x
i8> %a, <8 x i8> %b)
+// CHECK-NEXT: ret <8 x i8> [[V]]
+int8x8_t test_vuqadd_s8(int8x8_t a, uint8x8_t b) {
+ return vuqadd_s8(a, b);
+}
+
+// CHECK-LABEL: @test_vuqadd_s32(
+// CHECK: [[V:%.*]] = call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32>
%a, <2 x i32> %b)
+// CHECK-NEXT: ret <2 x i32> [[V]]
+int32x2_t test_vuqadd_s32(int32x2_t a, uint32x2_t b) {
+ return vuqadd_s32(a, b);
+}
+
// CHECK-LABEL: @test_vuqadd_s64(
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
@@ -17537,6 +17581,13 @@ int64x1_t test_vuqadd_s64(int64x1_t a, u
return vuqadd_s64(a, b);
}
+// CHECK-LABEL: @test_vuqadd_s16(
+// CHECK: [[V:%.*]] = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16>
%a, <4 x i16> %b)
+// CHECK-NEXT: ret <4 x i16> [[V]]
+int16x4_t test_vuqadd_s16(int16x4_t a, uint16x4_t b) {
+ return vuqadd_s16(a, b);
+}
+
// CHECK-LABEL: @test_vsqadd_u64(
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
___
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r371597 - [ARM] Take into account -mcpu and -mfpu options while handling 'crypto' feature
Author: dnsampaio
Date: Wed Sep 11 02:06:17 2019
New Revision: 371597
URL: http://llvm.org/viewvc/llvm-project?rev=371597&view=rev
Log:
[ARM] Take into account -mcpu and -mfpu options while handling 'crypto' feature
Submittin in behalf of krisb (Kristina Bessonova)
Summary:
'+crypto' means '+aes' and '+sha2' for arch >= ARMv8 when they were
not disabled explicitly. But this is correctly handled only in case of
'-march' option, though the feature may also be specified through
the '-mcpu' or '-mfpu' options. In the following example:
$ clang -mcpu=cortex-a57 -mfpu=crypto-neon-fp-armv8
'aes' and 'sha2' are disabled that is quite unexpected:
$ clang -cc1 -triple armv8--- -target-cpu cortex-a57
<...> -target-feature -sha2 -target-feature -aes -target-feature +crypto
This exposed by https://reviews.llvm.org/D63936 that makes
the 'aes' and 'sha2' features disabled by default.
So, while handling the 'crypto' feature we need to take into account:
- a CPU name, as it provides the information about architecture
(if no '-march' option specified),
- features, specified by the '-mcpu' and '-mfpu' options.
Reviewers: SjoerdMeijer, ostannard, labrinea, dnsampaio
Reviewed By: dnsampaio
Subscribers: ikudrin, javed.absar, kristof.beyls, cfe-commits
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66018
Author: krisb
Modified:
cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
cfe/trunk/test/Driver/arm-features.c
Modified: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td?rev=371597&r1=371596&r2=371597&view=diff
==
--- cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td (original)
+++ cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td Wed Sep 11 02:06:17
2019
@@ -384,6 +384,9 @@ def warn_target_unsupported_abs2008 : Wa
def warn_target_unsupported_compact_branches : Warning<
"ignoring '-mcompact-branches=' option because the '%0' architecture does
not"
" support it">, InGroup;
+def warn_target_unsupported_extension : Warning<
+ "ignoring extension '%0' because the '%1' architecture does not support it">,
+ InGroup;
def warn_drv_unsupported_gpopt : Warning<
"ignoring '-mgpopt' option as it cannot be used with %select{|the implicit"
" usage of }0-mabicalls">,
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp?rev=371597&r1=371596&r2=371597&view=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp Wed Sep 11 02:06:17 2019
@@ -477,23 +477,26 @@ fp16_fml_fallthrough:
Features.push_back("-crc");
}
- // For Arch >= ARMv8.0: crypto = sha2 + aes
+ // For Arch >= ARMv8.0 && A profile: crypto = sha2 + aes
// FIXME: this needs reimplementation after the TargetParser rewrite
- if (ArchName.find_lower("armv8a") != StringRef::npos ||
- ArchName.find_lower("armv8.1a") != StringRef::npos ||
- ArchName.find_lower("armv8.2a") != StringRef::npos ||
- ArchName.find_lower("armv8.3a") != StringRef::npos ||
- ArchName.find_lower("armv8.4a") != StringRef::npos) {
-if (ArchName.find_lower("+crypto") != StringRef::npos) {
- if (ArchName.find_lower("+nosha2") == StringRef::npos)
+ auto CryptoIt =
+llvm::find_if(llvm::reverse(Features),
+ [](const StringRef F) { return F.contains("crypto"); });
+ if (CryptoIt != Features.rend() && CryptoIt->take_front() == "+") {
+StringRef ArchSuffix = arm::getLLVMArchSuffixForARM(
+arm::getARMTargetCPU(CPUName, ArchName, Triple), ArchName, Triple);
+if (llvm::ARM::parseArchVersion(ArchSuffix) >= 8 &&
+llvm::ARM::parseArchProfile(ArchSuffix) == llvm::ARM::ProfileKind::A) {
+ if (ArchName.find_lower("+nosha2") == StringRef::npos &&
+ CPUName.find_lower("+nosha2") == StringRef::npos)
Features.push_back("+sha2");
- if (ArchName.find_lower("+noaes") == StringRef::npos)
+ if (ArchName.find_lower("+noaes") == StringRef::npos &&
+ CPUName.find_lower("+noaes") == StringRef::npos)
Features.push_back("+aes");
-} else if (ArchName.find_lower("-crypto") != StringRef::npos) {
- if (ArchName.find_lower("+sha2") == StringRef::npos)
-Features.push_back("-sha2");
- if (ArchName.find_lower("+aes") == StringRef::npos)
-Features.push_back("-aes");
+} else {
+ D.Diag(clang::diag::warn_target_unsupported_extension)
+<< "crypto" <<
llvm::ARM::getArchName(llvm::ARM::parseArch(ArchSuffix));
+ Features.push_back("-crypto");
}
}
@@ -655,7 +658,7 @@ std::string arm::getARMTargetCPU(StringR
llvm::ARM::ArchKind
r374785 - [ARM] Preserve fpu behaviour for '-crypto'
Author: dnsampaio
Date: Mon Oct 14 09:29:26 2019
New Revision: 374785
URL: http://llvm.org/viewvc/llvm-project?rev=374785&view=rev
Log:
[ARM] Preserve fpu behaviour for '-crypto'
Summary:
This patch restores the behaviour that -fpu overwrites the
architecture obtained from -march or -mcpu flags, not enforcing to
disable 'crypto' if march=armv7 and mfpu=neon-fp-armv8.
However, it does warn that 'crypto' is ignored when passing
mfpu=crypto-neon-fp-armv8.
Reviewers: peter.smith, labrinea
Reviewed By: peter.smith
Subscribers: nickdesaulniers, kristof.beyls, dmgreen, cfe-commits, krisb
Tags: #clang
Differential Revision: https://reviews.llvm.org/D67608
Modified:
cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
cfe/trunk/test/Driver/arm-features.c
Modified: cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp?rev=374785&r1=374784&r2=374785&view=diff
==
--- cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp (original)
+++ cfe/trunk/lib/Driver/ToolChains/Arch/ARM.cpp Mon Oct 14 09:29:26 2019
@@ -479,24 +479,33 @@ fp16_fml_fallthrough:
// For Arch >= ARMv8.0 && A profile: crypto = sha2 + aes
// FIXME: this needs reimplementation after the TargetParser rewrite
- auto CryptoIt =
-llvm::find_if(llvm::reverse(Features),
- [](const StringRef F) { return F.contains("crypto"); });
- if (CryptoIt != Features.rend() && CryptoIt->take_front() == "+") {
-StringRef ArchSuffix = arm::getLLVMArchSuffixForARM(
-arm::getARMTargetCPU(CPUName, ArchName, Triple), ArchName, Triple);
-if (llvm::ARM::parseArchVersion(ArchSuffix) >= 8 &&
-llvm::ARM::parseArchProfile(ArchSuffix) == llvm::ARM::ProfileKind::A) {
- if (ArchName.find_lower("+nosha2") == StringRef::npos &&
- CPUName.find_lower("+nosha2") == StringRef::npos)
-Features.push_back("+sha2");
- if (ArchName.find_lower("+noaes") == StringRef::npos &&
- CPUName.find_lower("+noaes") == StringRef::npos)
-Features.push_back("+aes");
-} else {
- D.Diag(clang::diag::warn_target_unsupported_extension)
-<< "crypto" <<
llvm::ARM::getArchName(llvm::ARM::parseArch(ArchSuffix));
- Features.push_back("-crypto");
+ auto CryptoIt = llvm::find_if(llvm::reverse(Features), [](const StringRef F)
{
+return F.contains("crypto");
+ });
+ if (CryptoIt != Features.rend()) {
+if (CryptoIt->take_front() == "+") {
+ StringRef ArchSuffix = arm::getLLVMArchSuffixForARM(
+ arm::getARMTargetCPU(CPUName, ArchName, Triple), ArchName, Triple);
+ if (llvm::ARM::parseArchVersion(ArchSuffix) >= 8 &&
+ llvm::ARM::parseArchProfile(ArchSuffix) ==
+ llvm::ARM::ProfileKind::A) {
+if (ArchName.find_lower("+nosha2") == StringRef::npos &&
+CPUName.find_lower("+nosha2") == StringRef::npos)
+ Features.push_back("+sha2");
+if (ArchName.find_lower("+noaes") == StringRef::npos &&
+CPUName.find_lower("+noaes") == StringRef::npos)
+ Features.push_back("+aes");
+ } else {
+D.Diag(clang::diag::warn_target_unsupported_extension)
+<< "crypto"
+<< llvm::ARM::getArchName(llvm::ARM::parseArch(ArchSuffix));
+// With -fno-integrated-as -mfpu=crypto-neon-fp-armv8 some assemblers
such as the GNU assembler
+// will permit the use of crypto instructions as the fpu will override
the architecture.
+// We keep the crypto feature in this case to preserve compatibility.
+// In all other cases we remove the crypto feature.
+if (!Args.hasArg(options::OPT_fno_integrated_as))
+ Features.push_back("-crypto");
+ }
}
}
Modified: cfe/trunk/test/Driver/arm-features.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/Driver/arm-features.c?rev=374785&r1=374784&r2=374785&view=diff
==
--- cfe/trunk/test/Driver/arm-features.c (original)
+++ cfe/trunk/test/Driver/arm-features.c Mon Oct 14 09:29:26 2019
@@ -79,3 +79,18 @@
// RUN: %clang -target arm-arm-none-eabi -mcpu=cortex-m23+crypto -### -c %s
2>&1 | FileCheck -check-prefix=CHECK-NOCRYPTO5 %s
// CHECK-NOCRYPTO5: warning: ignoring extension 'crypto' because the {{.*}}
architecture does not support it
// CHECK-NOCRYPTO5-NOT: "-target-feature" "+crypto"{{.*}} "-target-feature"
"+sha2" "-target-feature" "+aes"
+//
+// Check +crypto does not affect -march=armv7a -mfpu=crypto-neon-fp-armv8, but
it does warn that +crypto has no effect
+// RUN: %clang -target arm-none-none-eabi -fno-integrated-as -march=armv7a
-mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck
-check-prefixes=CHECK-WARNONLY,ALL %s
+// RUN: %clang -target arm-none-none-eabi -fno-integrated-as -march=armv7a+aes
-mfpu=crypto-neon-fp-armv8 -### -c %s 2>&1 | FileCheck
-check
r370716 - [ARM NEON] Avoid duplicated decarations
Author: dnsampaio
Date: Tue Sep 3 02:16:44 2019
New Revision: 370716
URL: http://llvm.org/viewvc/llvm-project?rev=370716&view=rev
Log:
[ARM NEON] Avoid duplicated decarations
Summary:
The declaration of arm neon intrinsics that are
"big endian safe" print the same code for big
and small endian targets.
This patch avoids duplicates by checking if an
intrinsic is safe to have a single definition.
(decreases header 11k lines out of 73k).
Reviewers: t.p.northover, ostannard, labrinea
Reviewed By: ostannard
Subscribers: kristof.beyls, cfe-commits, olista01
Tags: #clang
Differential Revision: https://reviews.llvm.org/D66588
Modified:
cfe/trunk/utils/TableGen/NeonEmitter.cpp
Modified: cfe/trunk/utils/TableGen/NeonEmitter.cpp
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/utils/TableGen/NeonEmitter.cpp?rev=370716&r1=370715&r2=370716&view=diff
==
--- cfe/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ cfe/trunk/utils/TableGen/NeonEmitter.cpp Tue Sep 3 02:16:44 2019
@@ -332,6 +332,17 @@ class Intrinsic {
NeonEmitter &Emitter;
std::stringstream OS;
+ bool isBigEndianSafe() const {
+if (BigEndianSafe)
+ return true;
+
+for (const auto &T : Types){
+ if (T.isVector() && T.getNumElements() > 1)
+return false;
+}
+return true;
+ }
+
public:
Intrinsic(Record *R, StringRef Name, StringRef Proto, TypeSpec OutTS,
TypeSpec InTS, ClassKind CK, ListInit *Body, NeonEmitter &Emitter,
@@ -1293,7 +1304,7 @@ void Intrinsic::emitReverseVariable(Vari
}
void Intrinsic::emitArgumentReversal() {
- if (BigEndianSafe)
+ if (isBigEndianSafe())
return;
// Reverse all vector arguments.
@@ -1314,7 +1325,7 @@ void Intrinsic::emitArgumentReversal() {
}
void Intrinsic::emitReturnReversal() {
- if (BigEndianSafe)
+ if (isBigEndianSafe())
return;
if (!getReturnType().isVector() || getReturnType().isVoid() ||
getReturnType().getNumElements() == 1)
@@ -1578,7 +1589,10 @@ std::pair Intrinsic::
Intr.Dependencies.insert(&Callee);
// Now create the call itself.
- std::string S = CallPrefix.str() + Callee.getMangledName(true) + "(";
+ std::string S = "";
+ if (!Callee.isBigEndianSafe())
+S += CallPrefix.str();
+ S += Callee.getMangledName(true) + "(";
for (unsigned I = 0; I < DI->getNumArgs() - 1; ++I) {
if (I != 0)
S += ", ";
@@ -1889,6 +1903,11 @@ Intrinsic::DagEmitter::emitDagArg(Init *
}
std::string Intrinsic::generate() {
+ // Avoid duplicated code for big and little endian
+ if (isBigEndianSafe()) {
+generateImpl(false, "", "");
+return OS.str();
+ }
// Little endian intrinsics are simple and don't require any argument
// swapping.
OS << "#ifdef __LITTLE_ENDIAN__\n";
___
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cfe-commits@lists.llvm.org
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r371410 - [NFC] Add aacps bitfields access test
Author: dnsampaio
Date: Mon Sep 9 08:39:45 2019
New Revision: 371410
URL: http://llvm.org/viewvc/llvm-project?rev=371410&view=rev
Log:
[NFC] Add aacps bitfields access test
Added:
cfe/trunk/test/CodeGen/aapcs-bitfield.c
Added: cfe/trunk/test/CodeGen/aapcs-bitfield.c
URL:
http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/aapcs-bitfield.c?rev=371410&view=auto
==
--- cfe/trunk/test/CodeGen/aapcs-bitfield.c (added)
+++ cfe/trunk/test/CodeGen/aapcs-bitfield.c Mon Sep 9 08:39:45 2019
@@ -0,0 +1,824 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple armv8-none-linux-eabi %s -emit-llvm -o - -O3 |
FileCheck %s -check-prefix=LE
+// RUN: %clang_cc1 -triple armebv8-none-linux-eabi %s -emit-llvm -o - -O3 |
FileCheck %s -check-prefix=BE
+
+struct st0 {
+ short c : 7;
+};
+
+// LE-LABEL: @st0_check_load(
+// LE-NEXT: entry:
+// LE-NEXT:[[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ST0:%.*]],
%struct.st0* [[M:%.*]], i32 0, i32 0
+// LE-NEXT:[[BF_LOAD:%.*]] = load i8, i8* [[TMP0]], align 2
+// LE-NEXT:[[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 1
+// LE-NEXT:[[BF_ASHR:%.*]] = ashr exact i8 [[BF_SHL]], 1
+// LE-NEXT:[[CONV:%.*]] = sext i8 [[BF_ASHR]] to i32
+// LE-NEXT:ret i32 [[CONV]]
+//
+// BE-LABEL: @st0_check_load(
+// BE-NEXT: entry:
+// BE-NEXT:[[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ST0:%.*]],
%struct.st0* [[M:%.*]], i32 0, i32 0
+// BE-NEXT:[[BF_LOAD:%.*]] = load i8, i8* [[TMP0]], align 2
+// BE-NEXT:[[BF_ASHR:%.*]] = ashr i8 [[BF_LOAD]], 1
+// BE-NEXT:[[CONV:%.*]] = sext i8 [[BF_ASHR]] to i32
+// BE-NEXT:ret i32 [[CONV]]
+//
+int st0_check_load(struct st0 *m) {
+ return m->c;
+}
+
+// LE-LABEL: @st0_check_store(
+// LE-NEXT: entry:
+// LE-NEXT:[[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ST0:%.*]],
%struct.st0* [[M:%.*]], i32 0, i32 0
+// LE-NEXT:[[BF_LOAD:%.*]] = load i8, i8* [[TMP0]], align 2
+// LE-NEXT:[[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], -128
+// LE-NEXT:[[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 1
+// LE-NEXT:store i8 [[BF_SET]], i8* [[TMP0]], align 2
+// LE-NEXT:ret void
+//
+// BE-LABEL: @st0_check_store(
+// BE-NEXT: entry:
+// BE-NEXT:[[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ST0:%.*]],
%struct.st0* [[M:%.*]], i32 0, i32 0
+// BE-NEXT:[[BF_LOAD:%.*]] = load i8, i8* [[TMP0]], align 2
+// BE-NEXT:[[BF_CLEAR:%.*]] = and i8 [[BF_LOAD]], 1
+// BE-NEXT:[[BF_SET:%.*]] = or i8 [[BF_CLEAR]], 2
+// BE-NEXT:store i8 [[BF_SET]], i8* [[TMP0]], align 2
+// BE-NEXT:ret void
+//
+void st0_check_store(struct st0 *m) {
+ m->c = 1;
+}
+
+struct st1 {
+ int a : 10;
+ short c : 6;
+};
+
+// LE-LABEL: @st1_check_load(
+// LE-NEXT: entry:
+// LE-NEXT:[[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ST1:%.*]],
%struct.st1* [[M:%.*]], i32 0, i32 0
+// LE-NEXT:[[BF_LOAD:%.*]] = load i16, i16* [[TMP0]], align 4
+// LE-NEXT:[[BF_ASHR:%.*]] = ashr i16 [[BF_LOAD]], 10
+// LE-NEXT:[[CONV:%.*]] = sext i16 [[BF_ASHR]] to i32
+// LE-NEXT:ret i32 [[CONV]]
+//
+// BE-LABEL: @st1_check_load(
+// BE-NEXT: entry:
+// BE-NEXT:[[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ST1:%.*]],
%struct.st1* [[M:%.*]], i32 0, i32 0
+// BE-NEXT:[[BF_LOAD:%.*]] = load i16, i16* [[TMP0]], align 4
+// BE-NEXT:[[BF_SHL:%.*]] = shl i16 [[BF_LOAD]], 10
+// BE-NEXT:[[BF_ASHR:%.*]] = ashr exact i16 [[BF_SHL]], 10
+// BE-NEXT:[[CONV:%.*]] = sext i16 [[BF_ASHR]] to i32
+// BE-NEXT:ret i32 [[CONV]]
+//
+int st1_check_load(struct st1 *m) {
+ return m->c;
+}
+
+// LE-LABEL: @st1_check_store(
+// LE-NEXT: entry:
+// LE-NEXT:[[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ST1:%.*]],
%struct.st1* [[M:%.*]], i32 0, i32 0
+// LE-NEXT:[[BF_LOAD:%.*]] = load i16, i16* [[TMP0]], align 4
+// LE-NEXT:[[BF_CLEAR:%.*]] = and i16 [[BF_LOAD]], 1023
+// LE-NEXT:[[BF_SET:%.*]] = or i16 [[BF_CLEAR]], 1024
+// LE-NEXT:store i16 [[BF_SET]], i16* [[TMP0]], align 4
+// LE-NEXT:ret void
+//
+// BE-LABEL: @st1_check_store(
+// BE-NEXT: entry:
+// BE-NEXT:[[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ST1:%.*]],
%struct.st1* [[M:%.*]], i32 0, i32 0
+// BE-NEXT:[[BF_LOAD:%.*]] = load i16, i16* [[TMP0]], align 4
+// BE-NEXT:[[BF_CLEAR:%.*]] = and i16 [[BF_LOAD]], -64
+// BE-NEXT:[[BF_SET:%.*]] = or i16 [[BF_CLEAR]], 1
+// BE-NEXT:store i16 [[BF_SET]], i16* [[TMP0]], align 4
+// BE-NEXT:ret void
+//
+void st1_check_store(struct st1 *m) {
+ m->c = 1;
+}
+
+struct st2 {
+ int a : 10;
+ short c : 7;
+};
+
+// LE-LABEL: @st2_check_load(
+// LE-NEXT: entry:
+// LE-NEXT:[[C:%.*]] = getelementptr inbounds [[STRUCT_ST2:%.*]],
%struct.st2* [[M:%.*]], i32 0, i32 1
+// LE-NEXT:[[BF_LOAD:%.*]] = load i8, i8* [[C]], align 2
+// LE-NEXT:[[BF_SHL:%.*]] = shl i8 [[BF_LOAD]], 1
+// LE-NEXT:[[BF_ASHR:%.*]] = ashr exact i8 [[BF_SHL]], 1
