[PATCH] D68021: [IntrinsicEmitter] Add overloaded type VecOfBitcastsToInt for SVE intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes accepted this revision.
c-rhodes added a comment.
This revision is now accepted and ready to land.

LGTM

Looks like a pretty straightforward change. Might be worth waiting a day or so 
before committing incase anyone else has any comments.


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[PATCH] D68023: [AArch64][SVE] Implement int_aarch64_sve_cnt intrinsic

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes accepted this revision.
c-rhodes added a comment.
This revision is now accepted and ready to land.

LGTM




Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:100-104
+  defm CLS_ZPmZ  : sve_int_un_pred_arit_1<   0b000, "cls", null_frag>;
+  defm CLZ_ZPmZ  : sve_int_un_pred_arit_1<   0b001, "clz", null_frag>;
+  defm CNT_ZPmZ  : sve_int_un_pred_arit_1<   0b010, "cnt", 
int_aarch64_sve_cnt>;
+  defm CNOT_ZPmZ : sve_int_un_pred_arit_1<   0b011, "cnot", null_frag>;
+  defm NOT_ZPmZ  : sve_int_un_pred_arit_1<   0b110, "not", null_frag>;

nit: align last argument


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[PATCH] D68380: [Driver] NFC: Remove duplicate call to getLibGccType

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added a reviewer: saugustine.

https://reviews.llvm.org/D68380

Files:
  clang/lib/Driver/ToolChains/CommonArgs.cpp


Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -1186,7 +1186,6 @@
   case ToolChain::UNW_None:
 return;
   case ToolChain::UNW_Libgcc: {
-LibGccType LGT = getLibGccType(D, Args);
 if (LGT == LibGccType::StaticLibGcc)
   CmdArgs.push_back("-lgcc_eh");
 else


Index: clang/lib/Driver/ToolChains/CommonArgs.cpp
===
--- clang/lib/Driver/ToolChains/CommonArgs.cpp
+++ clang/lib/Driver/ToolChains/CommonArgs.cpp
@@ -1186,7 +1186,6 @@
   case ToolChain::UNW_None:
 return;
   case ToolChain::UNW_Libgcc: {
-LibGccType LGT = getLibGccType(D, Args);
 if (LGT == LibGccType::StaticLibGcc)
   CmdArgs.push_back("-lgcc_eh");
 else
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[PATCH] D68380: [Driver] NFC: Remove duplicate call to getLibGccType

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL373712: [Driver] NFC: Remove duplicate call to getLibGccType 
(authored by c-rhodes, committed by ).
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D68380?vs=222977&id=223169#toc

Repository:
  rL LLVM

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Files:
  cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp


Index: cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
+++ cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
@@ -1186,7 +1186,6 @@
   case ToolChain::UNW_None:
 return;
   case ToolChain::UNW_Libgcc: {
-LibGccType LGT = getLibGccType(D, Args);
 if (LGT == LibGccType::StaticLibGcc)
   CmdArgs.push_back("-lgcc_eh");
 else


Index: cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
+++ cfe/trunk/lib/Driver/ToolChains/CommonArgs.cpp
@@ -1186,7 +1186,6 @@
   case ToolChain::UNW_None:
 return;
   case ToolChain::UNW_Libgcc: {
-LibGccType LGT = getLibGccType(D, Args);
 if (LGT == LibGccType::StaticLibGcc)
   CmdArgs.push_back("-lgcc_eh");
 else
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[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 278430.
c-rhodes added a comment.

Changes:

- Documented internal type attributes.
- Set `ASTNode = 0` on user-facing `ArmSveVectorBitsAttr` as the internal type 
attrs are used in the AST. Also removed the case for this from `TypePrinter`.
- `getSveVectorWidth` now returns an `unsigned`. Added an unreachable if `T` 
has no attrs.
- `s/getArmSveVectorBits/getBitwidthForAttributedSveType`. Also now returns an 
`unsigned` and asserts if `!T->isVLST()`.
- Add a few comments in test and reduced them a little so we dont tell all 
types for structs / unions etc.


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Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -60,3 +60,165 @@
 typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
 typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(N)));// expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svint8x2_t' (aka '__clang_svint8x2_t')}}
 typedef svfloat32x3_t badtype5 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svfloat32x3_t' (aka '__clang_svfloat32x3_t')}}
+
+// Test that we can define non-local fixed-length SVE types (unsupported for
+// sizeless types).
+fixed_int8_t global_int8;
+fixed_bfloat16_t global_bfloat16;
+fixed_bool_t global_bool;
+
+extern fixed_int8_t extern_int8;
+extern fixed_bfloat16_t extern_bfloat16;
+extern fixed_bool_t extern_bool;
+
+static fixed_int8_t static_int8;
+static fixed_bfloat16_t static_bfloat16;
+static fixed_bool_t static_bool;
+
+fixed_int8_t *global_int8_ptr;
+extern fixed_int8_t *extern_int8_ptr;
+static fixed_int8_t *static_int8_ptr;
+__thread fixed_int8_t thread_int8;
+
+typedef fixed_int8_t int8_typedef;
+typedef fixed_int8_t *int8_ptr_typedef;
+
+// Test sized expressions
+int sizeof_int8 = sizeof(global_int8);
+int sizeof_int8_var = sizeof(*global_int8_ptr);
+int sizeof_int8_var_ptr = sizeof(global_int8_ptr);
+
+extern fixed_int8_t *extern_int8_ptr;
+
+int alignof_int8 = __alignof__(extern_int8);
+int alignof_int8_var = __alignof__(*extern_int8_ptr);
+int alignof_int8_var_ptr = __alignof__(extern_int8_ptr);
+
+void f(int c) {
+  fixed_int8_t fs8;
+  svint8_t ss8;
+
+  void *sel __attribute__((unused));
+  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types ('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
+  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types ('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}
+}
+
+// --//
+// Sizeof
+
+#define VECTOR_SIZE ((N / 8))
+#define PRED_SIZE ((N / 64))
+
+_Static_assert(sizeof(fixed_int8_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_int16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_uint8_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_float16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bfloat16_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bool_t) == PRED_SIZE, "");
+
+// --//
+// Alignof
+
+#define VECTOR_ALIGN 16
+#define PRED_ALIGN 2
+
+_Static_assert(__alignof__(fixed_int8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_uint8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_float16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_float32_t) == VECTOR_ALIGN, "");
+_Static_assert(__aligno

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked 6 inline comments as done.
c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/Attr.td:1541
 
+def ArmSveVectorBits128 : TypeAttr {
+  let Spellings = [];

aaron.ballman wrote:
> aaron.ballman wrote:
> > c-rhodes wrote:
> > > sdesmalen wrote:
> > > > aaron.ballman wrote:
> > > > > sdesmalen wrote:
> > > > > > nit: Can you add a comment saying why these are undocumented (and 
> > > > > > have no spellings)
> > > > > Also, I think these are all missing `let SemaHandler = 0;` and `let 
> > > > > ASTNode = 0;`
> > > > > 
> > > > > Is there a reason why we need N different type attributes instead of 
> > > > > having a single type attribute which encodes the N as an argument? I 
> > > > > think this may simplify the patch somewhat as you no longer need to 
> > > > > switch over N as much.
> > > > > Is there a reason why we need N different type attributes instead of 
> > > > > having a single type attribute which encodes the N as an argument?
> > > > AIUI this was a workaround for getting the value of N from an 
> > > > AttributedType, because this only has `getAttrKind` to return the 
> > > > attribute kind, but no way to get the corresponding argument/value. 
> > > > This seemed like a simple way to do that without having to create a new 
> > > > subclass for Type and having to support that in various places. Is the 
> > > > latter the approach you were thinking of? (or is there perhaps a 
> > > > simpler way?)
> > > > Also, I think these are all missing let SemaHandler = 0; and let 
> > > > ASTNode = 0;
> > > 
> > > Good to know. In SemaType I'm doing `CurType = State.getAttributedType(A, 
> > > CurType, CurType);` which gives an `AttributedType` in the AST, should I 
> > > still set `let ASTNode = 0;` in this case?
> > > 
> > > > Is there a reason why we need N different type attributes instead of 
> > > > having a single type attribute which encodes the N as an argument?
> > > 
> > > As Sander mentioned, it seemed like the easiest solution, interested to 
> > > know if there's a better approach however
> > I was thinking specifically of creating a new `Type` subclass and 
> > supporting it rather than adding 5 new attributes that only vary by a 
> > bit-width (which means there's likely to be a 6th someday). It's not 
> > immediately clear to me whether that's a really big ask for little gain or 
> > not, though.
> Ah, you're right, we may still need `ASTNode` to be kept around for that, 
> good call.
> Also, I think these are all missing let SemaHandler = 0; and let ASTNode = 0;

I've added `let SemaHandler = 0;` for the internal types and `let ASTNode = 0;` 
for the user-facing attr.



Comment at: clang/lib/AST/ASTContext.cpp:1897
+
+bool ASTContext::getArmSveVectorBits(const Type *T, unsigned &Width) const {
+  if (!T->isVLST())

sdesmalen wrote:
> nit: I find this name a bit misleading, because I would expect the 
> (ARM_SVE_VECTOR_) bits to be the same regardless of the type. Maybe rename 
> this to `getBitwidthForAttributedSveType` ?
> nit: I find this name a bit misleading, because I would expect the 
> (ARM_SVE_VECTOR_) bits to be the same regardless of the type. Maybe rename 
> this to getBitwidthForAttributedSveType ?

You're right, poor choice of name, I've updated it



Comment at: clang/lib/Sema/SemaType.cpp:7754
 /// the ACLE, such as svint32_t and svbool_t.
-static void HandleArmSveVectorBitsTypeAttr(QualType &CurType,
-   const ParsedAttr &Attr, Sema &S) {
+static void HandleArmSveVectorBitsTypeAttr(TypeProcessingState &State,
+   QualType &CurType,

sdesmalen wrote:
> Unrelated changes?
> Unrelated changes?

`TypeProcessingState &State` is required to create an attributed type and 
`Sema` is attached to this so I removed it from the interface. This is inline 
with other attributed type handlers. I pulled `S.Context` out as it's used 
frequently.



Comment at: clang/lib/Sema/SemaType.cpp:7839
+  default:
+llvm_unreachable("unsupported vector size!");
+  case 128:

sdesmalen wrote:
> If we only support power-of-two for now, we should only have an 
> `llvm_unreachable` if we prevent parsing any of the other widths (and give an 
> appropriate diagnostic saying those widths are not yet supported).
> If we only support power-of-two for now, we should only have an 
> llvm_unreachable if we prevent parsing any of the other widths (and give an 
> appropriate diagnostic saying those widths are not yet supported).

Now that we check `VecSize != S.getLangOpts().ArmSveVectorBits` above I think 
this is ok as this shouldn't be reachable with `-msve-vector-bits=` 
validating the vector size.



Comment at: clang/test/Sema/attr-arm-sve-vector-bits.c:80
+  void *sel __attribute__((unused));
+  sel = c ? ss8 : fs8; // expected-error {{incompatib

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/Attr.td:1541
 
+def ArmSveVectorBits128 : TypeAttr {
+  let Spellings = [];

c-rhodes wrote:
> aaron.ballman wrote:
> > aaron.ballman wrote:
> > > c-rhodes wrote:
> > > > sdesmalen wrote:
> > > > > aaron.ballman wrote:
> > > > > > sdesmalen wrote:
> > > > > > > nit: Can you add a comment saying why these are undocumented (and 
> > > > > > > have no spellings)
> > > > > > Also, I think these are all missing `let SemaHandler = 0;` and `let 
> > > > > > ASTNode = 0;`
> > > > > > 
> > > > > > Is there a reason why we need N different type attributes instead 
> > > > > > of having a single type attribute which encodes the N as an 
> > > > > > argument? I think this may simplify the patch somewhat as you no 
> > > > > > longer need to switch over N as much.
> > > > > > Is there a reason why we need N different type attributes instead 
> > > > > > of having a single type attribute which encodes the N as an 
> > > > > > argument?
> > > > > AIUI this was a workaround for getting the value of N from an 
> > > > > AttributedType, because this only has `getAttrKind` to return the 
> > > > > attribute kind, but no way to get the corresponding argument/value. 
> > > > > This seemed like a simple way to do that without having to create a 
> > > > > new subclass for Type and having to support that in various places. 
> > > > > Is the latter the approach you were thinking of? (or is there perhaps 
> > > > > a simpler way?)
> > > > > Also, I think these are all missing let SemaHandler = 0; and let 
> > > > > ASTNode = 0;
> > > > 
> > > > Good to know. In SemaType I'm doing `CurType = 
> > > > State.getAttributedType(A, CurType, CurType);` which gives an 
> > > > `AttributedType` in the AST, should I still set `let ASTNode = 0;` in 
> > > > this case?
> > > > 
> > > > > Is there a reason why we need N different type attributes instead of 
> > > > > having a single type attribute which encodes the N as an argument?
> > > > 
> > > > As Sander mentioned, it seemed like the easiest solution, interested to 
> > > > know if there's a better approach however
> > > I was thinking specifically of creating a new `Type` subclass and 
> > > supporting it rather than adding 5 new attributes that only vary by a 
> > > bit-width (which means there's likely to be a 6th someday). It's not 
> > > immediately clear to me whether that's a really big ask for little gain 
> > > or not, though.
> > Ah, you're right, we may still need `ASTNode` to be kept around for that, 
> > good call.
> > Also, I think these are all missing let SemaHandler = 0; and let ASTNode = 
> > 0;
> 
> I've added `let SemaHandler = 0;` for the internal types and `let ASTNode = 
> 0;` for the user-facing attr.
> I was thinking specifically of creating a new Type subclass and supporting it 
> rather than adding 5 new attributes that only vary by a bit-width (which 
> means there's likely to be a 6th someday).

It would be nice if the `Attr` was accessible from the `AttributedType`, 
similar to how it is for `Decl`s, so something like:
```  if (const auto *AT = T->getAs())
if (ArmSveVectorBitsAttr *Attr = AT->getAttr())
  unsigned Width = Attr->getNumBits();```
Although I'm not sure if that makes sense or how easy it is. I do agree adding 
5 new attributes isn't ideal but for an initial implementation it's nice and 
simple. Would you be ok with us addressing this in a later patch?


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[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 278466.
c-rhodes added a comment.

Changes:

- Rebased.
- Added comments for args in calls to `ConvertTypeForMem` when 
`EnforceFixedLengthSVEAttribute` is set and documented 
`EnforceFixedLengthSVEAttribute`.
- `s/getFixedSVETypeForMemory/getFixedLengthSVETypeForMemory/`
- Documented memory representation for fixed-length predicates.


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Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/CodeGenTypes.h
  clang/test/Sema/attr-arm-sve-vector-bits-bitcast.c
  clang/test/Sema/attr-arm-sve-vector-bits-call.c
  clang/test/Sema/attr-arm-sve-vector-bits-cast.c
  clang/test/Sema/attr-arm-sve-vector-bits-codegen.c
  clang/test/Sema/attr-arm-sve-vector-bits-globals.c
  clang/test/Sema/attr-arm-sve-vector-bits-types.c

Index: clang/test/Sema/attr-arm-sve-vector-bits-types.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits-types.c
@@ -0,0 +1,525 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=128 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-128
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=256 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-256
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-512
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=1024 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-1024
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=2048 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-2048
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS_EXPERIMENTAL
+
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+//===--===//
+// Structs and unions
+//===--===//
+#define DEFINE_STRUCT(ty) \
+  struct struct_##ty {\
+fixed_##ty##_t x; \
+  } struct_##ty;
+
+#define DEFINE_UNION(ty) \
+  union union_##ty { \
+fixed_##ty##_t x;\
+  } union_##ty;
+
+DEFINE_STRUCT(int8)
+DEFINE_STRUCT(int16)
+DEFINE_STRUCT(int32)
+DEFINE_STRUCT(int64)
+DEFINE_STRUCT(uint8)
+DEFINE_STRUCT(uint16)
+DEFINE_STRUCT(uint32)
+DEFINE_STRUCT(uint64)
+DEFINE_STRUCT(float16)
+DEFINE_STRUCT(float32)
+DEFINE_STRUCT(float64)
+DEFINE_STRUCT(bfloat16)
+DEFINE_STRUCT(bool)
+
+DEFINE_UNION(int8)
+DEFINE_UNION(int16)
+DEFINE_UNION(int32)
+DEFINE_UNION(int64)
+DEFINE_UNION(uint8)
+DEFINE_UNION(uint16)
+DEFINE_UNION(uint32)
+DEFINE_UNION(uint64)
+DEFINE_UNION(float16)
+DEFINE_UNION(float32)
+DEFINE_UNION(float64)
+DEFINE_UNION(bfloat16)
+DEFINE_UNION(bool)
+
+//===--===//
+// Global variables
+//===--===//
+fixed_int8_t global_i8;
+fixed_int16_t global_i16;
+fixed_int32_t global_i32;
+fixed_int64_t global_i64;
+
+fixed_uint8_t global_u8;
+fixed_uint16_t global_u16;
+fixed_uint32_t global_u32;
+fixed_uint64_t global_u64;
+
+fixed_float16_t global_f16;
+fixed_float32_t global_f32;
+fixed_float64_t global_f64;
+
+fixed_bfloat16_t global_bf16;
+
+fixed_bool_t global_bool;
+
+//===--===//
+// Global arrays
+//===-

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked 5 inline comments as done.
c-rhodes added inline comments.



Comment at: clang/lib/CodeGen/CodeGenTypes.h:138
+  llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false,
+bool EnforceFixedLengthSVEAttribute = false);
 

efriedma wrote:
> The default for EnforceFixedLengthSVEAttribute seems backwards; I would 
> expect that almost everywhere that calls ConvertTypeForMem actually wants the 
> fixed-length type.  The scalable type only exists in registers.
> The default for EnforceFixedLengthSVEAttribute seems backwards; I would 
> expect that almost everywhere that calls ConvertTypeForMem actually wants the 
> fixed-length type. The scalable type only exists in registers.

It has no effect unless `T->isVLST()` so I think it makes sense.


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[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 278507.
c-rhodes added a comment.

Use `const auto *` and remove cast


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Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Driver/aarch64-sve-vector-bits.c
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -0,0 +1,62 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=128 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=256 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=1024 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=2048 -fallow-half-arguments-and-returns %s
+
+#define N __ARM_FEATURE_SVE_BITS_EXPERIMENTAL
+
+typedef __SVInt8_t svint8_t;
+typedef __SVInt16_t svint16_t;
+typedef __SVInt32_t svint32_t;
+typedef __SVInt64_t svint64_t;
+typedef __SVUint8_t svuint8_t;
+typedef __SVUint16_t svuint16_t;
+typedef __SVUint32_t svuint32_t;
+typedef __SVUint64_t svuint64_t;
+typedef __SVFloat16_t svfloat16_t;
+typedef __SVFloat32_t svfloat32_t;
+typedef __SVFloat64_t svfloat64_t;
+
+#if defined(__ARM_FEATURE_SVE_BF16)
+typedef __SVBFloat16_t svbfloat16_t;
+#endif
+
+typedef __SVBool_t svbool_t;
+
+// Define valid fixed-width SVE types
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+// Attribute must have a single argument
+typedef svint8_t no_argument __attribute__((arm_sve_vector_bits)); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+typedef svint8_t two_arguments __attribute__((arm_sve_vector_bits(2, 4))); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+
+// The number of SVE vector bits must be an integer constant expression
+typedef svint8_t non_int_size1 __attribute__((arm_sve_vector_bits(2.0)));   // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+typedef svint8_t non_int_size2 __attribute__((arm_sve_vector_bits("256"))); // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+
+typedef __clang_svint8x2_t svint8x2_t;
+typedef __clang_svfloat32x3_t svfloat32x3_t;
+
+// Attribute must be attached to a single SVE vector or predicate type.
+typedef void *badtype1 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'void *'}}
+typedef int badtype2 __attribute__((arm_sve_vector_bits(N)));   // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'int'}}
+typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
+typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked an inline comment as done.
c-rhodes added a comment.

In D83550#2155837 , @aaron.ballman 
wrote:

> LGTM aside from a small nit.




In D83550#2156063 , @rsandifo-arm 
wrote:

> Thanks for doing this.  FWIW, the patch LGTM from a spec point of view.  I 
> just saw one minor spelling nit.


Cheers!




Comment at: clang/include/clang/Basic/AttrDocs.td:4882
+to the SVE predicate type ``svbool_t``, this excludes tuple types such as
+``svint32x4_t``. The behaviour of the attribute is undefined unless
+``N==__ARM_FEATURE_SVE_BITS``, the implementation defined feature macro that is

rsandifo-arm wrote:
> nit: s/behaviour/behavior/, since I think the documentation uses 
> US/international English.
> nit: s/behaviour/behavior/, since I think the documentation uses 
> US/international English.

Good spot, I'll fix this before merging



Comment at: clang/lib/Sema/SemaType.cpp:7698
+llvm::APSInt &Result) {
+  Expr *AttrExpr = static_cast(Attr.getArgAsExpr(0));
+  if (AttrExpr->isTypeDependent() || AttrExpr->isValueDependent() ||

aaron.ballman wrote:
> `const auto *` and you should use `cast<>` instead of `static_cast<>`.
> const auto * and you should use cast<> instead of static_cast<>.

I've added `const auto *`, I don't think the cast was necessary since 
`Attr.getArgAsExpr` returns an `Expr *` although I noticed a few places using 
`static_cast` when calling this


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[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/Attr.td:1541
 
+def ArmSveVectorBits128 : TypeAttr {
+  let Spellings = [];

aaron.ballman wrote:
> c-rhodes wrote:
> > c-rhodes wrote:
> > > aaron.ballman wrote:
> > > > aaron.ballman wrote:
> > > > > c-rhodes wrote:
> > > > > > sdesmalen wrote:
> > > > > > > aaron.ballman wrote:
> > > > > > > > sdesmalen wrote:
> > > > > > > > > nit: Can you add a comment saying why these are undocumented 
> > > > > > > > > (and have no spellings)
> > > > > > > > Also, I think these are all missing `let SemaHandler = 0;` and 
> > > > > > > > `let ASTNode = 0;`
> > > > > > > > 
> > > > > > > > Is there a reason why we need N different type attributes 
> > > > > > > > instead of having a single type attribute which encodes the N 
> > > > > > > > as an argument? I think this may simplify the patch somewhat as 
> > > > > > > > you no longer need to switch over N as much.
> > > > > > > > Is there a reason why we need N different type attributes 
> > > > > > > > instead of having a single type attribute which encodes the N 
> > > > > > > > as an argument?
> > > > > > > AIUI this was a workaround for getting the value of N from an 
> > > > > > > AttributedType, because this only has `getAttrKind` to return the 
> > > > > > > attribute kind, but no way to get the corresponding 
> > > > > > > argument/value. This seemed like a simple way to do that without 
> > > > > > > having to create a new subclass for Type and having to support 
> > > > > > > that in various places. Is the latter the approach you were 
> > > > > > > thinking of? (or is there perhaps a simpler way?)
> > > > > > > Also, I think these are all missing let SemaHandler = 0; and let 
> > > > > > > ASTNode = 0;
> > > > > > 
> > > > > > Good to know. In SemaType I'm doing `CurType = 
> > > > > > State.getAttributedType(A, CurType, CurType);` which gives an 
> > > > > > `AttributedType` in the AST, should I still set `let ASTNode = 0;` 
> > > > > > in this case?
> > > > > > 
> > > > > > > Is there a reason why we need N different type attributes instead 
> > > > > > > of having a single type attribute which encodes the N as an 
> > > > > > > argument?
> > > > > > 
> > > > > > As Sander mentioned, it seemed like the easiest solution, 
> > > > > > interested to know if there's a better approach however
> > > > > I was thinking specifically of creating a new `Type` subclass and 
> > > > > supporting it rather than adding 5 new attributes that only vary by a 
> > > > > bit-width (which means there's likely to be a 6th someday). It's not 
> > > > > immediately clear to me whether that's a really big ask for little 
> > > > > gain or not, though.
> > > > Ah, you're right, we may still need `ASTNode` to be kept around for 
> > > > that, good call.
> > > > Also, I think these are all missing let SemaHandler = 0; and let 
> > > > ASTNode = 0;
> > > 
> > > I've added `let SemaHandler = 0;` for the internal types and `let ASTNode 
> > > = 0;` for the user-facing attr.
> > > I was thinking specifically of creating a new Type subclass and 
> > > supporting it rather than adding 5 new attributes that only vary by a 
> > > bit-width (which means there's likely to be a 6th someday).
> > 
> > It would be nice if the `Attr` was accessible from the `AttributedType`, 
> > similar to how it is for `Decl`s, so something like:
> > ```  if (const auto *AT = T->getAs())
> > if (ArmSveVectorBitsAttr *Attr = AT->getAttr())
> >   unsigned Width = Attr->getNumBits();```
> > Although I'm not sure if that makes sense or how easy it is. I do agree 
> > adding 5 new attributes isn't ideal but for an initial implementation it's 
> > nice and simple. Would you be ok with us addressing this in a later patch?
> > It would be nice if the Attr was accessible from the AttributedType, 
> > similar to how it is for Decls, so something like:
> 
> You can do that through an `AttributedTypeLoc` object, which I think should 
> be available from the situations you need to check this through a 
> `TypeSourceInfo *` for the type. Then you can use 
> `AttributedTypeLoc::getAttr()` to get the semantic attribute.
> 
> > Would you be ok with us addressing this in a later patch?
> 
> No and yes. It's a novel design to have a user-facing attribute that is never 
> hooked up in the AST but is instead used to decide which spellingless 
> attribute to use instead, so I'd strongly prefer to find a solution that 
> doesn't use this approach. I also think we'll wind up with cleaner code from 
> this. That said, if it turns out to be awkward to do because there's too much 
> code required to support it, then I can likely hold my nose.
> You can do that through an AttributedTypeLoc object, which I think should be 
> available from the situations you need to check this through a TypeSourceInfo 
> * for the type. Then you can use AttributedTypeLoc::getAttr() to get the 
> semantic attribute.

I've tried your suggestion w

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
c-rhodes marked an inline comment as done.
Closed by commit rGbb160e769dbe: [Sema][AArch64] Add parsing support for 
arm_sve_vector_bits attribute (authored by c-rhodes).

Changed prior to commit:
  https://reviews.llvm.org/D83550?vs=278507&id=278702#toc

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Driver/aarch64-sve-vector-bits.c
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -0,0 +1,62 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=128 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=256 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=1024 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=2048 -fallow-half-arguments-and-returns %s
+
+#define N __ARM_FEATURE_SVE_BITS_EXPERIMENTAL
+
+typedef __SVInt8_t svint8_t;
+typedef __SVInt16_t svint16_t;
+typedef __SVInt32_t svint32_t;
+typedef __SVInt64_t svint64_t;
+typedef __SVUint8_t svuint8_t;
+typedef __SVUint16_t svuint16_t;
+typedef __SVUint32_t svuint32_t;
+typedef __SVUint64_t svuint64_t;
+typedef __SVFloat16_t svfloat16_t;
+typedef __SVFloat32_t svfloat32_t;
+typedef __SVFloat64_t svfloat64_t;
+
+#if defined(__ARM_FEATURE_SVE_BF16)
+typedef __SVBFloat16_t svbfloat16_t;
+#endif
+
+typedef __SVBool_t svbool_t;
+
+// Define valid fixed-width SVE types
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+// Attribute must have a single argument
+typedef svint8_t no_argument __attribute__((arm_sve_vector_bits)); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+typedef svint8_t two_arguments __attribute__((arm_sve_vector_bits(2, 4))); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+
+// The number of SVE vector bits must be an integer constant expression
+typedef svint8_t non_int_size1 __attribute__((arm_sve_vector_bits(2.0)));   // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+typedef svint8_t non_int_size2 __attribute__((arm_sve_vector_bits("256"))); // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+
+typedef __clang_svint8x2_t svint8x2_t;
+typedef __clang_svfloat32x3_t svfloat32x3_t;
+
+// Attribute must be attached to a single SVE vector or predicate type.
+typedef void *badtype1 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'void *'}}
+typedef int badtype2 __attribute__((arm_sve_vector_bits(N)));   // expected-error {{'arm_sve_vector_bits' attribu

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/Attr.td:1541
 
+def ArmSveVectorBits128 : TypeAttr {
+  let Spellings = [];

aaron.ballman wrote:
> c-rhodes wrote:
> > aaron.ballman wrote:
> > > c-rhodes wrote:
> > > > c-rhodes wrote:
> > > > > aaron.ballman wrote:
> > > > > > aaron.ballman wrote:
> > > > > > > c-rhodes wrote:
> > > > > > > > sdesmalen wrote:
> > > > > > > > > aaron.ballman wrote:
> > > > > > > > > > sdesmalen wrote:
> > > > > > > > > > > nit: Can you add a comment saying why these are 
> > > > > > > > > > > undocumented (and have no spellings)
> > > > > > > > > > Also, I think these are all missing `let SemaHandler = 0;` 
> > > > > > > > > > and `let ASTNode = 0;`
> > > > > > > > > > 
> > > > > > > > > > Is there a reason why we need N different type attributes 
> > > > > > > > > > instead of having a single type attribute which encodes the 
> > > > > > > > > > N as an argument? I think this may simplify the patch 
> > > > > > > > > > somewhat as you no longer need to switch over N as much.
> > > > > > > > > > Is there a reason why we need N different type attributes 
> > > > > > > > > > instead of having a single type attribute which encodes the 
> > > > > > > > > > N as an argument?
> > > > > > > > > AIUI this was a workaround for getting the value of N from an 
> > > > > > > > > AttributedType, because this only has `getAttrKind` to return 
> > > > > > > > > the attribute kind, but no way to get the corresponding 
> > > > > > > > > argument/value. This seemed like a simple way to do that 
> > > > > > > > > without having to create a new subclass for Type and having 
> > > > > > > > > to support that in various places. Is the latter the approach 
> > > > > > > > > you were thinking of? (or is there perhaps a simpler way?)
> > > > > > > > > Also, I think these are all missing let SemaHandler = 0; and 
> > > > > > > > > let ASTNode = 0;
> > > > > > > > 
> > > > > > > > Good to know. In SemaType I'm doing `CurType = 
> > > > > > > > State.getAttributedType(A, CurType, CurType);` which gives an 
> > > > > > > > `AttributedType` in the AST, should I still set `let ASTNode = 
> > > > > > > > 0;` in this case?
> > > > > > > > 
> > > > > > > > > Is there a reason why we need N different type attributes 
> > > > > > > > > instead of having a single type attribute which encodes the N 
> > > > > > > > > as an argument?
> > > > > > > > 
> > > > > > > > As Sander mentioned, it seemed like the easiest solution, 
> > > > > > > > interested to know if there's a better approach however
> > > > > > > I was thinking specifically of creating a new `Type` subclass and 
> > > > > > > supporting it rather than adding 5 new attributes that only vary 
> > > > > > > by a bit-width (which means there's likely to be a 6th someday). 
> > > > > > > It's not immediately clear to me whether that's a really big ask 
> > > > > > > for little gain or not, though.
> > > > > > Ah, you're right, we may still need `ASTNode` to be kept around for 
> > > > > > that, good call.
> > > > > > Also, I think these are all missing let SemaHandler = 0; and let 
> > > > > > ASTNode = 0;
> > > > > 
> > > > > I've added `let SemaHandler = 0;` for the internal types and `let 
> > > > > ASTNode = 0;` for the user-facing attr.
> > > > > I was thinking specifically of creating a new Type subclass and 
> > > > > supporting it rather than adding 5 new attributes that only vary by a 
> > > > > bit-width (which means there's likely to be a 6th someday).
> > > > 
> > > > It would be nice if the `Attr` was accessible from the 
> > > > `AttributedType`, similar to how it is for `Decl`s, so something like:
> > > > ```  if (const auto *AT = T->getAs())
> > > > if (ArmSveVectorBitsAttr *Attr = AT->getAttr())
> > > >   unsigned Width = Attr->getNumBits();```
> > > > Although I'm not sure if that makes sense or how easy it is. I do agree 
> > > > adding 5 new attributes isn't ideal but for an initial implementation 
> > > > it's nice and simple. Would you be ok with us addressing this in a 
> > > > later patch?
> > > > It would be nice if the Attr was accessible from the AttributedType, 
> > > > similar to how it is for Decls, so something like:
> > > 
> > > You can do that through an `AttributedTypeLoc` object, which I think 
> > > should be available from the situations you need to check this through a 
> > > `TypeSourceInfo *` for the type. Then you can use 
> > > `AttributedTypeLoc::getAttr()` to get the semantic attribute.
> > > 
> > > > Would you be ok with us addressing this in a later patch?
> > > 
> > > No and yes. It's a novel design to have a user-facing attribute that is 
> > > never hooked up in the AST but is instead used to decide which 
> > > spellingless attribute to use instead, so I'd strongly prefer to find a 
> > > solution that doesn't use this approach. I also think we'll wind up with 
> > > cleaner code from this. That said, if it turns out to be awkward to do 
> > 

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 279178.
c-rhodes added a comment.

Changes:

- Remove internal type attributes (defined for each vector-size).
- Get the vector size from the `arm_sve_vector_bits` attribute via the 
`AttributedTypeLoc` associated with the typedef decl.
- Change `NumBits` argument for `ArmSveVectorBits` type attribute from int to 
unsigned.
- Only allow `ArmSveVectorBits` type attribute to be applied to typedefs (and 
added test).
- Set `let PragmaAttributeSupport = 0;` after specifying `Subjects` to fixed 
`clang/test/Misc/pragma-attribute-supported-attributes-list.test`.
- `vector-length sized` -> `vector-length-sized`.


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Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/Type.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -60,3 +60,168 @@
 typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
 typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(N)));// expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svint8x2_t' (aka '__clang_svint8x2_t')}}
 typedef svfloat32x3_t badtype5 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svfloat32x3_t' (aka '__clang_svfloat32x3_t')}}
+
+// Attribute only applies to typedefs.
+svint8_t non_typedef_type __attribute__((arm_sve_vector_bits(N)));  // expected-error {{'arm_sve_vector_bits' attribute only applies to typedefs}}
+
+// Test that we can define non-local fixed-length SVE types (unsupported for
+// sizeless types).
+fixed_int8_t global_int8;
+fixed_bfloat16_t global_bfloat16;
+fixed_bool_t global_bool;
+
+extern fixed_int8_t extern_int8;
+extern fixed_bfloat16_t extern_bfloat16;
+extern fixed_bool_t extern_bool;
+
+static fixed_int8_t static_int8;
+static fixed_bfloat16_t static_bfloat16;
+static fixed_bool_t static_bool;
+
+fixed_int8_t *global_int8_ptr;
+extern fixed_int8_t *extern_int8_ptr;
+static fixed_int8_t *static_int8_ptr;
+__thread fixed_int8_t thread_int8;
+
+typedef fixed_int8_t int8_typedef;
+typedef fixed_int8_t *int8_ptr_typedef;
+
+// Test sized expressions
+int sizeof_int8 = sizeof(global_int8);
+int sizeof_int8_var = sizeof(*global_int8_ptr);
+int sizeof_int8_var_ptr = sizeof(global_int8_ptr);
+
+extern fixed_int8_t *extern_int8_ptr;
+
+int alignof_int8 = __alignof__(extern_int8);
+int alignof_int8_var = __alignof__(*extern_int8_ptr);
+int alignof_int8_var_ptr = __alignof__(extern_int8_ptr);
+
+void f(int c) {
+  fixed_int8_t fs8;
+  svint8_t ss8;
+
+  void *sel __attribute__((unused));
+  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types ('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
+  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types ('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}
+}
+
+// --//
+// Sizeof
+
+#define VECTOR_SIZE ((N / 8))
+#define PRED_SIZE ((N / 64))
+
+_Static_assert(sizeof(fixed_int8_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_int16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_uint8_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_float16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bfloat16_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bool_t) == PRED_SIZE, "");
+
+// --//
+// Alignof
+
+#define VECTOR_ALIGN 16
+#define PRED_ALIGN 2
+
+_Static_assert(__alignof__(fixed_int8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_uint8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint32_t) == VECTOR_ALIGN, "");
+_Static_assert(__a

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked an inline comment as done.
c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/Attr.td:1541
 
+def ArmSveVectorBits128 : TypeAttr {
+  let Spellings = [];

c-rhodes wrote:
> aaron.ballman wrote:
> > c-rhodes wrote:
> > > aaron.ballman wrote:
> > > > c-rhodes wrote:
> > > > > c-rhodes wrote:
> > > > > > aaron.ballman wrote:
> > > > > > > aaron.ballman wrote:
> > > > > > > > c-rhodes wrote:
> > > > > > > > > sdesmalen wrote:
> > > > > > > > > > aaron.ballman wrote:
> > > > > > > > > > > sdesmalen wrote:
> > > > > > > > > > > > nit: Can you add a comment saying why these are 
> > > > > > > > > > > > undocumented (and have no spellings)
> > > > > > > > > > > Also, I think these are all missing `let SemaHandler = 
> > > > > > > > > > > 0;` and `let ASTNode = 0;`
> > > > > > > > > > > 
> > > > > > > > > > > Is there a reason why we need N different type attributes 
> > > > > > > > > > > instead of having a single type attribute which encodes 
> > > > > > > > > > > the N as an argument? I think this may simplify the patch 
> > > > > > > > > > > somewhat as you no longer need to switch over N as much.
> > > > > > > > > > > Is there a reason why we need N different type attributes 
> > > > > > > > > > > instead of having a single type attribute which encodes 
> > > > > > > > > > > the N as an argument?
> > > > > > > > > > AIUI this was a workaround for getting the value of N from 
> > > > > > > > > > an AttributedType, because this only has `getAttrKind` to 
> > > > > > > > > > return the attribute kind, but no way to get the 
> > > > > > > > > > corresponding argument/value. This seemed like a simple way 
> > > > > > > > > > to do that without having to create a new subclass for Type 
> > > > > > > > > > and having to support that in various places. Is the latter 
> > > > > > > > > > the approach you were thinking of? (or is there perhaps a 
> > > > > > > > > > simpler way?)
> > > > > > > > > > Also, I think these are all missing let SemaHandler = 0; 
> > > > > > > > > > and let ASTNode = 0;
> > > > > > > > > 
> > > > > > > > > Good to know. In SemaType I'm doing `CurType = 
> > > > > > > > > State.getAttributedType(A, CurType, CurType);` which gives an 
> > > > > > > > > `AttributedType` in the AST, should I still set `let ASTNode 
> > > > > > > > > = 0;` in this case?
> > > > > > > > > 
> > > > > > > > > > Is there a reason why we need N different type attributes 
> > > > > > > > > > instead of having a single type attribute which encodes the 
> > > > > > > > > > N as an argument?
> > > > > > > > > 
> > > > > > > > > As Sander mentioned, it seemed like the easiest solution, 
> > > > > > > > > interested to know if there's a better approach however
> > > > > > > > I was thinking specifically of creating a new `Type` subclass 
> > > > > > > > and supporting it rather than adding 5 new attributes that only 
> > > > > > > > vary by a bit-width (which means there's likely to be a 6th 
> > > > > > > > someday). It's not immediately clear to me whether that's a 
> > > > > > > > really big ask for little gain or not, though.
> > > > > > > Ah, you're right, we may still need `ASTNode` to be kept around 
> > > > > > > for that, good call.
> > > > > > > Also, I think these are all missing let SemaHandler = 0; and let 
> > > > > > > ASTNode = 0;
> > > > > > 
> > > > > > I've added `let SemaHandler = 0;` for the internal types and `let 
> > > > > > ASTNode = 0;` for the user-facing attr.
> > > > > > I was thinking specifically of creating a new Type subclass and 
> > > > > > supporting it rather than adding 5 new attributes that only vary by 
> > > > > > a bit-width (which means there's likely to be a 6th someday).
> > > > > 
> > > > > It would be nice if the `Attr` was accessible from the 
> > > > > `AttributedType`, similar to how it is for `Decl`s, so something like:
> > > > > ```  if (const auto *AT = T->getAs())
> > > > > if (ArmSveVectorBitsAttr *Attr = AT->getAttr())
> > > > >   unsigned Width = Attr->getNumBits();```
> > > > > Although I'm not sure if that makes sense or how easy it is. I do 
> > > > > agree adding 5 new attributes isn't ideal but for an initial 
> > > > > implementation it's nice and simple. Would you be ok with us 
> > > > > addressing this in a later patch?
> > > > > It would be nice if the Attr was accessible from the AttributedType, 
> > > > > similar to how it is for Decls, so something like:
> > > > 
> > > > You can do that through an `AttributedTypeLoc` object, which I think 
> > > > should be available from the situations you need to check this through 
> > > > a `TypeSourceInfo *` for the type. Then you can use 
> > > > `AttributedTypeLoc::getAttr()` to get the semantic attribute.
> > > > 
> > > > > Would you be ok with us addressing this in a later patch?
> > > > 
> > > > No and yes. It's a novel design to have a user-facing attribute that is 
> > > > never hooked up in the AST but is instead used to decide which 

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 279265.
c-rhodes added a comment.

Change the default for `EnforceFixedLengthSVEAttribute`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83553/new/

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Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/CodeGenTypes.h
  clang/test/Sema/attr-arm-sve-vector-bits-bitcast.c
  clang/test/Sema/attr-arm-sve-vector-bits-call.c
  clang/test/Sema/attr-arm-sve-vector-bits-cast.c
  clang/test/Sema/attr-arm-sve-vector-bits-codegen.c
  clang/test/Sema/attr-arm-sve-vector-bits-globals.c
  clang/test/Sema/attr-arm-sve-vector-bits-types.c

Index: clang/test/Sema/attr-arm-sve-vector-bits-types.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits-types.c
@@ -0,0 +1,525 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=128 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-128
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=256 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-256
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-512
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=1024 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-1024
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -msve-vector-bits=2048 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-2048
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS_EXPERIMENTAL
+
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+//===--===//
+// Structs and unions
+//===--===//
+#define DEFINE_STRUCT(ty) \
+  struct struct_##ty {\
+fixed_##ty##_t x; \
+  } struct_##ty;
+
+#define DEFINE_UNION(ty) \
+  union union_##ty { \
+fixed_##ty##_t x;\
+  } union_##ty;
+
+DEFINE_STRUCT(int8)
+DEFINE_STRUCT(int16)
+DEFINE_STRUCT(int32)
+DEFINE_STRUCT(int64)
+DEFINE_STRUCT(uint8)
+DEFINE_STRUCT(uint16)
+DEFINE_STRUCT(uint32)
+DEFINE_STRUCT(uint64)
+DEFINE_STRUCT(float16)
+DEFINE_STRUCT(float32)
+DEFINE_STRUCT(float64)
+DEFINE_STRUCT(bfloat16)
+DEFINE_STRUCT(bool)
+
+DEFINE_UNION(int8)
+DEFINE_UNION(int16)
+DEFINE_UNION(int32)
+DEFINE_UNION(int64)
+DEFINE_UNION(uint8)
+DEFINE_UNION(uint16)
+DEFINE_UNION(uint32)
+DEFINE_UNION(uint64)
+DEFINE_UNION(float16)
+DEFINE_UNION(float32)
+DEFINE_UNION(float64)
+DEFINE_UNION(bfloat16)
+DEFINE_UNION(bool)
+
+//===--===//
+// Global variables
+//===--===//
+fixed_int8_t global_i8;
+fixed_int16_t global_i16;
+fixed_int32_t global_i32;
+fixed_int64_t global_i64;
+
+fixed_uint8_t global_u8;
+fixed_uint16_t global_u16;
+fixed_uint32_t global_u32;
+fixed_uint64_t global_u64;
+
+fixed_float16_t global_f16;
+fixed_float32_t global_f32;
+fixed_float64_t global_f64;
+
+fixed_bfloat16_t global_bf16;
+
+fixed_bool_t global_bool;
+
+//===--===//
+// Global arrays
+//===--===//
+fixed_int8_t global_arr_i8[3];
+fixed_int16_t global_arr_i16[3];
+fixed_int32_t global_arr_i32[3];
+fixed_int64_t global_arr_i64[3];
+
+f

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked an inline comment as done.
c-rhodes added inline comments.



Comment at: clang/lib/CodeGen/CodeGenTypes.h:138
+  llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false,
+bool EnforceFixedLengthSVEAttribute = false);
 

efriedma wrote:
> c-rhodes wrote:
> > efriedma wrote:
> > > The default for EnforceFixedLengthSVEAttribute seems backwards; I would 
> > > expect that almost everywhere that calls ConvertTypeForMem actually wants 
> > > the fixed-length type.  The scalable type only exists in registers.
> > > The default for EnforceFixedLengthSVEAttribute seems backwards; I would 
> > > expect that almost everywhere that calls ConvertTypeForMem actually wants 
> > > the fixed-length type. The scalable type only exists in registers.
> > 
> > It has no effect unless `T->isVLST()` so I think it makes sense.
> My question is "why is the current default for EnforceFixedLengthSVEAttribute 
> correct?" You answer for that is "because VLST types are rare"?  I'm not sure 
> how that's related.
> 
> Essentially, the issue is that ConvertTypeForMem means "I'm allocating 
> something in memory; what is its type?".  Except for a few places where we've 
> specifically added handling to make it work, the code assumes scalable types 
> don't exist.  So in most places, we want the fixed version.  With the current 
> default, I'm afraid we're going to end up with weird failures with various 
> constructs you haven't tested.
> 
> I guess if there's some large number of places where the current default is 
> actually beneficial, the current patch wouldn't make it obvious, but my 
> intuition is that are few places like that.
>> My question is "why is the current default for 
>> EnforceFixedLengthSVEAttribute correct?" You answer for that is "because 
>> VLST types are rare"? I'm not sure how that's related.

>Essentially, the issue is that ConvertTypeForMem means "I'm allocating 
>something in memory; what is its type?". Except for a few places where we've 
>specifically added handling to make it work, the code assumes scalable types 
>don't exist. So in most places, we want the fixed version. With the current 
>default, I'm afraid we're going to end up with weird failures with various 
>constructs you haven't tested.

Sorry I misunderstood what you meant. I think you're right that does make 
sense, I guess the benefit of defaulting to false is (hopefully) those failures 
would have come to our attention and we could explicitly add test cases for 
those, although I suspect the same applies with your suggestion with the added 
benefit of us supporting constructs we haven't explicitly tested as you say. 
Anyhow, I've made the change, cheers!


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[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/lib/AST/ASTContext.cpp:1887
+
+unsigned getSvePredWidth(const Type *T) { return getSveVectorWidth(T) / 8; }
+

aaron.ballman wrote:
> Should this be dividing by the number of bits in a char for the target as 
> opposed to hard-coding to 8?
> Should this be dividing by the number of bits in a char for the target as 
> opposed to hard-coding to 8?

Predicate registers in SVE hold one bit per byte of a vector register so each 
predicate is 1/8th the size of a vector which are defined in bits, it has to be 
8 and I know `getCharWidth` returns 8 for the target this is implemented for 
but I dont know what it would mean for any other target or if we care about 
that?


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[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 279455.
c-rhodes added a comment.

- Make helpers static in ASTContext.
- Use `getCharWidth`.
- `s/vector-length-sized/vector-length-specific`.


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Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/Type.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -60,3 +60,168 @@
 typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
 typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(N)));// expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svint8x2_t' (aka '__clang_svint8x2_t')}}
 typedef svfloat32x3_t badtype5 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svfloat32x3_t' (aka '__clang_svfloat32x3_t')}}
+
+// Attribute only applies to typedefs.
+svint8_t non_typedef_type __attribute__((arm_sve_vector_bits(N)));  // expected-error {{'arm_sve_vector_bits' attribute only applies to typedefs}}
+
+// Test that we can define non-local fixed-length SVE types (unsupported for
+// sizeless types).
+fixed_int8_t global_int8;
+fixed_bfloat16_t global_bfloat16;
+fixed_bool_t global_bool;
+
+extern fixed_int8_t extern_int8;
+extern fixed_bfloat16_t extern_bfloat16;
+extern fixed_bool_t extern_bool;
+
+static fixed_int8_t static_int8;
+static fixed_bfloat16_t static_bfloat16;
+static fixed_bool_t static_bool;
+
+fixed_int8_t *global_int8_ptr;
+extern fixed_int8_t *extern_int8_ptr;
+static fixed_int8_t *static_int8_ptr;
+__thread fixed_int8_t thread_int8;
+
+typedef fixed_int8_t int8_typedef;
+typedef fixed_int8_t *int8_ptr_typedef;
+
+// Test sized expressions
+int sizeof_int8 = sizeof(global_int8);
+int sizeof_int8_var = sizeof(*global_int8_ptr);
+int sizeof_int8_var_ptr = sizeof(global_int8_ptr);
+
+extern fixed_int8_t *extern_int8_ptr;
+
+int alignof_int8 = __alignof__(extern_int8);
+int alignof_int8_var = __alignof__(*extern_int8_ptr);
+int alignof_int8_var_ptr = __alignof__(extern_int8_ptr);
+
+void f(int c) {
+  fixed_int8_t fs8;
+  svint8_t ss8;
+
+  void *sel __attribute__((unused));
+  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types ('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
+  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types ('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}
+}
+
+// --//
+// Sizeof
+
+#define VECTOR_SIZE ((N / 8))
+#define PRED_SIZE ((N / 64))
+
+_Static_assert(sizeof(fixed_int8_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_int16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_uint8_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_float16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bfloat16_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bool_t) == PRED_SIZE, "");
+
+// --//
+// Alignof
+
+#define VECTOR_ALIGN 16
+#define PRED_ALIGN 2
+
+_Static_assert(__alignof__(fixed_int8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_uint8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_float16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_float32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_float64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_bfloat16_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_bool_t) == PRED_ALIGN, "");
+
+// --//
+/

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

In D83551#2164984 , @aaron.ballman 
wrote:

> The attribute bits LGTM, thanks!


Thanks for reviewing!


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[Differential] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was not accepted when it landed; it landed in state "Needs 
Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rG89e61e782b73: [Sema][AArch64] Add semantics for 
arm_sve_vector_bits attribute (authored by c-rhodes).

Changed prior to commit:
  https://reviews.llvm.org/D83551?vs=278430&id=279097#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83551/new/

https://reviews.llvm.org/D83551

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/Type.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -60,3 +60,168 @@
 typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
 typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(N)));// expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svint8x2_t' (aka '__clang_svint8x2_t')}}
 typedef svfloat32x3_t badtype5 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svfloat32x3_t' (aka '__clang_svfloat32x3_t')}}
+
+// Attribute only applies to typedefs.
+svint8_t non_typedef_type __attribute__((arm_sve_vector_bits(N)));  // expected-error {{'arm_sve_vector_bits' attribute only applies to typedefs}}
+
+// Test that we can define non-local fixed-length SVE types (unsupported for
+// sizeless types).
+fixed_int8_t global_int8;
+fixed_bfloat16_t global_bfloat16;
+fixed_bool_t global_bool;
+
+extern fixed_int8_t extern_int8;
+extern fixed_bfloat16_t extern_bfloat16;
+extern fixed_bool_t extern_bool;
+
+static fixed_int8_t static_int8;
+static fixed_bfloat16_t static_bfloat16;
+static fixed_bool_t static_bool;
+
+fixed_int8_t *global_int8_ptr;
+extern fixed_int8_t *extern_int8_ptr;
+static fixed_int8_t *static_int8_ptr;
+__thread fixed_int8_t thread_int8;
+
+typedef fixed_int8_t int8_typedef;
+typedef fixed_int8_t *int8_ptr_typedef;
+
+// Test sized expressions
+int sizeof_int8 = sizeof(global_int8);
+int sizeof_int8_var = sizeof(*global_int8_ptr);
+int sizeof_int8_var_ptr = sizeof(global_int8_ptr);
+
+extern fixed_int8_t *extern_int8_ptr;
+
+int alignof_int8 = __alignof__(extern_int8);
+int alignof_int8_var = __alignof__(*extern_int8_ptr);
+int alignof_int8_var_ptr = __alignof__(extern_int8_ptr);
+
+void f(int c) {
+  fixed_int8_t fs8;
+  svint8_t ss8;
+
+  void *sel __attribute__((unused));
+  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types ('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
+  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types ('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}
+}
+
+// --//
+// Sizeof
+
+#define VECTOR_SIZE ((N / 8))
+#define PRED_SIZE ((N / 64))
+
+_Static_assert(sizeof(fixed_int8_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_int16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_uint8_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_float16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bfloat16_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bool_t) == PRED_SIZE, "");
+
+// --//
+// Alignof
+
+#define VECTOR_ALIGN 16
+#define PRED_ALIGN 2
+
+_Static_assert(__alignof__(fixed_int8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_uint8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_float16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_float32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_float64_t) == VECTOR_ALIGN, "");
+

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG89e61e782b73: [Sema][AArch64] Add semantics for 
arm_sve_vector_bits attribute (authored by c-rhodes).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83551/new/

https://reviews.llvm.org/D83551

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/Type.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -60,3 +60,168 @@
 typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
 typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(N)));// expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svint8x2_t' (aka '__clang_svint8x2_t')}}
 typedef svfloat32x3_t badtype5 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svfloat32x3_t' (aka '__clang_svfloat32x3_t')}}
+
+// Attribute only applies to typedefs.
+svint8_t non_typedef_type __attribute__((arm_sve_vector_bits(N)));  // expected-error {{'arm_sve_vector_bits' attribute only applies to typedefs}}
+
+// Test that we can define non-local fixed-length SVE types (unsupported for
+// sizeless types).
+fixed_int8_t global_int8;
+fixed_bfloat16_t global_bfloat16;
+fixed_bool_t global_bool;
+
+extern fixed_int8_t extern_int8;
+extern fixed_bfloat16_t extern_bfloat16;
+extern fixed_bool_t extern_bool;
+
+static fixed_int8_t static_int8;
+static fixed_bfloat16_t static_bfloat16;
+static fixed_bool_t static_bool;
+
+fixed_int8_t *global_int8_ptr;
+extern fixed_int8_t *extern_int8_ptr;
+static fixed_int8_t *static_int8_ptr;
+__thread fixed_int8_t thread_int8;
+
+typedef fixed_int8_t int8_typedef;
+typedef fixed_int8_t *int8_ptr_typedef;
+
+// Test sized expressions
+int sizeof_int8 = sizeof(global_int8);
+int sizeof_int8_var = sizeof(*global_int8_ptr);
+int sizeof_int8_var_ptr = sizeof(global_int8_ptr);
+
+extern fixed_int8_t *extern_int8_ptr;
+
+int alignof_int8 = __alignof__(extern_int8);
+int alignof_int8_var = __alignof__(*extern_int8_ptr);
+int alignof_int8_var_ptr = __alignof__(extern_int8_ptr);
+
+void f(int c) {
+  fixed_int8_t fs8;
+  svint8_t ss8;
+
+  void *sel __attribute__((unused));
+  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types ('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
+  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types ('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}
+}
+
+// --//
+// Sizeof
+
+#define VECTOR_SIZE ((N / 8))
+#define PRED_SIZE ((N / 64))
+
+_Static_assert(sizeof(fixed_int8_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_int16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_uint8_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_float16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_float64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bfloat16_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_bool_t) == PRED_SIZE, "");
+
+// --//
+// Alignof
+
+#define VECTOR_ALIGN 16
+#define PRED_ALIGN 2
+
+_Static_assert(__alignof__(fixed_int8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_int64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_uint8_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_uint64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_float16_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_float32_t) == VECTOR_ALIGN, "");
+_Static_assert(__alignof__(fixed_float64_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_bfloat16_t) == VECTOR_ALIGN, "");
+
+_Static_assert(__alignof__(fixed_bool_t) == PRED_ALIGN, "");
+
+// 

[PATCH] D82582: [SVE] Remove calls to VectorType::getNumElements from clang

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:5612-5613
 
   llvm::VectorType *VTy = GetNeonType(this, Type, HasLegalHalfType, false,
   AllowBFloatArgsAndRet);
   llvm::Type *Ty = VTy;

Is there a reason you can't do a single cast here?


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[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked an inline comment as done.
c-rhodes added inline comments.



Comment at: clang/lib/CodeGen/CGExpr.cpp:152
+  Align, Name,
+  /*ArraySize=*/nullptr, Alloca);
 

efriedma wrote:
> Do we need to bitcast the result of CreateTempAlloca to a pointer to the 
> array type?  I'm concerned that we might miss a bitcast if the source code 
> uses the address of the variable.
> Do we need to bitcast the result of CreateTempAlloca to a pointer to the 
> array type? I'm concerned that we might miss a bitcast if the source code 
> uses the address of the variable.

You were right, I've spent some time investigating this. The current 
implementation crashes on:
```fixed_int32_t global;
fixed_int32_t address_of_global() {
  fixed_int32_t *global_ptr;
  global_ptr = &global;
  return *global_ptr;
}```

the reason being `global` is represented as an `ArrayType` whereas the pointer 
`global_ptr` is scalable:

```@global = global [4 x i32] zeroinitializer, align 16
%global_ptr = alloca *, align 8```

so when storing the address of `global` to `global_ptr` the store it tries to 
create causes a crash:

`store [4 x i32]* @global, ** %global_ptr, align 8`

I tried your suggestion to bitcast to alloca to the array type in 
`CreateMemTemp` but found for that example it isn't called, it's created by a 
call to `CreateTempAlloca` in CGDecl.cpp (`EmitAutoVarAlloca`). 
`CreateTempAlloca` takes an `llvm::Type *Ty` so it's not as straightforward as 
doing a bitcast there, although I found it could be done in `EmitAutoVarAlloca` 
but it means having to handle this is two places I'm aware of and potentially 
others I haven't hit. In this case as well it also required looking through the 
pointer to see if the pointee was a VLST then doing a bitcast.

I've also experimented with representing allocas as fixed-length arrays to see 
if that will make it any easier and it does simplify the patch a little. It 
does require handling `PointerType` in `ConvertTypeForMem` however as we do for 
`ConstantArray`, same issue I mentioned in response to your other comment about 
removing that.

I planning to update the patch with that implementation but I've just found 
another issue:

```fixed_int32_t arr[3];
fixed_int32_t *z() {
  fixed_int32_t *array_ptr;
  array_ptr = &arr[0];
  return array_ptr;
}```

trying to create a store:
`store [4 x i32]* %0, ** %retval, align 8`

although this is done in CGStmt.cpp as it's for a retval so it looks like a 
bitcast could also be required there.



Comment at: clang/lib/CodeGen/CodeGenModule.cpp:3985
+else
+  Init = EmitNullConstant(D->getType());
   } else {

efriedma wrote:
> EmitNullConstant should just do the right thing, I think, now that we've 
> changed the default behavior of ConvertTypeForMem.
> EmitNullConstant should just do the right thing, I think, now that we've 
> changed the default behavior of ConvertTypeForMem.

Good spot, these changes can be removed



Comment at: clang/lib/CodeGen/CodeGenTypes.cpp:151
+  return llvm::ArrayType::get(*MemTy, A->getSize().getZExtValue());
+  }
+

efriedma wrote:
> I think the default handling for constant arrays should do the right thing, 
> now that we've changed the default behavior of ConvertTypeForMem.
> I think the default handling for constant arrays should do the right thing, 
> now that we've changed the default behavior of ConvertTypeForMem.

`ConvertType` looks at the canonical type so the type attribute is lost.


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[PATCH] D82582: [SVE] Remove calls to VectorType::getNumElements from clang

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

there's a few places the `getNumElements` calls can be fixed by getting the 
initial cast right




Comment at: clang/lib/CodeGen/CGBuiltin.cpp:5986
   case NEON::BI__builtin_neon_vqrdmulh_lane_v: {
 auto *RTy = cast(Ty);
 if (BuiltinID == NEON::BI__builtin_neon_vqdmulhq_lane_v ||

cast here



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:9872
   case NEON::BI__builtin_neon_vfma_laneq_v: {
 llvm::VectorType *VTy = cast(Ty);
 // v1f64 fma should be mapped to Neon scalar f64 fma

cast here



Comment at: clang/lib/CodeGen/CGExpr.cpp:1765
   }
   auto *VectorTy = dyn_cast(
   cast(Addr.getPointer()->getType())->getElementType());

cast here



Comment at: clang/lib/CodeGen/CGExpr.cpp:1799
   llvm::Type *SrcTy = Value->getType();
   auto *VecTy = dyn_cast(SrcTy);
   // Handle vec3 special.

cast here



Comment at: clang/lib/CodeGen/CGExpr.cpp:2214
   if (const VectorType *VTy = Dst.getType()->getAs()) {
 unsigned NumSrcElts = VTy->getNumElements();
 unsigned NumDstElts =

missed one here



Comment at: clang/lib/CodeGen/CGExprScalar.cpp:1638
 
 llvm::VectorType *MTy = cast(Mask->getType());
 

cast here



Comment at: clang/lib/CodeGen/SwiftCallingConv.cpp:321
   // If we have a vector type, split it.
   if (auto vecTy = dyn_cast_or_null(type)) {
 auto eltTy = vecTy->getElementType();

cast here


Repository:
  rG LLVM Github Monorepo

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[PATCH] D81462: [SveEmitter] Add builtins for svtbl2

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes accepted this revision.
c-rhodes added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rG LLVM Github Monorepo

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[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, rsandifo-arm, efriedma, ctetreau, 
cameron.mcinally.
Herald added subscribers: danielkiss, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: aaron.ballman.
Herald added a project: clang.

This patch implements parsing support for the 'arm_sve_vector_bits' type
attribute, defined by the Arm C Language Extensions (ACLE, version 00bet5,
section 3.7.3) for SVE [1].

The purpose of this attribute is to define fixed-length (VLST) versions
of existing sizeless types (VLAT). For example:

  #if __ARM_FEATURE_SVE_BITS==512
  typedef svint32_t fixed_svint32_t __attribute__((arm_sve_vector_bits(512)));
  #endif

Creates a type 'fixed_svint32_t' that is a fixed-length version of
'svint32_t' that is normal-sized (rather than sizeless) and contains
exactly 512 bits. Unlike 'svint32_t', this type can be used in places
such as structs and arrays where sizeless types can't.

Implemented in this patch is the following:

- Defined and tested attribute taking single argument.
- Checks the argument is an integer constant expression.
- Attribute can only be attached to a single SVE vector or predicate type, 
excluding tuple types such as svint32x4_t.
- Validates N == __ARM_FEATURE_SVE_BITS, where N is the number of bits passed 
to the attribute.
- Basic validation of the __ARM_FEATURE_SVE_BITS macro.

The __ARM_FEATURE_SVE_BITS macro will be enabled by the
-msve-vector-bits= flag in the final patch of the series.

[1] https://developer.arm.com/documentation/100987/latest


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83550

Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/arm-feature-sve-bits-macro.c
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -0,0 +1,43 @@
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=128 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=256 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=1024 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=2048 -fallow-half-arguments-and-returns %s
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+
+// Define valid fixed-width SVE types
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+// Attribute must have a single argument
+typedef svint8_t no_argument __attribute__((arm_sve_vector_bits)); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+typedef svint8_t two_arguments __attribute__((arm_sve_vector_bits(2, 4))); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+
+// The number of SVE vector bits must be an integer constant expression
+typedef svint8_t non_int_size1 __attribute__((arm_sve_vector_bits(2.0)));   // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+typedef svint8_t non_int_size2 __attribute__((arm_sve_vector_bits("256"))); // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+
+// Attribute must be attached to a single SVE vector or predicate type.
+typedef void *badtype1 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' att

[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, rsandifo-arm, efriedma, cameron.mcinally, 
ctetreau.
Herald added subscribers: danielkiss, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: aaron.ballman.
Herald added a project: clang.

This patch implements semantics for the 'arm_sve_vector_bits' type
attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1].
The purpose of this attribute is to define fixed-length (VLST) versions
of existing sizeless types (VLAT).

Implemented in this patch is the the behaviour described in section 3.7.3.2
and minimal parts of sections 3.7.3.3 and 3.7.3.4, this includes:

- Defining VLST globals, structs, unions, and local variables
- Implicit casting between VLAT <=> VLST.
- Diagnosis of ill-formed conditional expressions of the form:

  C ?  E1 : E2

  where E1 is a VLAT type and E2 is a VLST, or vice-versa. This avoids any 
ambiguity about the nature of the result type (i.e is it sized or sizeless).
- For vectors:
  - sizeof(VLST) == N/8
  - alignof(VLST) == 16
- For predicates:
  - sizeof(VLST) == N/64
  - alignof(VLST) == 2

VLSTs have the same representation as VLATs in the AST but are wrapped
with a TypeAttribute. Scalable types are currently emitted in the IR for
uses such as globals and structs which don't support these types, this
is addressed in the next patch with codegen, where VLSTs are lowered to
sized arrays for globals, structs / unions and arrays.

Not implemented in this patch is the behaviour guarded by the feature
macros:

- __ARM_FEATURE_SVE_VECTOR_OPERATORS
- __ARM_FEATURE_SVE_PREDICATE_OPERATORS

As such, the GNU __attribute__((vector_size)) extension is not available
and operators such as binary '+' are not supported for VLSTs. Support
for this is intended to be addressed by later patches.

[1] https://developer.arm.com/documentation/100987/latest


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83551

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -41,3 +41,194 @@
 typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
 typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svint8x2_t' (aka '__clang_svint8x2_t')}}
 typedef svfloat32x3_t badtype5 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svfloat32x3_t' (aka '__clang_svfloat32x3_t')}}
+
+fixed_int8_t global_int8;
+fixed_bfloat16_t global_bfloat16;
+fixed_bool_t global_bool;
+
+extern fixed_int8_t extern_int8;
+extern fixed_bfloat16_t extern_bfloat16;
+extern fixed_bool_t extern_bool;
+
+static fixed_int8_t static_int8;
+static fixed_bfloat16_t static_bfloat16;
+static fixed_bool_t static_bool;
+
+fixed_int8_t* global_int8_ptr;
+extern fixed_int8_t* extern_int8_ptr;
+static fixed_int8_t* static_int8_ptr;
+__thread fixed_int8_t thread_int8;
+
+typedef fixed_int8_t int8_typedef;
+typedef fixed_int8_t *int8_ptr_typedef;
+
+int sizeof_int8 = sizeof(global_int8);
+int sizeof_int8_var = sizeof(*global_int8_ptr);
+int sizeof_int8_var_ptr = sizeof(global_int8_ptr);
+
+extern fixed_int8_t *extern_int8_ptr;
+
+int alignof_int8 = __alignof__(extern_int8);
+int alignof_int8_var = __alignof__(*extern_int8_ptr);
+int alignof_int8_var_ptr = __alignof__(extern_int8_ptr);
+
+void f(bool c) {
+  fixed_int8_t fs8;
+  svint8_t ss8;
+
+  void *sel __attribute__((unused));
+  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types ('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
+  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types ('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}
+}
+
+// --//
+// Sizeof
+
+#define VECTOR_SIZE ((N / 8))
+#define PRED_SIZE ((N / 64))
+
+_Static_assert(sizeof(fixed_int8_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_int16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_int64_t) == VECTOR_SIZE, "");
+
+_Static_assert(sizeof(fixed_uint8_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint16_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint32_t) == VECTOR_SIZE, "");
+_Static_assert(sizeof(fixed_uint64_t) == VECTOR_SIZE, ""

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, rsandifo-arm, efriedma, cameron.mcinally, 
ctetreau.
Herald added subscribers: danielkiss, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: clang.

This patch implements codegen for the 'arm_sve_vector_bits' type
attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1].
The purpose of this attribute is to define fixed-length (VLST) versions
of existing sizeless types (VLAT).

Implemented in this patch is the lowering of VLSTs to valid types.
VLSTs (unlike VLATs) can be used in globals, members of structs
and unions, and arrays. To support this in this patch we lower VLSTs to
arrays. For example, in the following C code:

  #if __ARM_FEATURE_SVE_BITS==512
  typedef svint32_t fixed_svint32_t __attribute__((arm_sve_vector_bits(512)));
  struct struct_int32 {
fixed_int32_t x;
  } struct_int32;
  #endif

the struct is lowered to:

  %struct.struct_int32 = type { [16 x i32] }

where the member 'x' is a fixed-length variant of 'svint32_t' that
contains exactly 512 bits.

When loading from a VLST to a VLAT, or when storing a VLAT to a VLST,
the address is bitcasted, e.g.

  bitcast [N x i8]* %addr.ptr to *

[1] https://developer.arm.com/documentation/100987/latest


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D83553

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/CodeGenTypes.h
  clang/test/Sema/attr-arm-sve-vector-bits-bitcast.c
  clang/test/Sema/attr-arm-sve-vector-bits-call.c
  clang/test/Sema/attr-arm-sve-vector-bits-cast.c
  clang/test/Sema/attr-arm-sve-vector-bits-codegen.c
  clang/test/Sema/attr-arm-sve-vector-bits-globals.c
  clang/test/Sema/attr-arm-sve-vector-bits-types.c

Index: clang/test/Sema/attr-arm-sve-vector-bits-types.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits-types.c
@@ -0,0 +1,525 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=128 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-128
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=256 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-256
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-512
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=1024 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-1024
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=2048 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-2048
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+//===--===//
+// Structs and unions
+//===--===//
+#define DEFINE_STRUCT(ty) \
+  struct struct_##ty {\
+fixed_##ty##_t x; \
+  } struct_##ty;
+
+#define DEFINE_UNION(ty) \
+  union union_##ty { \
+fixed_##ty##_t x;\
+  } union_##ty;
+
+DEFINE_STRUCT(int8)
+DEFINE_STRUCT(int16)
+DEFINE_STRUCT(int32)
+DEFINE_STRUCT(int64)
+DEFINE_STRUCT(uint8)
+DEFINE_STRUCT(uint16)
+DEFINE_STRUCT(uint32)
+DEFINE_STRUCT(uint64)
+DEFINE_STRUCT(float16)
+DEFINE_STRUCT(float32)
+DEFINE_STRUCT(float64)
+DEFINE_STRUCT(bfloat16)
+DEFINE_STRUCT(bool)
+
+DEFINE_UNION(int8)
+DEFINE_UNIO

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 277043.
c-rhodes added a comment.

Changes:

- Use fixed-length instead of fixed-width in naming.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83553/new/

https://reviews.llvm.org/D83553

Files:
  clang/lib/CodeGen/CGExpr.cpp
  clang/lib/CodeGen/CGRecordLayoutBuilder.cpp
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/CodeGenTypes.cpp
  clang/lib/CodeGen/CodeGenTypes.h
  clang/test/Sema/attr-arm-sve-vector-bits-bitcast.c
  clang/test/Sema/attr-arm-sve-vector-bits-call.c
  clang/test/Sema/attr-arm-sve-vector-bits-cast.c
  clang/test/Sema/attr-arm-sve-vector-bits-codegen.c
  clang/test/Sema/attr-arm-sve-vector-bits-globals.c
  clang/test/Sema/attr-arm-sve-vector-bits-types.c

Index: clang/test/Sema/attr-arm-sve-vector-bits-types.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits-types.c
@@ -0,0 +1,525 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=128 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-128
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=256 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-256
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=512 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-512
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=1024 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-1024
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -D__ARM_FEATURE_SVE_BITS=2048 -fallow-half-arguments-and-returns -S -emit-llvm -o - %s | FileCheck %s --check-prefix=CHECK-2048
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+//===--===//
+// Structs and unions
+//===--===//
+#define DEFINE_STRUCT(ty) \
+  struct struct_##ty {\
+fixed_##ty##_t x; \
+  } struct_##ty;
+
+#define DEFINE_UNION(ty) \
+  union union_##ty { \
+fixed_##ty##_t x;\
+  } union_##ty;
+
+DEFINE_STRUCT(int8)
+DEFINE_STRUCT(int16)
+DEFINE_STRUCT(int32)
+DEFINE_STRUCT(int64)
+DEFINE_STRUCT(uint8)
+DEFINE_STRUCT(uint16)
+DEFINE_STRUCT(uint32)
+DEFINE_STRUCT(uint64)
+DEFINE_STRUCT(float16)
+DEFINE_STRUCT(float32)
+DEFINE_STRUCT(float64)
+DEFINE_STRUCT(bfloat16)
+DEFINE_STRUCT(bool)
+
+DEFINE_UNION(int8)
+DEFINE_UNION(int16)
+DEFINE_UNION(int32)
+DEFINE_UNION(int64)
+DEFINE_UNION(uint8)
+DEFINE_UNION(uint16)
+DEFINE_UNION(uint32)
+DEFINE_UNION(uint64)
+DEFINE_UNION(float16)
+DEFINE_UNION(float32)
+DEFINE_UNION(float64)
+DEFINE_UNION(bfloat16)
+DEFINE_UNION(bool)
+
+//===--===//
+// Global variables
+//===--===//
+fixed_int8_t global_i8;
+fixed_int16_t global_i16;
+fixed_int32_t global_i32;
+fixed_int64_t global_i64;
+
+fixed_uint8_t global_u8;
+fixed_uint16_t global_u16;
+fixed_uint32_t global_u32;
+fixed_uint64_t global_u64;
+
+fixed_float16_t global_f16;
+fixed_float32_t global_f32;
+fixed_float64_t global_f64;
+
+fixed_bfloat16_t global_bf16;
+
+fixed_bool_t global_bool;
+
+//===--===//
+// Global arrays
+//===--===//
+fixed_int8_t global_arr_i8[3];
+fixed_int16_t global_arr_i16[3];
+fixed_int32_t global_arr_i32[3];
+fixed_int64_t global_arr_i64[3];
+
+fixed

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 277853.
c-rhodes added a comment.

Address @sdesmalen comments


CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/arm-feature-sve-bits-macro.c
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -0,0 +1,43 @@
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=128 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=256 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=1024 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=2048 -fallow-half-arguments-and-returns %s
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+
+// Define valid fixed-width SVE types
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+// Attribute must have a single argument
+typedef svint8_t no_argument __attribute__((arm_sve_vector_bits)); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+typedef svint8_t two_arguments __attribute__((arm_sve_vector_bits(2, 4))); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+
+// The number of SVE vector bits must be an integer constant expression
+typedef svint8_t non_int_size1 __attribute__((arm_sve_vector_bits(2.0)));   // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+typedef svint8_t non_int_size2 __attribute__((arm_sve_vector_bits("256"))); // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+
+// Attribute must be attached to a single SVE vector or predicate type.
+typedef void *badtype1 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'void *'}}
+typedef int badtype2 __attribute__((arm_sve_vector_bits(N)));   // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'int'}}
+typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
+typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svint8x2_t' (aka '__clang_svint8x2_t')}}
+typedef svfloat32x3_t badtype5 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svfloat32x3_t' (aka '__clang_svfloat32x3_t')}}
Index: clang/test/Sema/arm-feature-sve-bits-macro.c
===
--- /dev/null
+++ clang/test/Sema/arm-feature-sve-bits-macro.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=512 -fallow-half-arguments-and-returns %s
+
+#include 
+
+#define N 512
+
+// __ARM_FEATURE_SVE_BITS macro must be defined for attribute to have any effect
+#undef __ARM_FEATURE_SVE_BITS
+typedef svint8_t macro_undefined __attribute__((arm_sve_vector_bits(N))); // expected-error {{__ARM_FEATURE_SVE_BITS is not defined}}
+
+// __ARM_FEATURE_SVE_BITS macro must have a single argument
+#define __ARM_FEATURE_SVE_BITS
+

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked 6 inline comments as done.
c-rhodes added inline comments.



Comment at: clang/lib/Sema/SemaType.cpp:7784
+  // The __ARM_FEATURE_SVE_BITS macro must be defined when using this 
attribute.
+  auto &PP = S.getPreprocessor();
+  if (!PP.isMacroDefined("__ARM_FEATURE_SVE_BITS")) {

sdesmalen wrote:
> I think that the code that checks if the value of the attribute matches the 
> value set by -msve-vector-bits should be part of Sema, not the parser. Also 
> I'm tempted to suggest decoupling the value of the macro from the code that 
> checks the attribute-value matches -msve-vector-bits.
> 
> If the arm_sve.h header file defines a constant value like this:
> ```#if defined(__ARM_SVE_FEATURE_BITS)
> const unsigned __arm_sve_feature_bits = __ARM_SVE_FEATURE_BITS
> #endif```
> You can check for the availability and value of this constant in the AST 
> during semantic analysis. That way, if for whatever reason the value of the 
> macro is redefined, the compiler can issue a diagnostic. Ideally we would 
> insert a `__arm_sve_feature_bits` constant into the compilation unit directly 
> when -msve-vector-bits is passed, but I don't know Clang enough to suggest 
> where or at which point to add that.
> I think that the code that checks if the value of the attribute matches the 
> value set by -msve-vector-bits should be part of Sema, not the parser.
This code which is checking `N==__ARM_FEATURE_SVE_BITS` is in Sema, maybe 
there's a more suitable place I'm not aware of but I think it makes sense to 
check this when looking at the type attribute.

> That way, if for whatever reason the value of the macro is redefined, the 
> compiler can issue a diagnostic. 
I'm not convinced having a constant in the header fixes that, I suspect the 
user could redefine that constant as they could the macro, e.g.:
```void f() {
  const unsigned __arm_sve_feature_bits = 512;
}```

Ideally we want to diagnose inconsistent vector-lengths since we don't support 
it,  but for the time being maybe we can be explicit about what we do support 
and encourage users to use the `-msve-vector-bits` flag.





Comment at: clang/lib/Sema/SemaType.cpp:7818
+  unsigned VecSize = static_cast(SveVectorSizeInBits.getZExtValue());
+  if (ArmSveFeatureBits->getValue() != VecSize) {
+S.Diag(Attr.getLoc(), diag::err_attribute_bad_sve_vector_size) << VecSize;

sdesmalen wrote:
> `ArmSveFeatureBits` can be `nullptr`. Or it shouldn't use `dyn_cast`.
I've added a check + diagnostic if it's a nullptr



Comment at: clang/test/Sema/arm-feature-sve-bits-macro.c:1
+// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -fsyntax-only -verify 
-D__ARM_FEATURE_SVE_BITS=512 -D__ARM_FEATURE_SVE 
-fallow-half-arguments-and-returns %s
+

sdesmalen wrote:
> nit: `-D__ARM_FEATURE_SVE` is no longer necessary.
Missed that one, cheers!


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[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 278009.
c-rhodes marked 2 inline comments as done and an inline comment as not done.
c-rhodes added a comment.

Address @aaron.ballman comments


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Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/arm-feature-sve-bits-macro.c
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -0,0 +1,44 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=128 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=256 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=1024 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=2048 -fallow-half-arguments-and-returns %s
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS
+
+// Define valid fixed-width SVE types
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+// Attribute must have a single argument
+typedef svint8_t no_argument __attribute__((arm_sve_vector_bits)); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+typedef svint8_t two_arguments __attribute__((arm_sve_vector_bits(2, 4))); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+
+// The number of SVE vector bits must be an integer constant expression
+typedef svint8_t non_int_size1 __attribute__((arm_sve_vector_bits(2.0)));   // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+typedef svint8_t non_int_size2 __attribute__((arm_sve_vector_bits("256"))); // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+
+// Attribute must be attached to a single SVE vector or predicate type.
+typedef void *badtype1 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'void *'}}
+typedef int badtype2 __attribute__((arm_sve_vector_bits(N)));   // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'int'}}
+typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
+typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svint8x2_t' (aka '__clang_svint8x2_t')}}
+typedef svfloat32x3_t badtype5 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'svfloat32x3_t' (aka '__clang_svfloat32x3_t')}}
Index: clang/test/Sema/arm-feature-sve-bits-macro.c
===
--- /dev/null
+++ clang/test/Sema/arm-feature-sve-bits-macro.c
@@ -0,0 +1,29 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -fsyntax-only -verify -D__ARM_FEATURE_SVE_BITS=512 -fallow-half-arguments-and-returns %s
+
+#include 
+
+#define N 512
+
+// __ARM_FEATURE_SVE_BITS macro must be defined for 

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked 6 inline comments as done.
c-rhodes added a comment.

@aaron.ballman thanks for comments! I've updated the patch




Comment at: clang/include/clang/Basic/Attr.td:1538
+  let Args = [IntArgument<"NumBits">];
+  let Documentation = [Undocumented];
+}

aaron.ballman wrote:
> No new, undocumented attributes, please.
I've added some docs



Comment at: clang/test/Sema/arm-feature-sve-bits-macro.c:3
+
+#include 
+

aaron.ballman wrote:
> This should not be using a system include (unless you control the include 
> path from the RUN line so this doesn't depend on the system running the test).
Good spot, I missed `// REQUIRES: aarch64-registered-target` which we use in 
the other ACLE tests.



Comment at: clang/test/Sema/arm-feature-sve-bits-macro.c:4
+#include 
+
+#define N 512

aaron.ballman wrote:
> You should have a test that the attribute works at this location due to the 
> macro being defined on the command line.
I think that's covered by `clang/test/Sema/attr-arm-sve-vector-bits.c`



Comment at: clang/test/Sema/arm-feature-sve-bits-macro.c:22
+// SVE vector bits must equal __ARM_FEATURE_SVE_BITS
+#define __ARM_FEATURE_SVE_BITS 512
+typedef svint8_t badsize __attribute__((arm_sve_vector_bits(256))); // 
expected-error {{inconsistent SVE vector size '256', must match 
__ARM_FEATURE_SVE_BITS feature macro set by -msve-vector-bits}}

aaron.ballman wrote:
> I'd also appreciate test cases like:
> ```
> #define __ARM_FEATURE_SVE_BITS(x)  512
> #define __ARM_FEATURE_SVE_BITS N
> ```
> 
> #define __ARM_FEATURE_SVE_BITS N
Good point, I've added a test for this which I think covers the 
`isValueDependent` check.

> #define __ARM_FEATURE_SVE_BITS(x)  512
I did try this but no diagnostic is emitted, were you thinking this would cover 
`isTypeDependent`? To be honest I copied that from `HandleNeonVectorTypeAttr` 
and I'm not sure if it's necessary or what a test would look like for it. The 
tests for `neon_vector_type` only cover non-ICE "2.0".



Comment at: clang/test/Sema/attr-arm-sve-vector-bits.c:7
+
+#include 
+

aaron.ballman wrote:
> Same issue here as above.
As above, I've added `// REQUIRES: aarch64-registered-target`


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[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/lib/Sema/SemaType.cpp:7784
+  // The __ARM_FEATURE_SVE_BITS macro must be defined when using this 
attribute.
+  auto &PP = S.getPreprocessor();
+  if (!PP.isMacroDefined("__ARM_FEATURE_SVE_BITS")) {

sdesmalen wrote:
> efriedma wrote:
> > c-rhodes wrote:
> > > sdesmalen wrote:
> > > > I think that the code that checks if the value of the attribute matches 
> > > > the value set by -msve-vector-bits should be part of Sema, not the 
> > > > parser. Also I'm tempted to suggest decoupling the value of the macro 
> > > > from the code that checks the attribute-value matches -msve-vector-bits.
> > > > 
> > > > If the arm_sve.h header file defines a constant value like this:
> > > > ```#if defined(__ARM_SVE_FEATURE_BITS)
> > > > const unsigned __arm_sve_feature_bits = __ARM_SVE_FEATURE_BITS
> > > > #endif```
> > > > You can check for the availability and value of this constant in the 
> > > > AST during semantic analysis. That way, if for whatever reason the 
> > > > value of the macro is redefined, the compiler can issue a diagnostic. 
> > > > Ideally we would insert a `__arm_sve_feature_bits` constant into the 
> > > > compilation unit directly when -msve-vector-bits is passed, but I don't 
> > > > know Clang enough to suggest where or at which point to add that.
> > > > I think that the code that checks if the value of the attribute matches 
> > > > the value set by -msve-vector-bits should be part of Sema, not the 
> > > > parser.
> > > This code which is checking `N==__ARM_FEATURE_SVE_BITS` is in Sema, maybe 
> > > there's a more suitable place I'm not aware of but I think it makes sense 
> > > to check this when looking at the type attribute.
> > > 
> > > > That way, if for whatever reason the value of the macro is redefined, 
> > > > the compiler can issue a diagnostic. 
> > > I'm not convinced having a constant in the header fixes that, I suspect 
> > > the user could redefine that constant as they could the macro, e.g.:
> > > ```void f() {
> > >   const unsigned __arm_sve_feature_bits = 512;
> > > }```
> > > 
> > > Ideally we want to diagnose inconsistent vector-lengths since we don't 
> > > support it,  but for the time being maybe we can be explicit about what 
> > > we do support and encourage users to use the `-msve-vector-bits` flag.
> > > 
> > > 
> > I don't think it makes sense to try to parse the value of the 
> > __ARM_FEATURE_SVE_BITS out of the macro.  The macro should be defined by 
> > the compiler itself, so we should have the value stored somewhere else.
> > This code which is checking N==__ARM_FEATURE_SVE_BITS is in Sema, maybe 
> > there's a more suitable place I'm not aware of but I think it makes sense 
> > to check this when looking at the type attribute.
> You're right, I mistook this Sema function for parsing function, my bad.
> 
> > I'm not convinced having a constant in the header fixes that, I suspect the 
> > user could redefine that constant as they could the macro, e.g.:
> > ```void f() {
> >   const unsigned __arm_sve_feature_bits = 512;
> > }```
> You can probably search for the value of `__arm_sve_feature_bits` at a global 
> scope rather than the current scope. It could also be an internal state 
> variable in Clang. As long as we don't have to rely on the value of the macro 
> while we're parsing the file. I'm personally not too bothered if you want to 
> do this in a separate patch while you're still implementing the feature, or 
> if you want to update this patch, but it needs to get fixed because parsing 
> the macro is the wrong way around.
> 
> > Ideally we want to diagnose inconsistent vector-lengths since we don't 
> > support it, but for the time being maybe we can be explicit about what we 
> > do support and encourage users to use the -msve-vector-bits flag.
> When this feature is implemented, the `-msve-vector-bits` driver flag is the 
> only interface to set the vector-length, any other way would be invalid.
> I don't think it makes sense to try to parse the value of the 
> __ARM_FEATURE_SVE_BITS out of the macro. The macro should be defined by the 
> compiler itself, so we should have the value stored somewhere else.

I intend to set the macro in the patch adding `-msve-vector-bits`, maybe that 
flag could set some internal state variable in clang as Sander suggests. I'll 
look into it.


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[PATCH] D83551: [PATCH 2/4][Sema][AArch64] Add semantics for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/Attr.td:1541
 
+def ArmSveVectorBits128 : TypeAttr {
+  let Spellings = [];

sdesmalen wrote:
> aaron.ballman wrote:
> > sdesmalen wrote:
> > > nit: Can you add a comment saying why these are undocumented (and have no 
> > > spellings)
> > Also, I think these are all missing `let SemaHandler = 0;` and `let ASTNode 
> > = 0;`
> > 
> > Is there a reason why we need N different type attributes instead of having 
> > a single type attribute which encodes the N as an argument? I think this 
> > may simplify the patch somewhat as you no longer need to switch over N as 
> > much.
> > Is there a reason why we need N different type attributes instead of having 
> > a single type attribute which encodes the N as an argument?
> AIUI this was a workaround for getting the value of N from an AttributedType, 
> because this only has `getAttrKind` to return the attribute kind, but no way 
> to get the corresponding argument/value. This seemed like a simple way to do 
> that without having to create a new subclass for Type and having to support 
> that in various places. Is the latter the approach you were thinking of? (or 
> is there perhaps a simpler way?)
> Also, I think these are all missing let SemaHandler = 0; and let ASTNode = 0;

Good to know. In SemaType I'm doing `CurType = State.getAttributedType(A, 
CurType, CurType);` which gives an `AttributedType` in the AST, should I still 
set `let ASTNode = 0;` in this case?

> Is there a reason why we need N different type attributes instead of having a 
> single type attribute which encodes the N as an argument?

As Sander mentioned, it seemed like the easiest solution, interested to know if 
there's a better approach however


Repository:
  rG LLVM Github Monorepo

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[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 278218.
c-rhodes edited the summary of this revision.
c-rhodes added a comment.
Herald added a subscriber: dang.

Added `-msve-vector-bits=` flag. If specified the 
`__ARM_FEATURE_SVE_BITS__EXPERIMENTAL` macro is defined and a language option 
`ArmSveVectorBits` is set. The language option replaces the macro parsing in 
SemaType for the attributed type and the macro tests have been removed. Now 
that the `-msve-vector-bits` flag is implemented in this patch, the final patch 
in the series is intended to make the feature macro non-experimental.


CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D83550

Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Driver/aarch64-sve-vector-bits.c
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -0,0 +1,44 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=128 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=256 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=1024 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=2048 -fallow-half-arguments-and-returns %s
+
+#include 
+
+#define N __ARM_FEATURE_SVE_BITS__EXPERIMENTAL
+
+// Define valid fixed-width SVE types
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+// Attribute must have a single argument
+typedef svint8_t no_argument __attribute__((arm_sve_vector_bits)); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+typedef svint8_t two_arguments __attribute__((arm_sve_vector_bits(2, 4))); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+
+// The number of SVE vector bits must be an integer constant expression
+typedef svint8_t non_int_size1 __attribute__((arm_sve_vector_bits(2.0)));   // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+typedef svint8_t non_int_size2 __attribute__((arm_sve_vector_bits("256"))); // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+
+// Attribute must be attached to a single SVE vector or predicate type.
+typedef void *badtype1 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'void *'}}
+typedef int badtype2 __attribute__((arm_sve_vector_bits(N)));   // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'int'}}
+typedef float badtype3 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'float'}}
+typedef svint8x2_t badtype4 __attribute__((arm_sve_vector_bits(N)));// expected-error {{'arm_sve_vec

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 278249.
c-rhodes added a comment.

- Add a note to docs explaining this feature is a WIP.
- `s/__ARM_FEATURE_SVE_BITS__EXPERIMENTAL/__ARM_FEATURE_SVE_BITS_EXPERIMENTAL`.
- `s/validIntegerConstantExpr/verifyValidIntegerConstantExpr`.
- Removed unrelated change.
- Removed `// REQUIRES: aarch64-registered-target` and `#include ` 
from test. Sizeless ACLE types are typedef'd in the test, copied from header.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83550/new/

https://reviews.llvm.org/D83550

Files:
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/DiagnosticDriverKinds.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Basic/LangOptions.def
  clang/include/clang/Driver/Options.td
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Driver/ToolChains/Arch/AArch64.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Frontend/CompilerInvocation.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Driver/aarch64-sve-vector-bits.c
  clang/test/Preprocessor/aarch64-target-features.c
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- /dev/null
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -0,0 +1,62 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=128 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=256 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=1024 -fallow-half-arguments-and-returns %s
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -msve-vector-bits=2048 -fallow-half-arguments-and-returns %s
+
+#define N __ARM_FEATURE_SVE_BITS_EXPERIMENTAL
+
+typedef __SVInt8_t svint8_t;
+typedef __SVInt16_t svint16_t;
+typedef __SVInt32_t svint32_t;
+typedef __SVInt64_t svint64_t;
+typedef __SVUint8_t svuint8_t;
+typedef __SVUint16_t svuint16_t;
+typedef __SVUint32_t svuint32_t;
+typedef __SVUint64_t svuint64_t;
+typedef __SVFloat16_t svfloat16_t;
+typedef __SVFloat32_t svfloat32_t;
+typedef __SVFloat64_t svfloat64_t;
+
+#if defined(__ARM_FEATURE_SVE_BF16)
+typedef __SVBFloat16_t svbfloat16_t;
+#endif
+
+typedef __SVBool_t svbool_t;
+
+// Define valid fixed-width SVE types
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint16_t fixed_int16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svint64_t fixed_int64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svuint8_t fixed_uint8_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint16_t fixed_uint16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint32_t fixed_uint32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svuint64_t fixed_uint64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svfloat16_t fixed_float16_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat32_t fixed_float32_t __attribute__((arm_sve_vector_bits(N)));
+typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbfloat16_t fixed_bfloat16_t __attribute__((arm_sve_vector_bits(N)));
+
+typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
+
+// Attribute must have a single argument
+typedef svint8_t no_argument __attribute__((arm_sve_vector_bits)); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+typedef svint8_t two_arguments __attribute__((arm_sve_vector_bits(2, 4))); // expected-error {{'arm_sve_vector_bits' attribute takes one argument}}
+
+// The number of SVE vector bits must be an integer constant expression
+typedef svint8_t non_int_size1 __attribute__((arm_sve_vector_bits(2.0)));   // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+typedef svint8_t non_int_size2 __attribute__((arm_sve_vector_bits("256"))); // expected-error {{'arm_sve_vector_bits' attribute requires an integer constant}}
+
+typedef __clang_svint8x2_t svint8x2_t;
+typedef __clang_svfloat32x3_t svfloat32x3_t;
+
+// Attribute must be attached to a single SVE vector or predicate type.
+typedef void *badtype1 __attribute__((arm_sve_vector_bits(N))); // expected-error {{'arm_sve_vector_bits' attribute applied to non-SVE type 'void *'}}
+typedef int badtype2 __attribute__((arm_sv

[PATCH] D83550: [PATCH 1/4][Sema][AArch64] Add parsing support for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked 6 inline comments as done.
c-rhodes added inline comments.



Comment at: clang/test/Sema/arm-feature-sve-bits-macro.c:3
+
+#include 
+

aaron.ballman wrote:
> c-rhodes wrote:
> > aaron.ballman wrote:
> > > This should not be using a system include (unless you control the include 
> > > path from the RUN line so this doesn't depend on the system running the 
> > > test).
> > Good spot, I missed `// REQUIRES: aarch64-registered-target` which we use 
> > in the other ACLE tests.
> That makes me uncomfortable as this means you won't get any testing on 
> platforms that may have odd behaviors, like Windows when in MS compatibility 
> mode. I'm not keen on adding attributes that can only be tested under certain 
> circumstances as we want to ensure behavior on all platforms.
> 
> We typically handle this by requiring the test to replicate the system header 
> in an Inputs folder that then gets set on the RUN line so that the test can 
> be reproduced on any platform. Was that approach considered and rejected for 
> some reason?
> That makes me uncomfortable as this means you won't get any testing on 
> platforms that may have odd behaviors, like Windows when in MS compatibility 
> mode. I'm not keen on adding attributes that can only be tested under certain 
> circumstances as we want to ensure behavior on all platforms.

I've removed `// REQUIRES: aarch64-registered-target` and the include, it's 
sufficient to typedef the types we need from the header.

> We typically handle this by requiring the test to replicate the system header 
> in an Inputs folder that then gets set on the RUN line so that the test can 
> be reproduced on any platform. Was that approach considered and rejected for 
> some reason?

I wasn't aware of this, good to know! That might come in handy in the next 
patch actually as I use a function from the ACLE to test calls with 
fixed-length types.


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[PATCH] D82178: [AArch64][SVE] Guard svbfloat16_t with feature macro in ACLE

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, efriedma, stuij, fpetrogalli.
Herald added subscribers: cfe-commits, danielkiss, psnobl, rkruppe, 
kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: clang.
sdesmalen added inline comments.



Comment at: clang/utils/TableGen/SveEmitter.cpp:1091
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
+  OS << "typedef __SVBFloat16_t svbfloat16_t;\n";
+  OS << "#endif\n\n";

Can you also add an error if `__ARM_FEATURE_SVE_BF16` is defined, but 
`__ARM_FEATURE_BF16_SCALAR_ARITHMETIC` isn't?
something like:
```#ifndef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC
#error "__ARM_FEATURE_BF16_SCALAR_ARITHMETIC must be defined when 
__ARM_FEATURE_SVE_BF16 is defined"
#endif
```


`svbfloat16_t` should only be defined if the `__ARM_FEATURE_SVE_BF16`
feature macro is enabled, similar to the scalar `bfloat16_t` type. Patch
also contains a fix for ld1ro intrinsic which should be guarded on
`__ARM_FEATURE_SVE_BF16` rather than `__ARM_FEATURE_BF16_SCALAR_ARITHMETIC`.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82178

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
  clang/utils/TableGen/SveEmitter.cpp


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1085,8 +1085,11 @@
   OS << "typedef __SVUint16_t svuint16_t;\n";
   OS << "typedef __SVUint32_t svuint32_t;\n";
   OS << "typedef __SVUint64_t svuint64_t;\n";
-  OS << "typedef __SVFloat16_t svfloat16_t;\n";
-  OS << "typedef __SVBFloat16_t svbfloat16_t;\n\n";
+  OS << "typedef __SVFloat16_t svfloat16_t;\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
+  OS << "typedef __SVBFloat16_t svbfloat16_t;\n";
+  OS << "#endif\n\n";
 
   OS << "#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC\n";
   OS << "typedef __bf16 bfloat16_t;\n";
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
 
 #include 
 
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -484,8 +484,8 @@
 let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64)" in {
   def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, 
"aarch64_sve_ld1ro">;
 }
-let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64) && 
defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)" in {
-  def SVLD1RO_BF : SInst<"svld1ro[_{2}]", "dPc", "b", MergeNone, 
"aarch64_sve_ld1ro">;
+let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64) && 
defined(__ARM_FEATURE_SVE_BF16)" in {
+  def SVLD1RO_BF16 : SInst<"svld1ro[_{2}]", "dPc", "b", MergeNone, 
"aarch64_sve_ld1ro">;
 }
 

 // Stores


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1085,8 +1085,11 @@
   OS << "typedef __SVUint16_t svuint16_t;\n";
   OS << "typedef __SVUint32_t svuint32_t;\n";
   OS << "typedef __SVUint64_t svuint64_t;\n";
-  OS << "typedef __SVFloat16_t svfloat16_t;\n";
-  OS << "typedef __SVBFloat16_t svbfloat16_t;\n\n";
+  OS << "typedef __SVFloat16_t svfloat16_t;\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_SVE_BF1

[PATCH] D82178: [AArch64][SVE] Guard svbfloat16_t with feature macro in ACLE

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 272043.
c-rhodes added a comment.

Changes:

- Error if `__ARM_FEATURE_BF16_SCALAR_ARITHMETIC` not defined when defining 
`__ARM_FEATURE_SVE_BF16`.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82178/new/

https://reviews.llvm.org/D82178

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
  clang/utils/TableGen/SveEmitter.cpp


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1085,8 +1085,15 @@
   OS << "typedef __SVUint16_t svuint16_t;\n";
   OS << "typedef __SVUint32_t svuint32_t;\n";
   OS << "typedef __SVUint64_t svuint64_t;\n";
-  OS << "typedef __SVFloat16_t svfloat16_t;\n";
-  OS << "typedef __SVBFloat16_t svbfloat16_t;\n\n";
+  OS << "typedef __SVFloat16_t svfloat16_t;\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
+  OS << "#if !defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)\n";
+  OS << "#error \"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC must be defined when "
+"__ARM_FEATURE_SVE_BF16 is defined\"\n";
+  OS << "#endif\n";
+  OS << "typedef __SVBFloat16_t svbfloat16_t;\n";
+  OS << "#endif\n\n";
 
   OS << "#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC\n";
   OS << "typedef __bf16 bfloat16_t;\n";
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
 
 #include 
 
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -484,8 +484,8 @@
 let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64)" in {
   def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, 
"aarch64_sve_ld1ro">;
 }
-let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64) && 
defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)" in {
-  def SVLD1RO_BF : SInst<"svld1ro[_{2}]", "dPc", "b", MergeNone, 
"aarch64_sve_ld1ro">;
+let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64) && 
defined(__ARM_FEATURE_SVE_BF16)" in {
+  def SVLD1RO_BF16 : SInst<"svld1ro[_{2}]", "dPc", "b", MergeNone, 
"aarch64_sve_ld1ro">;
 }
 

 // Stores


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1085,8 +1085,15 @@
   OS << "typedef __SVUint16_t svuint16_t;\n";
   OS << "typedef __SVUint32_t svuint32_t;\n";
   OS << "typedef __SVUint64_t svuint64_t;\n";
-  OS << "typedef __SVFloat16_t svfloat16_t;\n";
-  OS << "typedef __SVBFloat16_t svbfloat16_t;\n\n";
+  OS << "typedef __SVFloat16_t svfloat16_t;\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
+  OS << "#if !defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)\n";
+  OS << "#error \"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC must be defined when "
+"__ARM_FEATURE_SVE_BF16 is defined\"\n";
+  OS << "#endif\n";
+  OS << "typedef __SVBFloat16_t svbfloat16_t;\n";
+  OS << "#endif\n\n";
 
   OS << "#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC\n";
   OS << "typedef __bf16 bfloat16_t;\n";
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_

[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, efriedma, stuij, david-arm, fpetrogalli, 
kmclaughlin.
Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, 
kristof.beyls, tschuett.
Herald added projects: clang, LLVM.

Added for following intrinsics:

- zip1, zip2, zip1q, zip2q
- trn1, trn2, trn1q, trn2q
- uzp1, uzp2, uzp1q, uzp2q
- splice
- rev
- sel


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82182

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2.c
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
@@ -57,6 +57,16 @@
   ret  %out
 }
 
+define  @sel_bf16( %pg,  %a,  %b) {
+; CHECK-LABEL: sel_bf16:
+; CHECK: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.sel.nxv8bf16( %pg,
+%a,
+%b)
+  ret  %out
+}
+
 define  @sel_f16( %pg,  %a,  %b) {
 ; CHECK-LABEL: sel_f16:
 ; CHECK: sel z0.h, p0, z0.h, z1.h
@@ -92,6 +102,7 @@
 declare  @llvm.aarch64.sve.sel.nxv8i16(, , )
 declare  @llvm.aarch64.sve.sel.nxv4i32(, , )
 declare  @llvm.aarch64.sve.sel.nxv2i64(, , )
+declare  @llvm.aarch64.sve.sel.nxv8bf16(, , )
 declare  @llvm.aarch64.sve.sel.nxv8f16(, , )
 declare  @llvm.aarch64.sve.sel.nxv4f32(, , )
 declare  @llvm.aarch64.sve.sel.nxv2f64(, , )
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -803,6 +803,14 @@
   ret  %res
 }
 
+define  @rev_bf16( %a) {
+; CHECK-LABEL: rev_bf16
+; CHECK: rev z0.h, z0.h
+; CHECK-NEXT: ret
+  %res = call  @llvm.aarch64.sve.rev.nxv8bf16( %a)
+  ret  %res
+}
+
 define  @rev_f16( %a) {
 ; CHECK-LABEL: rev_f16
 ; CHECK: rev z0.h, z0.h
@@ -871,6 +879,16 @@
   ret  %out
 }
 
+define  @splice_bf16( %pg,  %a,  %b) {
+; CHECK-LABEL: splice_bf16:
+; CHECK: splice z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.splice.nxv8bf16( %pg,
+   %a,
+   %b)
+  ret  %out
+}
+
 define  @splice_f16( %pg,  %a,  %b) {
 ; CHECK-LABEL: splice_f16:
 ; CHECK: splice z0.h, p0, z0.h, z1.h
@@ -1165,6 +1183,15 @@
   ret  %out
 }
 
+define  @trn1_bf16( %a,  %b) {
+; CHECK-LABEL: trn1_bf16:
+; CHECK: trn1 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.trn1.nxv8bf16( %a,
+ %b)
+  ret  %out
+}
+
 define  @trn1_f16( %a,  %b) {
 ; CHECK-LABEL: trn1_f16:
 ; CHECK: trn1 z0.h, z0.h, z1.h
@@ -1277,6 +1304,15 @@
   ret  %out
 }
 
+define  @trn2_bf16( %a,  %b) {
+; CHECK-LABEL: trn2_bf16:
+; CHECK: trn2 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.trn2.nxv8bf16( %a,
+ %b)
+  ret  %out
+}
+
 define  @trn2_f16( %a,  %b) {
 ; CHECK-LABEL: trn2_f16:
 ; CHECK: trn2 z0.h, z0.h, z1.h
@@ -1389,6 +1425,15 @@
   ret  %out
 }
 
+define  @uzp1_bf16( %a,  %b) {
+; CHECK-LABEL: uzp1_bf16:
+; CHECK: uzp1 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.uzp1.nxv8bf16( %a,
+ %b)
+  ret  %out
+}
+
 define  @uzp1_f16( %a,  %b) {
 ; CHECK-LABEL: uzp1_f16:
 ; CHECK: uzp1 z0.h, z0.h, z1.h
@@ -1501,6 +1546,15 @@
   ret  %out
 }
 
+define  @uzp2_bf16( %a,  %b) {
+; CHECK-LABEL: uzp2_bf16:
+; CHECK: uzp2 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.uzp2.n

[PATCH] D82186: [AArch64][SVE] Add bfloat16 support to svlen intrinsic

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, efriedma, david-arm, fpetrogalli, stuij.
Herald added subscribers: danielkiss, psnobl, rkruppe, kristof.beyls, tschuett.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82186

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c
  clang/utils/TableGen/SveEmitter.cpp


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -643,6 +643,7 @@
 Predicate = false;
 Signed = false;
 Float = false;
+BFloat = false;
 ElementBitwidth = Bitwidth = 64;
 NumVectors = 0;
 break;
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c
@@ -1,7 +1,7 @@
 // REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu 
-target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu 
-target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o 
- %s >/dev/null 2>%t
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-o - %s >/dev/null 2>%t
 // RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
 
 // If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README 
for instructions on how to resolve it.
@@ -113,3 +113,12 @@
   // CHECK: ret i64 %[[SHL]]
   return SVE_ACLE_FUNC(svlen,_f64,,)(op);
 }
+
+uint64_t test_svlen_bf16(svbfloat16_t op)
+{
+  // CHECK-LABEL: test_svlen_bf16
+  // CHECK: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
+  // CHECK: %[[SHL:.*]] = shl i64 %[[VSCALE]], 3
+  // CHECK: ret i64 %[[SHL]]
+  return SVE_ACLE_FUNC(svlen,_bf16,,)(op);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -8292,6 +8292,7 @@
   case SVE::BI__builtin_sve_svpfalse_b:
 return ConstantInt::getFalse(Ty);
 
+  case SVE::BI__builtin_sve_svlen_bf16:
   case SVE::BI__builtin_sve_svlen_f16:
   case SVE::BI__builtin_sve_svlen_f32:
   case SVE::BI__builtin_sve_svlen_f64:
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -1205,6 +1205,10 @@
 def SVCNTP : SInst<"svcntp_{d}",  "nPP", "PcPsPiPl",MergeNone, 
"aarch64_sve_cntp">;
 def SVLEN  : SInst<"svlen[_{d}]", "nd",  "csilUcUsUiUlhfd", MergeNone>;
 
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def SVLEN_BF16 : SInst<"svlen[_{d}]", "nd", "b", MergeNone>;
+}
+
 

 // Saturating scalar arithmetic
 


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -643,6 +643,7 @@
 Predicate = false;
 Signed = false;
 Float = false;
+BFloat = false;
 ElementBitwidth = Bitwidth = 64;
 NumVectors = 0;
 break;
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c
@@ -1,7 +1,7 @@
 // REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o

[PATCH] D82178: [AArch64][SVE] Guard svbfloat16_t with feature macro in ACLE

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 272091.
c-rhodes added a comment.

Changes:

- Include `arm_bf16.h` if `__ARM_FEATURE_BF16_SCALAR_ARITHMETIC` is defined.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82178/new/

https://reviews.llvm.org/D82178

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
  clang/utils/TableGen/SveEmitter.cpp


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1085,10 +1085,20 @@
   OS << "typedef __SVUint16_t svuint16_t;\n";
   OS << "typedef __SVUint32_t svuint32_t;\n";
   OS << "typedef __SVUint64_t svuint64_t;\n";
-  OS << "typedef __SVFloat16_t svfloat16_t;\n";
-  OS << "typedef __SVBFloat16_t svbfloat16_t;\n\n";
+  OS << "typedef __SVFloat16_t svfloat16_t;\n\n";
 
-  OS << "#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC\n";
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16) && "
+"!defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)\n";
+  OS << "#error \"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC must be defined when "
+"__ARM_FEATURE_SVE_BF16 is defined\"\n";
+  OS << "#endif\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
+  OS << "typedef __SVBFloat16_t svbfloat16_t;\n";
+  OS << "#endif\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)\n";
+  OS << "#include \n";
   OS << "typedef __bf16 bfloat16_t;\n";
   OS << "#endif\n\n";
 
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
 
 #include 
 
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -484,8 +484,8 @@
 let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64)" in {
   def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, 
"aarch64_sve_ld1ro">;
 }
-let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64) && 
defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)" in {
-  def SVLD1RO_BF : SInst<"svld1ro[_{2}]", "dPc", "b", MergeNone, 
"aarch64_sve_ld1ro">;
+let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64) && 
defined(__ARM_FEATURE_SVE_BF16)" in {
+  def SVLD1RO_BF16 : SInst<"svld1ro[_{2}]", "dPc", "b", MergeNone, 
"aarch64_sve_ld1ro">;
 }
 

 // Stores


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1085,10 +1085,20 @@
   OS << "typedef __SVUint16_t svuint16_t;\n";
   OS << "typedef __SVUint32_t svuint32_t;\n";
   OS << "typedef __SVUint64_t svuint64_t;\n";
-  OS << "typedef __SVFloat16_t svfloat16_t;\n";
-  OS << "typedef __SVBFloat16_t svbfloat16_t;\n\n";
+  OS << "typedef __SVFloat16_t svfloat16_t;\n\n";
 
-  OS << "#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC\n";
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16) && "
+"!defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)\n";
+  OS << "#error \"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC must be defined when "
+"__ARM_FEATURE_SVE_BF16 is defined\"\n";
+  OS << "#endif\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
+  OS << "typedef __SVBFloat16_t svbfloat16_t;\n";
+  OS << "#endif\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)\n";
+  OS << "#include \n";
   OS << "typedef __bf16

[PATCH] D82186: [AArch64][SVE] Add bfloat16 support to svlen intrinsic

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len.c:2
 // REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu 
-target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu 
-target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o 
- %s >/dev/null 2>%t
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s

fpetrogalli wrote:
> We said `ARM_FEATURE_BF16_SCALAR_ARITHMETIC` is implied by 
> `__ARM_FEATURE_SVE_BF16`, so I think you should remove this macro definition.
that's correct but it's not handled yet, `__ARM_FEATURE_SVE_BF16` isn't enabled 
as the implementation is incomplete, it'll eventually be enabled in the driver, 
but for now we need to explicitly define both macros in all tests.


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[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/arm_sve.td:1115
 
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def SVREV_BF16: SInst<"svrev[_{d}]","dd",   "b", MergeNone, 
"aarch64_sve_rev">;

fpetrogalli wrote:
> nit: could create a multiclass here like @sdesmalen have done in 
> https://reviews.llvm.org/D82187, seems quite a nice way to keep the 
> definition of the intrinsics together (look for `multiclass StructLoad`, for 
> example)
it might be a bit tedious having separate multiclasses, what do you think about:
```multiclass SInstBF16 ft = [], list ch = []> {
  def : SInst;
  let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
def : SInst;
  }
}

defm SVREV: SInstBF16<"svrev[_{d}]","dd",   "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_rev">;
defm SVSEL: SInstBF16<"svsel[_{d}]","dPdd", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_sel">;
defm SVSPLICE : SInstBF16<"svsplice[_{d}]", "dPdd", "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_splice">;
defm SVTRN1   : SInstBF16<"svtrn1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_trn1">;
defm SVTRN2   : SInstBF16<"svtrn2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_trn2">;
defm SVUZP1   : SInstBF16<"svuzp1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_uzp1">;
defm SVUZP2   : SInstBF16<"svuzp2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_uzp2">;
defm SVZIP1   : SInstBF16<"svzip1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_zip1">;
defm SVZIP2   : SInstBF16<"svzip2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_zip2">;```

?


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[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/arm_sve.td:1115
 
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def SVREV_BF16: SInst<"svrev[_{d}]","dd",   "b", MergeNone, 
"aarch64_sve_rev">;

c-rhodes wrote:
> fpetrogalli wrote:
> > nit: could create a multiclass here like @sdesmalen have done in 
> > https://reviews.llvm.org/D82187, seems quite a nice way to keep the 
> > definition of the intrinsics together (look for `multiclass StructLoad`, 
> > for example)
> it might be a bit tedious having separate multiclasses, what do you think 
> about:
> ```multiclass SInstBF16 = "",
>  list ft = [], list ch = []> {
>   def : SInst;
>   let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
> def : SInst;
>   }
> }
> 
> defm SVREV: SInstBF16<"svrev[_{d}]","dd",   "csilUcUsUiUlhfd", 
> MergeNone, "aarch64_sve_rev">;
> defm SVSEL: SInstBF16<"svsel[_{d}]","dPdd", "csilUcUsUiUlhfd", 
> MergeNone, "aarch64_sve_sel">;
> defm SVSPLICE : SInstBF16<"svsplice[_{d}]", "dPdd", "csilUcUsUiUlhfd", 
> MergeNone, "aarch64_sve_splice">;
> defm SVTRN1   : SInstBF16<"svtrn1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> MergeNone, "aarch64_sve_trn1">;
> defm SVTRN2   : SInstBF16<"svtrn2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> MergeNone, "aarch64_sve_trn2">;
> defm SVUZP1   : SInstBF16<"svuzp1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> MergeNone, "aarch64_sve_uzp1">;
> defm SVUZP2   : SInstBF16<"svuzp2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> MergeNone, "aarch64_sve_uzp2">;
> defm SVZIP1   : SInstBF16<"svzip1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> MergeNone, "aarch64_sve_zip1">;
> defm SVZIP2   : SInstBF16<"svzip2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> MergeNone, "aarch64_sve_zip2">;```
> 
> ?
I've played around with this and it works great for instructions guarded on a 
single feature flag but falls apart for the .Q forms that also require 
`__ARM_FEATURE_SVE_MATMUL_FP64`. I suspect there's a nice way of handling it in 
tablegen by passing the features as a list of strings and joining them but I 
spent long enough trying to get that to work so I'm going to keep it simple for 
now.


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[PATCH] D82178: [AArch64][SVE] Guard svbfloat16_t with feature macro in ACLE

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGc8fae2bb4afe: [AArch64][SVE] Guard svbfloat16_t with feature 
macro in ACLE (authored by c-rhodes).

Changed prior to commit:
  https://reviews.llvm.org/D82178?vs=272091&id=272664#toc

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Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
  clang/utils/TableGen/SveEmitter.cpp


Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -1088,10 +1088,20 @@
   OS << "typedef __SVUint16_t svuint16_t;\n";
   OS << "typedef __SVUint32_t svuint32_t;\n";
   OS << "typedef __SVUint64_t svuint64_t;\n";
-  OS << "typedef __SVFloat16_t svfloat16_t;\n";
-  OS << "typedef __SVBFloat16_t svbfloat16_t;\n\n";
+  OS << "typedef __SVFloat16_t svfloat16_t;\n\n";
 
-  OS << "#ifdef __ARM_FEATURE_BF16_SCALAR_ARITHMETIC\n";
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16) && "
+"!defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)\n";
+  OS << "#error \"__ARM_FEATURE_BF16_SCALAR_ARITHMETIC must be defined when "
+"__ARM_FEATURE_SVE_BF16 is defined\"\n";
+  OS << "#endif\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_SVE_BF16)\n";
+  OS << "typedef __SVBFloat16_t svbfloat16_t;\n";
+  OS << "#endif\n\n";
+
+  OS << "#if defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC)\n";
+  OS << "#include \n";
   OS << "typedef __bf16 bfloat16_t;\n";
   OS << "#endif\n\n";
 
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ld1ro-bfloat.c
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE -triple 
aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE_MATMUL_FP64 -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
 
 #include 
 
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfmmla.c
@@ -1,5 +1,5 @@
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 -triple 
aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
 
 #include 
 
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -494,8 +494,8 @@
 let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64)" in {
   def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, 
"aarch64_sve_ld1ro">;
 }
-let ArchGuard = "defined(__ARM_FEATURE_SVE_MAT

[PATCH] D82178: [AArch64][SVE] Guard svbfloat16_t with feature macro in ACLE

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

In D82178#2106847 , @fpetrogalli wrote:

> LGTM! Thanks.


Thanks for reviewing!


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[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel.c:2
 // REQUIRES: aarch64-registered-target
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu 
-target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -triple aarch64-none-linux-gnu 
-target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o 
- %s >/dev/null 2>%t
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s

sdesmalen wrote:
> Can you move the clang bfloat tests to separate files and add a RUN line 
> similar to what we've done for the sve2 tests (to check that we get a 
> diagnostic if +bf16 is not specified) ?
I can move the bfloat tests to separate files but I'm not sure about the RUN 
line, if `+bf16` is omitted we get the following:

```/home/culrho01/llvm-project/build/bin/clang -cc1 -internal-isystem 
/home/culrho01/llvm-project/build/lib/clang/11.0.0/include -nostdsysteminc 
-D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-fallow-half-arguments-and-returns -fsyntax-only -verify 
/home/culrho01/llvm-project/clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c
error: no expected directives found: consider use of 'expected-no-diagnostics'
error: 'error' diagnostics seen but not expected:
  File /home/culrho01/llvm-project/build/lib/clang/11.0.0/include/arm_bf16.h 
Line 14: __bf16 is not supported on this target
  File /home/culrho01/llvm-project/build/lib/clang/11.0.0/include/arm_sve.h 
Line 52: __bf16 is not supported on this target
3 errors generated.```

Whereas I think the desired behaviour we want to test as we do for sve2 is 
checking the intrinsics are guarded with the right feature flag, which at the 
moment would be omitting `-D__ARM_FEATURE_SVE_BF16` from the RUN line, until 
`+bf16` implies `-D__ARM_FEATURE_SVE_BF16` anyway, which is when the ACLE is 
fully complete. Should I do that? I guess we'd want to update this RUN line to 
omit `+bf16` when it implies the feature macro


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[PATCH] D82369: [SveEmitter] Add verify-checks to Clang bfloat16 tests

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_bfdot.c:3-6
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu 
-target-feature +sve -fallow-half-arguments-and-returns -fsyntax-only -verify %s
+
+// expected-error@arm_bf16.h:* {{__bf16 is not supported on this target}}
+// expected-error@arm_sve.h:*  {{__bf16 is not supported on this target}}

I don't think there's any value in testing this for each ACLE test adding 
bfloat support, see my comment here: https://reviews.llvm.org/D82182#2108831

There's value in checking that specific intrinsics are guarded by 
`__ARM_FEATURE_SVE_BF16` (which will eventually be implied by `+bf16`), but I 
suspect we could create a single test for what you've added here that just 
includes `arm_sve.h`.



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[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 272745.
c-rhodes added a comment.

Changes:

- Moved bfloat tests to separate files.
- Added checks to test intrinsics are guarded by feature flag, this is by 
omitting the feature macro `__ARM_FEATURE_SVE_BF16` for now but will eventually 
be updated to omit `+bf16` once the feature flag implies the macro.


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Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
@@ -57,6 +57,16 @@
   ret  %out
 }
 
+define  @sel_bf16( %pg,  %a,  %b) {
+; CHECK-LABEL: sel_bf16:
+; CHECK: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.sel.nxv8bf16( %pg,
+%a,
+%b)
+  ret  %out
+}
+
 define  @sel_f16( %pg,  %a,  %b) {
 ; CHECK-LABEL: sel_f16:
 ; CHECK: sel z0.h, p0, z0.h, z1.h
@@ -92,6 +102,7 @@
 declare  @llvm.aarch64.sve.sel.nxv8i16(, , )
 declare  @llvm.aarch64.sve.sel.nxv4i32(, , )
 declare  @llvm.aarch64.sve.sel.nxv2i64(, , )
+declare  @llvm.aarch64.sve.sel.nxv8bf16(, , )
 declare  @llvm.aarch64.sve.sel.nxv8f16(, , )
 declare  @llvm.aarch64.sve.sel.nxv4f32(, , )
 declare  @llvm.aarch64.sve.sel.nxv2f64(, , )
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -806,6 +806,14 @@
   ret  %res
 }
 
+define  @rev_bf16( %a) {
+; CHECK-LABEL: rev_bf16
+; CHECK: rev z0.h, z0.h
+; CHECK-NEXT: ret
+  %res = call  @llvm.aarch64.sve.rev.nxv8bf16( %a)
+  ret  %res
+}
+
 define  @rev_f16( %a) {
 ; CHECK-LABEL: rev_f16
 ; CHECK: rev z0.h, z0.h
@@ -874,6 +882,16 @@
   ret  %out
 }
 
+define  @splice_bf16( %pg,  %a,  %b) {
+; CHECK-LABEL: splice_bf16:
+; CHECK: splice z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.splice.nxv8bf16( %pg,
+   %a,
+   %b)
+  ret  %out
+}
+
 define  @splice_f16( %pg,  %a,  %b) {
 ; CHECK-LABEL: splice_f16:
 ; CHECK: splice z0.h, p0, z0.h, z1.h
@@ -1168,6 +1186,15 @@
   ret  %out
 }
 
+define  @trn1_bf16( %a,  %b) {
+; CHECK-LABEL: trn1_bf16:
+; CHECK: trn1 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.trn1.nxv8bf16( %a,
+ %b)
+  ret  %out
+}
+
 define  @trn1_f16( %a,  %b) {
 ; CHECK-LABEL: trn1_f16:
 ; CHECK: trn1 z0.h, z0.h, z1.h
@@ -1280,6 +1307,15 @@
   ret  %out
 }
 
+define  @trn2_bf16( %a,  %b) {
+; CHECK-LABEL: trn2_bf16:
+; CHECK: trn2 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.trn2.nxv8bf16( %a,
+ %b)
+  ret  %out
+}
+
 define  @trn2_f16( %a,  %b) {
 ; CHECK-LABEL: trn2_f16:
 ; CHECK: trn2 z0.h, z0.h, z1.h
@@ -1392,6 +1428,15 @@
   ret  %out
 }
 
+define  @uzp1_bf16( %a,  %b) {
+; CHECK-LABEL: uzp1_bf16:
+; CHECK: uzp1 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.uzp1.nxv8bf16( %a,
+ %b)
+  ret  %out
+}
+
 define  @uzp1_f16( %a,  %b) {
 ; CHECK-LABEL: uzp1_f16:
 ; CHECK: uzp1 z0.h, z0.h, z1.h
@@ -1504,6 +1549,15 @@
   ret  %out
 }
 
+define  @uzp2_bf16( %a,  %b) {
+; CHECK-LABEL: uzp2_bf16:

[PATCH] D82186: [AArch64][SVE] Add bfloat16 support to svlen intrinsic

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 272753.
c-rhodes added a comment.

Changes:

- Rebased.
- Moved bfloat test to separate file.
- Added checks to test intrinsics are guarded by feature flag, this is by 
omitting the feature macro `__ARM_FEATURE_SVE_BF16` for now but will eventually 
be updated to omit `+bf16` once the feature flag implies the macro.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82186/new/

https://reviews.llvm.org/D82186

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c


Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c
@@ -0,0 +1,27 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-o - %s >/dev/null 2>%t
+// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify 
-verify-ignore-unexpected=error -verify-ignore-unexpected=note %s
+
+// If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README 
for instructions on how to resolve it.
+// ASM-NOT: warning
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+uint64_t test_svlen_bf16(svbfloat16_t op)
+{
+  // CHECK-LABEL: test_svlen_bf16
+  // CHECK: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
+  // CHECK: %[[SHL:.*]] = shl i64 %[[VSCALE]], 3
+  // CHECK: ret i64 %[[SHL]]
+  // expected-warning@+1 {{implicit declaration of function 'svlen_bf16'}}
+  return SVE_ACLE_FUNC(svlen,_bf16,,)(op);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -8413,6 +8413,7 @@
   case SVE::BI__builtin_sve_svpfalse_b:
 return ConstantInt::getFalse(Ty);
 
+  case SVE::BI__builtin_sve_svlen_bf16:
   case SVE::BI__builtin_sve_svlen_f16:
   case SVE::BI__builtin_sve_svlen_f32:
   case SVE::BI__builtin_sve_svlen_f64:
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -1244,6 +1244,10 @@
 def SVCNTP : SInst<"svcntp_{d}",  "nPP", "PcPsPiPl",MergeNone, 
"aarch64_sve_cntp">;
 def SVLEN  : SInst<"svlen[_{d}]", "nd",  "csilUcUsUiUlhfd", MergeNone>;
 
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def SVLEN_BF16 : SInst<"svlen[_{d}]", "nd", "b", MergeNone>;
+}
+
 

 // Saturating scalar arithmetic
 


Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c
@@ -0,0 +1,27 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o - %s >/dev/null 2>%t
+// RUN: FileCheck --check-prefix=ASM --allow-empty %s 

[PATCH] D82391: [AArch64][SVE] Add bfloat16 support to svext intrinsic

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, kmclaughlin, efriedma, david-arm, 
fpetrogalli.
Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, 
kristof.beyls, tschuett.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82391

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
  clang/utils/TableGen/SveEmitter.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -516,6 +516,16 @@
   ret  %out
 }
 
+define  @ext_bf16( %a,  %b) {
+; CHECK-LABEL: ext_bf16:
+; CHECK: ext z0.b, z0.b, z1.b, #6
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.ext.nxv8bf16( %a,
+%b,
+   i32 3)
+  ret  %out
+}
+
 define  @ext_f16( %a,  %b) {
 ; CHECK-LABEL: ext_f16:
 ; CHECK: ext z0.b, z0.b, z1.b, #6
@@ -1876,6 +1886,7 @@
 declare  @llvm.aarch64.sve.ext.nxv8i16(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv4i32(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv2i64(, , i32)
+declare  @llvm.aarch64.sve.ext.nxv8bf16(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv8f16(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv4f32(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv2f64(, , i32)
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1405,12 +1405,13 @@
   // constraint that none of the bits change when stored to memory as one
   // type, and and reloaded as another type.
   let Predicates = [IsLE] in {
-def : Pat<(nxv16i8 (bitconvert (nxv8i16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
-def : Pat<(nxv16i8 (bitconvert (nxv4i32 ZPR:$src))), (nxv16i8 ZPR:$src)>;
-def : Pat<(nxv16i8 (bitconvert (nxv2i64 ZPR:$src))), (nxv16i8 ZPR:$src)>;
-def : Pat<(nxv16i8 (bitconvert (nxv8f16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
-def : Pat<(nxv16i8 (bitconvert (nxv4f32 ZPR:$src))), (nxv16i8 ZPR:$src)>;
-def : Pat<(nxv16i8 (bitconvert (nxv2f64 ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv16i8 (bitconvert (nxv8i16  ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv16i8 (bitconvert (nxv4i32  ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv16i8 (bitconvert (nxv2i64  ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv16i8 (bitconvert (nxv8f16  ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv16i8 (bitconvert (nxv4f32  ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv16i8 (bitconvert (nxv2f64  ZPR:$src))), (nxv16i8 ZPR:$src)>;
+def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
 
 def : Pat<(nxv8i16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 def : Pat<(nxv8i16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8i16 ZPR:$src)>;
@@ -1435,7 +1436,6 @@
 
 def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
-def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
@@ -1454,6 +1454,9 @@
 def : Pat<(nxv2f64 (bitconvert (nxv2i64 ZPR:$src))), (nxv2f64 ZPR:$src)>;
 def : Pat<(nxv2f64 (bitconvert (nxv8f16 ZPR:$src))), (nxv2f64 ZPR:$src)>;
 def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>;
+
+def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
   }
 
   def : Pat<(nxv16i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>;
Index: clang/utils/TableGen/SveEmitter.cpp
===
--- clang/utils/TableGen/SveEmitter.cpp
+++ clang/utils/TableGen/SveEmitter.cpp
@@ -596,6 +596,7 @@
   case 'i':
 Predicate = false;
 Float = false;
+BFloat = false;
 ElementBitwidth = Bitwidth = 64;
 NumVectors = 0;
 Signed = false;
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
@@ -0,0 +1,26 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 

[PATCH] D82399: [AArch64][SVE2] Add bfloat16 support to whilerw/whilewr intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, efriedma, kmclaughlin, david-arm, 
fpetrogalli, stuij.
Herald added subscribers: danielkiss, kristof.beyls, tschuett.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82399

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilerw-bfloat.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
  llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll

Index: llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
===
--- llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
+++ llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
@@ -36,6 +36,14 @@
   ret  %out
 }
 
+define  @whilerw_bfloat(bfloat* %a, bfloat* %b) {
+; CHECK-LABEL: whilerw_bfloat:
+; CHECK: whilerw  p0.h, x0, x1
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.whilerw.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
+  ret  %out
+}
+
 define  @whilerw_half(half* %a, half* %b) {
 ; CHECK-LABEL: whilerw_half:
 ; CHECK: whilerw  p0.h, x0, x1
@@ -96,6 +104,14 @@
   ret  %out
 }
 
+define  @whilewr_bfloat(bfloat* %a, bfloat* %b) {
+; CHECK-LABEL: whilewr_bfloat:
+; CHECK: whilewr  p0.h, x0, x1
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.whilewr.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
+  ret  %out
+}
+
 define  @whilewr_half(half* %a, half* %b) {
 ; CHECK-LABEL: whilewr_half:
 ; CHECK: whilewr  p0.h, x0, x1
@@ -125,6 +141,7 @@
 declare  @llvm.aarch64.sve.whilerw.s.nx4i1(i32* %a, i32* %b)
 declare  @llvm.aarch64.sve.whilerw.d.nx2i1(i64* %a, i64* %b)
 
+declare  @llvm.aarch64.sve.whilerw.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
 declare  @llvm.aarch64.sve.whilerw.h.nx8i1.f16.f16(half* %a, half* %b)
 declare  @llvm.aarch64.sve.whilerw.s.nx4i1.f32.f32(float* %a, float* %b)
 declare  @llvm.aarch64.sve.whilerw.d.nx2i1.f64.f64(double* %a, double* %b)
@@ -134,6 +151,7 @@
 declare  @llvm.aarch64.sve.whilewr.s.nx4i1(i32* %a, i32* %b)
 declare  @llvm.aarch64.sve.whilewr.d.nx2i1(i64* %a, i64* %b)
 
+declare  @llvm.aarch64.sve.whilewr.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
 declare  @llvm.aarch64.sve.whilewr.h.nx8i1.f16.f16(half* %a, half* %b)
 declare  @llvm.aarch64.sve.whilewr.s.nx4i1.f32.f32(float* %a, float* %b)
 declare  @llvm.aarch64.sve.whilewr.d.nx2i1.f64.f64(double* %a, double* %b)
Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+// Test expected warnings for implicit declaration when +sve2 is missing
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+// Test expected warnings for implicit declaration when +bf16 is missing
+// NOTE: +bf16 doesn't currently imply __ARM_FEATURE_SVE_BF16, once the
+// implementation is complete it will, at which point -target-feature +bf16
+// should be removed.
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+
+// Test expected ambiguous call error for overloaded form when +bf16 is missing
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify=overload-bf16 -verify-ignore-unexpected=note %s
+
+#include 
+
+#ifdef SVE_OVERLOADED

[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/arm_sve.td:1115
 
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def SVREV_BF16: SInst<"svrev[_{d}]","dd",   "b", MergeNone, 
"aarch64_sve_rev">;

fpetrogalli wrote:
> c-rhodes wrote:
> > c-rhodes wrote:
> > > fpetrogalli wrote:
> > > > nit: could create a multiclass here like @sdesmalen have done in 
> > > > https://reviews.llvm.org/D82187, seems quite a nice way to keep the 
> > > > definition of the intrinsics together (look for `multiclass 
> > > > StructLoad`, for example)
> > > it might be a bit tedious having separate multiclasses, what do you think 
> > > about:
> > > ```multiclass SInstBF16 > > string i = "",
> > >  list ft = [], list ch = []> {
> > >   def : SInst;
> > >   let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
> > > def : SInst;
> > >   }
> > > }
> > > 
> > > defm SVREV: SInstBF16<"svrev[_{d}]","dd",   "csilUcUsUiUlhfd", 
> > > MergeNone, "aarch64_sve_rev">;
> > > defm SVSEL: SInstBF16<"svsel[_{d}]","dPdd", "csilUcUsUiUlhfd", 
> > > MergeNone, "aarch64_sve_sel">;
> > > defm SVSPLICE : SInstBF16<"svsplice[_{d}]", "dPdd", "csilUcUsUiUlhfd", 
> > > MergeNone, "aarch64_sve_splice">;
> > > defm SVTRN1   : SInstBF16<"svtrn1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > MergeNone, "aarch64_sve_trn1">;
> > > defm SVTRN2   : SInstBF16<"svtrn2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > MergeNone, "aarch64_sve_trn2">;
> > > defm SVUZP1   : SInstBF16<"svuzp1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > MergeNone, "aarch64_sve_uzp1">;
> > > defm SVUZP2   : SInstBF16<"svuzp2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > MergeNone, "aarch64_sve_uzp2">;
> > > defm SVZIP1   : SInstBF16<"svzip1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > MergeNone, "aarch64_sve_zip1">;
> > > defm SVZIP2   : SInstBF16<"svzip2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > MergeNone, "aarch64_sve_zip2">;```
> > > 
> > > ?
> > I've played around with this and it works great for instructions guarded on 
> > a single feature flag but falls apart for the .Q forms that also require 
> > `__ARM_FEATURE_SVE_MATMUL_FP64`. I suspect there's a nice way of handling 
> > it in tablegen by passing the features as a list of strings and joining 
> > them but I spent long enough trying to get that to work so I'm going to 
> > keep it simple for now.
> > it might be a bit tedious having separate multiclasses, what do you think 
> > about:
> 
> Sorry I think I misunderstood you when we last discussed this. I didn't mean 
> to write a multiclass that would work for ALL intrinsics that uses regular 
> types and bfloats I just meant to merge together those who were using the 
> same archguard and that you are adding in this patch.
> 
> I think you could keep both macros in a single ArchGuard string:
> 
> ```
> multiclass SInstPerm {
>   def : SInst;
>   let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
> def : SInst;
>   }
> }
> 
> defm SVREV: SInstPerm<"svrev[_{d}]","dd",MergeNone, 
> "aarch64_sve_rev">;
> ...
> 
> multiclass SInstPermMatmul {
>   def : SInst;
>   let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16) && 
> defined(__ARM_FEATURE_SVE_MATMUL_FP64)" in {
> def : SInst;
>   }
> }
> 
> def SVTRN1Q : SInstPermMatmul ...
> ...
> ```
Sure, I understood you meant separate multiclasses for each intrinsic / group 
similar to what Sander implemented for structured loads / stores but I thought 
it would be quite abit of extra code to implement that, hence why I proposed a 
single multiclass that could handle this. I've experimented with the 
`SInstBF16` multiclass I mentioned above and have it working with an extra arg 
for arch features. I'll create a follow up patch and if people are happy with 
it we'll move forward with that, otherwise I'm happy to implement your 
suggestion.


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[PATCH] D82399: [AArch64][SVE2] Add bfloat16 support to whilerw/whilewr intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG05e10ee0aee0: [AArch64][SVE2] Add bfloat16 support to 
whilerw/whilewr intrinsics (authored by c-rhodes).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82399/new/

https://reviews.llvm.org/D82399

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilerw-bfloat.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
  llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll

Index: llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
===
--- llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
+++ llvm/test/CodeGen/AArch64/sve2-intrinsics-contiguous-conflict-detection.ll
@@ -36,6 +36,14 @@
   ret  %out
 }
 
+define  @whilerw_bfloat(bfloat* %a, bfloat* %b) {
+; CHECK-LABEL: whilerw_bfloat:
+; CHECK: whilerw  p0.h, x0, x1
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.whilerw.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
+  ret  %out
+}
+
 define  @whilerw_half(half* %a, half* %b) {
 ; CHECK-LABEL: whilerw_half:
 ; CHECK: whilerw  p0.h, x0, x1
@@ -96,6 +104,14 @@
   ret  %out
 }
 
+define  @whilewr_bfloat(bfloat* %a, bfloat* %b) {
+; CHECK-LABEL: whilewr_bfloat:
+; CHECK: whilewr  p0.h, x0, x1
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.whilewr.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
+  ret  %out
+}
+
 define  @whilewr_half(half* %a, half* %b) {
 ; CHECK-LABEL: whilewr_half:
 ; CHECK: whilewr  p0.h, x0, x1
@@ -125,6 +141,7 @@
 declare  @llvm.aarch64.sve.whilerw.s.nx4i1(i32* %a, i32* %b)
 declare  @llvm.aarch64.sve.whilerw.d.nx2i1(i64* %a, i64* %b)
 
+declare  @llvm.aarch64.sve.whilerw.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
 declare  @llvm.aarch64.sve.whilerw.h.nx8i1.f16.f16(half* %a, half* %b)
 declare  @llvm.aarch64.sve.whilerw.s.nx4i1.f32.f32(float* %a, float* %b)
 declare  @llvm.aarch64.sve.whilerw.d.nx2i1.f64.f64(double* %a, double* %b)
@@ -134,6 +151,7 @@
 declare  @llvm.aarch64.sve.whilewr.s.nx4i1(i32* %a, i32* %b)
 declare  @llvm.aarch64.sve.whilewr.d.nx2i1(i64* %a, i64* %b)
 
+declare  @llvm.aarch64.sve.whilewr.h.nx8i1.bf16.bf16(bfloat* %a, bfloat* %b)
 declare  @llvm.aarch64.sve.whilewr.h.nx8i1.f16.f16(half* %a, half* %b)
 declare  @llvm.aarch64.sve.whilewr.s.nx4i1.f32.f32(float* %a, float* %b)
 declare  @llvm.aarch64.sve.whilewr.d.nx2i1.f64.f64(double* %a, double* %b)
Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
@@ -0,0 +1,36 @@
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+
+// Test expected warnings for implicit declaration when +sve2 is missing
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
+
+// Test expected warnings for implicit declaration when +bf16 is missing
+// NOTE: +bf16 doesn't currently imply __ARM_FEATURE_SVE_BF16, once the
+// implementation is complete it will, at which point -target-feature +bf16
+// should be removed.
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify -verify-ignore-unexpected=error %s
+
+// Test expected ambiguous call error for overloaded form when +bf16 is missing
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify=overload-bf16 -verify-ignore-unexpected=not

[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG26502ad60922: [AArch64][SVE] Add bfloat16 support to perm 
and select intrinsics (authored by c-rhodes).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82182/new/

https://reviews.llvm.org/D82182

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_rev-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_sel-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_splice-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn1-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_trn2-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp1-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_uzp2-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip1-fp64-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_zip2-fp64-bfloat.c
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-sel.ll
@@ -57,6 +57,16 @@
   ret  %out
 }
 
+define  @sel_bf16( %pg,  %a,  %b) {
+; CHECK-LABEL: sel_bf16:
+; CHECK: sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.sel.nxv8bf16( %pg,
+%a,
+%b)
+  ret  %out
+}
+
 define  @sel_f16( %pg,  %a,  %b) {
 ; CHECK-LABEL: sel_f16:
 ; CHECK: sel z0.h, p0, z0.h, z1.h
@@ -92,6 +102,7 @@
 declare  @llvm.aarch64.sve.sel.nxv8i16(, , )
 declare  @llvm.aarch64.sve.sel.nxv4i32(, , )
 declare  @llvm.aarch64.sve.sel.nxv2i64(, , )
+declare  @llvm.aarch64.sve.sel.nxv8bf16(, , )
 declare  @llvm.aarch64.sve.sel.nxv8f16(, , )
 declare  @llvm.aarch64.sve.sel.nxv4f32(, , )
 declare  @llvm.aarch64.sve.sel.nxv2f64(, , )
Index: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -806,6 +806,14 @@
   ret  %res
 }
 
+define  @rev_bf16( %a) {
+; CHECK-LABEL: rev_bf16
+; CHECK: rev z0.h, z0.h
+; CHECK-NEXT: ret
+  %res = call  @llvm.aarch64.sve.rev.nxv8bf16( %a)
+  ret  %res
+}
+
 define  @rev_f16( %a) {
 ; CHECK-LABEL: rev_f16
 ; CHECK: rev z0.h, z0.h
@@ -874,6 +882,16 @@
   ret  %out
 }
 
+define  @splice_bf16( %pg,  %a,  %b) {
+; CHECK-LABEL: splice_bf16:
+; CHECK: splice z0.h, p0, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.splice.nxv8bf16( %pg,
+   %a,
+   %b)
+  ret  %out
+}
+
 define  @splice_f16( %pg,  %a,  %b) {
 ; CHECK-LABEL: splice_f16:
 ; CHECK: splice z0.h, p0, z0.h, z1.h
@@ -1168,6 +1186,15 @@
   ret  %out
 }
 
+define  @trn1_bf16( %a,  %b) {
+; CHECK-LABEL: trn1_bf16:
+; CHECK: trn1 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.trn1.nxv8bf16( %a,
+ %b)
+  ret  %out
+}
+
 define  @trn1_f16( %a,  %b) {
 ; CHECK-LABEL: trn1_f16:
 ; CHECK: trn1 z0.h, z0.h, z1.h
@@ -1280,6 +1307,15 @@
   ret  %out
 }
 
+define  @trn2_bf16( %a,  %b) {
+; CHECK-LABEL: trn2_bf16:
+; CHECK: trn2 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.trn2.nxv8bf16( %a,
+ %b)
+  ret  %out
+}
+
 define  @trn2_f16( %a,  %b) {
 ; CHECK-LABEL: trn2_f16:
 ; CHECK: trn2 z0.h, z0.h, z1.h
@@ -1392,6 +1428,15 @@
   ret  %out
 }
 
+define  @uzp1_bf16( %a,  %b) {
+; CHECK-LABEL: uzp1_bf16:
+; CHECK: uzp1 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.uzp1.nxv8bf16( %a,
+ %b)
+  ret  %out
+}
+
 define  @uzp1_f16( %a,  %b) {
 ; CHECK-LABEL: uzp1_f16:
 ; CHECK: uzp1 z0.h, z0.h, z1.h
@@ -1504,6 +1549,15 @@
   ret  %out
 }
 
+define  @uzp2_bf16( %a,  %b) {
+; CHECK-LABEL: uzp2_bf16:
+; CHECK: uzp2 z0.h, z0.h, z1.h
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.uzp2.nxv8bf16( %a,
+  

[PATCH] D82186: [AArch64][SVE] Add bfloat16 support to svlen intrinsic

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGfd2c4b899932: [AArch64][SVE] Add bfloat16 support to svlen 
intrinsic (authored by c-rhodes).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82186/new/

https://reviews.llvm.org/D82186

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c


Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c
@@ -0,0 +1,27 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-o - %s >/dev/null 2>%t
+// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify 
-verify-ignore-unexpected=error -verify-ignore-unexpected=note %s
+
+// If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README 
for instructions on how to resolve it.
+// ASM-NOT: warning
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+uint64_t test_svlen_bf16(svbfloat16_t op)
+{
+  // CHECK-LABEL: test_svlen_bf16
+  // CHECK: %[[VSCALE:.*]] = call i64 @llvm.vscale.i64()
+  // CHECK: %[[SHL:.*]] = shl i64 %[[VSCALE]], 3
+  // CHECK: ret i64 %[[SHL]]
+  // expected-warning@+1 {{implicit declaration of function 'svlen_bf16'}}
+  return SVE_ACLE_FUNC(svlen,_bf16,,)(op);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -8434,6 +8434,7 @@
   case SVE::BI__builtin_sve_svpfalse_b:
 return ConstantInt::getFalse(Ty);
 
+  case SVE::BI__builtin_sve_svlen_bf16:
   case SVE::BI__builtin_sve_svlen_f16:
   case SVE::BI__builtin_sve_svlen_f32:
   case SVE::BI__builtin_sve_svlen_f64:
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -1281,6 +1281,10 @@
 def SVCNTP : SInst<"svcntp_{d}",  "nPP", "PcPsPiPl",MergeNone, 
"aarch64_sve_cntp">;
 def SVLEN  : SInst<"svlen[_{d}]", "nd",  "csilUcUsUiUlhfd", MergeNone>;
 
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def SVLEN_BF16 : SInst<"svlen[_{d}]", "nd", "b", MergeNone>;
+}
+
 

 // Saturating scalar arithmetic
 


Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_len-bfloat.c
@@ -0,0 +1,27 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o - %s >/dev/null 2>%t
+// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu -target-feature +s

[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked an inline comment as done.
c-rhodes added inline comments.



Comment at: clang/include/clang/Basic/arm_sve.td:1115
 
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def SVREV_BF16: SInst<"svrev[_{d}]","dd",   "b", MergeNone, 
"aarch64_sve_rev">;

c-rhodes wrote:
> fpetrogalli wrote:
> > c-rhodes wrote:
> > > c-rhodes wrote:
> > > > fpetrogalli wrote:
> > > > > nit: could create a multiclass here like @sdesmalen have done in 
> > > > > https://reviews.llvm.org/D82187, seems quite a nice way to keep the 
> > > > > definition of the intrinsics together (look for `multiclass 
> > > > > StructLoad`, for example)
> > > > it might be a bit tedious having separate multiclasses, what do you 
> > > > think about:
> > > > ```multiclass SInstBF16 > > > string i = "",
> > > >  list ft = [], list ch = []> {
> > > >   def : SInst;
> > > >   let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
> > > > def : SInst;
> > > >   }
> > > > }
> > > > 
> > > > defm SVREV: SInstBF16<"svrev[_{d}]","dd",   "csilUcUsUiUlhfd", 
> > > > MergeNone, "aarch64_sve_rev">;
> > > > defm SVSEL: SInstBF16<"svsel[_{d}]","dPdd", "csilUcUsUiUlhfd", 
> > > > MergeNone, "aarch64_sve_sel">;
> > > > defm SVSPLICE : SInstBF16<"svsplice[_{d}]", "dPdd", "csilUcUsUiUlhfd", 
> > > > MergeNone, "aarch64_sve_splice">;
> > > > defm SVTRN1   : SInstBF16<"svtrn1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > > MergeNone, "aarch64_sve_trn1">;
> > > > defm SVTRN2   : SInstBF16<"svtrn2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > > MergeNone, "aarch64_sve_trn2">;
> > > > defm SVUZP1   : SInstBF16<"svuzp1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > > MergeNone, "aarch64_sve_uzp1">;
> > > > defm SVUZP2   : SInstBF16<"svuzp2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > > MergeNone, "aarch64_sve_uzp2">;
> > > > defm SVZIP1   : SInstBF16<"svzip1[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > > MergeNone, "aarch64_sve_zip1">;
> > > > defm SVZIP2   : SInstBF16<"svzip2[_{d}]",   "ddd",  "csilUcUsUiUlhfd", 
> > > > MergeNone, "aarch64_sve_zip2">;```
> > > > 
> > > > ?
> > > I've played around with this and it works great for instructions guarded 
> > > on a single feature flag but falls apart for the .Q forms that also 
> > > require `__ARM_FEATURE_SVE_MATMUL_FP64`. I suspect there's a nice way of 
> > > handling it in tablegen by passing the features as a list of strings and 
> > > joining them but I spent long enough trying to get that to work so I'm 
> > > going to keep it simple for now.
> > > it might be a bit tedious having separate multiclasses, what do you think 
> > > about:
> > 
> > Sorry I think I misunderstood you when we last discussed this. I didn't 
> > mean to write a multiclass that would work for ALL intrinsics that uses 
> > regular types and bfloats I just meant to merge together those who were 
> > using the same archguard and that you are adding in this patch.
> > 
> > I think you could keep both macros in a single ArchGuard string:
> > 
> > ```
> > multiclass SInstPerm {
> >   def : SInst;
> >   let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
> > def : SInst;
> >   }
> > }
> > 
> > defm SVREV: SInstPerm<"svrev[_{d}]","dd",MergeNone, 
> > "aarch64_sve_rev">;
> > ...
> > 
> > multiclass SInstPermMatmul {
> >   def : SInst;
> >   let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16) && 
> > defined(__ARM_FEATURE_SVE_MATMUL_FP64)" in {
> > def : SInst;
> >   }
> > }
> > 
> > def SVTRN1Q : SInstPermMatmul ...
> > ...
> > ```
> Sure, I understood you meant separate multiclasses for each intrinsic / group 
> similar to what Sander implemented for structured loads / stores but I 
> thought it would be quite abit of extra code to implement that, hence why I 
> proposed a single multiclass that could handle this. I've experimented with 
> the `SInstBF16` multiclass I mentioned above and have it working with an 
> extra arg for arch features. I'll create a follow up patch and if people are 
> happy with it we'll move forward with that, otherwise I'm happy to implement 
> your suggestion.
> I'll create a follow up patch

https://reviews.llvm.org/D82450


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[PATCH] D82450: [AArch64][SVE] Add multiclass for bfloat16 intrinsic definitions

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, fpetrogalli, kmclaughlin, efriedma.
Herald added subscribers: danielkiss, psnobl, rkruppe, kristof.beyls, tschuett.
Herald added a project: clang.

Patch implements a multiclass 'SInstBF16', a wrapper around SInst that
also defines a bfloat16 variant. This is used to merge the definitions
of intrinsics with bfloat16 support. The multiclass also handles
multiple arch guards.


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Files:
  clang/include/clang/Basic/arm_sve.td

Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -253,6 +253,26 @@
 : Inst {
 }
 
+// SInstBF16: Wrapper around SInst that also defines a bfloat16 instruction
+// guarded by __ARM_FEATURE_SVE_BF16. Type signature matches SInst but has an
+// extra arg 'arch_features', a list of strings used to construct the
+// ArchGuard. This is useful for defining intrinsics that are guarded on one or
+// more arch features.
+multiclass SInstBF16 ft = [], list ch = [],
+ list arch_features = []> {
+  let ArchGuard = !foldl("", arch_features, lhs, rhs,
+ lhs # !if(!ne(lhs, ""), " && ", "") # rhs) in {
+def : SInst;
+  }
+  let ArchGuard = !foldl("", !listconcat(arch_features,
+ ["__ARM_FEATURE_SVE_BF16"]),
+ lhs, rhs,
+ lhs # !if(!ne(lhs, ""), " && ", "") # rhs) in {
+def : SInst;
+  }
+}
+
 // MInst: Instructions which access memory
 class MInst f,
 MemEltType met = MemEltTyDefault, string i = "">
@@ -498,11 +518,7 @@
 }
 
 // Load one quadword and replicate (scalar base)
-def SVLD1RQ : SInst<"svld1rq[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_ld1rq">;
-
-let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
-  def SVLD1RQ_BF : SInst<"svld1rq[_{2}]", "dPc",  "b", MergeNone, "aarch64_sve_ld1rq">;
-}
+defm SVLD1RQ : SInstBF16<"svld1rq[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_ld1rq">;
 
 multiclass StructLoad {
   def : SInst;
@@ -522,12 +538,7 @@
 defm SVLD4_VNUM : StructLoad<"svld4_vnum[_{2}]", "4Pcl", "aarch64_sve_ld4">;
 
 // Load one octoword and replicate (scalar base)
-let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64)" in {
-  def SVLD1RO : SInst<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_ld1ro">;
-}
-let ArchGuard = "defined(__ARM_FEATURE_SVE_MATMUL_FP64) && defined(__ARM_FEATURE_SVE_BF16)" in {
-  def SVLD1RO_BF16 : SInst<"svld1ro[_{2}]", "dPc", "b", MergeNone, "aarch64_sve_ld1ro">;
-}
+defm SVLD1RO : SInstBF16<"svld1ro[_{2}]", "dPc", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_ld1ro", [], [], ["__ARM_FEATURE_SVE_MATMUL_FP64"]>;
 
 let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
   def SVBFDOT: SInst<"svbfdot[_{0}]","MMdd",  "b", MergeNone, "aarch64_sve_bfdot",[IsOverloadNone]>;
@@ -1170,36 +1181,24 @@
 // instruction's immediate.
 def SVDUP_LANE   : SInst<"svdup_lane[_{d}]",  "ddL",  "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_tbl">;
 def SVDUPQ_LANE  : SInst<"svdupq_lane[_{d}]", "ddn",  "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_dupq_lane">;
-def SVEXT: SInst<"svext[_{d}]",   "dddi", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_ext", [], [ImmCheck<2, ImmCheckExtract, 1>]>;
 def SVLASTA  : SInst<"svlasta[_{d}]", "sPd",  "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_lasta">;
 def SVLASTB  : SInst<"svlastb[_{d}]", "sPd",  "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_lastb">;
-def SVREV: SInst<"svrev[_{d}]",   "dd",   "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_rev">;
-def SVSEL: SInst<"svsel[_{d}]",   "dPdd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_sel">;
-def SVSPLICE : SInst<"svsplice[_{d}]","dPdd", "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_splice">;
 def SVTBL: SInst<"svtbl[_{d}]",   "ddu",  "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_tbl">;
-def SVTRN1   : SInst<"svtrn1[_{d}]",  "ddd",  "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_trn1">;
-def SVTRN2   : SInst<"svtrn2[_{d}]",  "ddd",  "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_trn2">;
 def SVUNPKHI_S   : SInst<"svunpkhi[_{d}]","dh",   "sil", MergeNone, "aarch64_sve_sunpkhi">;
 def SVUNPKHI_U   : SInst<"svunpkhi[_{d}]","dh",   "UsUiUl",  MergeNone, "aarch64_sve_uunpkhi">;
 def SVUNPKLO_S   : SInst<"svunpklo[_{d}]","dh",   "sil", MergeNone, "aarch64_sve_sunpklo">;
 def SVUNPKLO_U   : SInst<"svunpklo[_{d}]","dh",   "UsUiUl",  MergeNone, "aarch64_sve_uunpklo">;
-def SVUZP1   : SInst<"svuzp1[_{d}]",  "ddd",  "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_uzp1">;
-def SVUZP2   : SInst<"svuzp2[_{d}]",  "ddd",  "csilUcUsUiUlhfd", MergeNone, "aarch64_sve_uzp2">;
-def SVZIP1   

[PATCH] D82182: [AArch64][SVE] Add bfloat16 support to perm and select intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll:809
 
+define  @rev_bf16( %a) {
+; CHECK-LABEL: rev_bf16

sdesmalen wrote:
> Does this test not need the `+bf16` attribute to work? (which implies the 
> patterns are missing the right predicate)
It should do, sorry I missed that. I've tried:
```diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td 
b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 46cca2a..5ab2502 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -1124,10 +1124,13 @@ multiclass sve_int_perm_reverse_z {
   def : SVE_1_Op_Pat(NAME # _S)>;
   def : SVE_1_Op_Pat(NAME # _D)>;

-  def : SVE_1_Op_Pat(NAME # _H)>;
   def : SVE_1_Op_Pat(NAME # _H)>;
   def : SVE_1_Op_Pat(NAME # _S)>;
   def : SVE_1_Op_Pat(NAME # _D)>;
+
+  let Predicates = [HasBF16] in {
+def : SVE_1_Op_Pat(NAME # _H)>;
+  }
 }```

but this still works without `+bf16`. I noticed in your patch D82187 you check 
`Subtarget->hasBF16()` for `MVT::nxv8bf16` at select phase of ISEL, I guess 
it's different here with patterns. I also noticed we add the register class for 
`MVT::nxv8bf16` in AArch64ISelLowering without checking `Subtarget->hasBF16()` 
which I suspect is a bug. This test requires `+bf16` with that fixed but I 
wonder why the predicate isn't being recognised.


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[PATCH] D82429: [sve][acle] Add some C intrinsics for brain float types.

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: 
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2-bfloat.c:4-5
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +bf16 -target-feature +sve 
-fallow-half-arguments-and-returns -fsyntax-only -verify=overload 
-verify-ignore-unexpected=error %s
+

Missing a test that checks for warning/error if `__ARM_FEATURE_SVE_BF16` isn't 
defined, these two run lines are checking that for sve2 where we get an 
implicit declaration warning. See 
https://reviews.llvm.org/D82399#change-gND08cruJN2Z for an example



Comment at: 
clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbx-bfloat.c:4-5
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_SVE_BF16 -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-fsyntax-only -verify -verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE_BF16 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +bf16 -target-feature +sve 
-fallow-half-arguments-and-returns -fsyntax-only -verify=overload 
-verify-ignore-unexpected=error %s
+

same here



Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1024
+
+  def : SVE_2_Op_Pat(NAME 
# _H)>;
 }

pattern needs to be predicated on `+bf16`. I suspect you might hit the same 
issue I did here: https://reviews.llvm.org/D82182#inline-758348

I found setting the predicate in the multiclass like that doesn't work as it's 
nested and there's an outer predicate (where the instruction is defined in 
`AArch64SVEInstrInfo.td`). For splice I found the following works:
```  let Predicates = [HasBF16, HasSVE] in {
def : SVE_3_Op_Pat;
  }```

by defining the pattern guarded on `+bf16` in `AArch64SVEInstrInfo.td` .



Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1058
 
+  def : Pat<(nxv8bf16 (op nxv8bf16:$Op1, nxv8bf16:$Op2, nxv8i16:$Op3)),
+(nxv8bf16 (!cast(NAME # _H) (REG_SEQUENCE ZPR2, 
nxv8bf16:$Op1, zsub0,

as above, needs to be predicated on `+bf16`



Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1060
+(nxv8bf16 (!cast(NAME # _H) (REG_SEQUENCE ZPR2, 
nxv8bf16:$Op1, zsub0,
+
nxv8bf16:$Op2, zsub1),
+ nxv8i16:$Op3))>;

nit: space



Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:1108
+
+  def : SVE_3_Op_Pat(NAME # _H)>;
 }

needs to be predicated on `+bf16`



Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:3698
+  def : SVE_3_Op_Pat(NAME # _H)>;
+  def : SVE_3_Op_Pat(NAME # _H)>;
+  def : SVE_3_Op_Pat(NAME # _S)>;

needs to be predicated on `+bf16`



Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-counting-bits.ll:1
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t

need to add `+bf16` to flags



Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-counting-bits.ll:153-154
+  %out = call  @llvm.aarch64.sve.cnt.nxv8bf16( %a,
+%pg,
+%b)
+  ret  %out

nit: add space for alignment



Comment at: llvm/test/CodeGen/AArch64/sve2-intrinsics-perm-tb.ll:1
 ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
 

need to add +bf16 to flags


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[PATCH] D82429: [sve][acle] Add some C intrinsics for brain float types.

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2-bfloat.c:7
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu 
-target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns 
-fsyntax-only -verify -verify-ignore-unexpected=error 
-verify-ignore-unexpected=note %s
+// R UN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify=overload-bf16 
-verify-ignore-unexpected=error -verify-ignore-unexpected=note %s
+

fpetrogalli wrote:
> I could do with an extra pair of eyes here: I can't figure out why the 
> warning raised by this run is not detected by the `overload-bf16-warning` 
> below... (Same for the same line I have added in the test for tbx).
Ah, it works in the example I linked because `whilerw` / `whilewr` uses the 
scalar `bfloat16_t`, whereas this is using sizeless type which is predicated on 
`-D__ARM_FEATURE_SVE_BF16` so we get:

```error: 'error' diagnostics seen but not expected:
  File 
/home/culrho01/llvm-project/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2-bfloat.c
 Line 18: unknown type name 'svbfloat16_t'; did you mean 'svfloat16_t'?
  File 
/home/culrho01/llvm-project/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2-bfloat.c
 Line 18: unknown type name 'svbfloat16x2_t'; did you mean 'svfloat16x2_t'?```

I'm not sure if/how we can test this for the overloaded form


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[PATCH] D82345: [sve][acle] Implement some of the C intrinsics for brain float.

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

We need to guard the LLVM patterns on the +bf16 feature as we've done in other 
patches




Comment at: clang/include/clang/Basic/arm_sve.td:694
 def SVDUPQ_16 : SInst<"svdupq[_n]_{d}", "d",  "sUsh", MergeNone>;
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16) && 
defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC) " in {
+  def SVDUPQ_BF16 : SInst<"svdupq[_n]_{d}", "d",  "b", MergeNone>;

`__ARM_FEATURE_SVE_BF16` will imply `__ARM_FEATURE_BF16_SCALAR_ARITHMETIC` so 
guarding only on the former should be sufficient. Same applies below



Comment at: clang/include/clang/Basic/arm_sve.td:830
 
+def SVINSR   : SInst<"svinsr[_n_{d}]", "dds",  "csilUcUsUiUlhfd", MergeNone, 
"aarch64_sve_insr">;
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16) && 
defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC) " in {

nit: remove double spaces



Comment at: clang/lib/CodeGen/CGBuiltin.cpp:7745-7746
+
+  case SVETypeFlags::EltTyBFloat16:
+return llvm::ScalableVectorType::get(Builder.getInt1Ty(), 8);
   }

already added in D82399, you should see it when rebasing



Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll:317-318
+  %out = call bfloat @llvm.aarch64.sve.clastb.n.nxv8bf16( %pg,
+bfloat %a,
+ 
%b)
+  ret bfloat %out

nit: alignment



Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll:665
+  %res = call bfloat @llvm.aarch64.sve.lasta.nxv8bf16( %pg,
+%a)
+  ret bfloat %res

nit: alignment



Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-scalar-to-vec.ll:65-66
+  %out = call  @llvm.aarch64.sve.dup.nxv8bf16( %a,
+ %pg,
+bfloat %b)
+  ret  %out

nit: alignment


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[PATCH] D82391: [AArch64][SVE] Add bfloat16 support to svext intrinsic

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 273365.
c-rhodes added a comment.

Changes:

- Guard patterns on `+bf16`.


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Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll


Index: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -516,6 +516,16 @@
   ret  %out
 }
 
+define  @ext_bf16( %a,  %b) #0 {
+; CHECK-LABEL: ext_bf16:
+; CHECK: ext z0.b, z0.b, z1.b, #6
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.ext.nxv8bf16( %a,
+%b,
+   i32 3)
+  ret  %out
+}
+
 define  @ext_f16( %a,  %b) {
 ; CHECK-LABEL: ext_f16:
 ; CHECK: ext z0.b, z0.b, z1.b, #6
@@ -1876,6 +1886,7 @@
 declare  @llvm.aarch64.sve.ext.nxv8i16(, 
, i32)
 declare  @llvm.aarch64.sve.ext.nxv4i32(, 
, i32)
 declare  @llvm.aarch64.sve.ext.nxv2i64(, 
, i32)
+declare  @llvm.aarch64.sve.ext.nxv8bf16(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv8f16(, 
, i32)
 declare  @llvm.aarch64.sve.ext.nxv4f32(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv2f64(, , i32)
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1454,7 +1454,6 @@
 
 def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
-def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
@@ -1473,6 +1472,14 @@
 def : Pat<(nxv2f64 (bitconvert (nxv2i64 ZPR:$src))), (nxv2f64 ZPR:$src)>;
 def : Pat<(nxv2f64 (bitconvert (nxv8f16 ZPR:$src))), (nxv2f64 ZPR:$src)>;
 def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>;
+
+  }
+
+  let Predicates = [IsLE, HasBF16] in {
+def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
+
+def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
   }
 
   def : Pat<(nxv16i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS 
PPR:$src, PPR)>;
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
@@ -0,0 +1,26 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-o - %s >/dev/null 2>%t
+// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify 
-verify-ignore-unexpected=error -verify-ignore-unexpected=note %s
+
+// If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README 
for instructions on how to resolve it.
+// ASM-NOT: warning
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svbfloat16_t test_svext_bf16(svbfloat16_t op1, svbfloat16_t op2)
+{
+  // CHECK-LABEL: test_svext_bf16
+  // CHECK: %[[INTRINSIC:.*]] = call  
@llvm.aarch64.sve.ext.nxv8bf16( %op1,  %op2, i32 127)
+  // CHECK: ret  %[[INTRINSIC]]
+  // expected-warning@+1 {{implicit dec

[PATCH] D82429: [sve][acle] Add some C intrinsics for brain float types.

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes accepted this revision.
c-rhodes added inline comments.
This revision is now accepted and ready to land.



Comment at: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2-bfloat.c:7
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu 
-target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns 
-fsyntax-only -verify -verify-ignore-unexpected=error 
-verify-ignore-unexpected=note %s
+// R UN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify=overload-bf16 
-verify-ignore-unexpected=error -verify-ignore-unexpected=note %s
+

c-rhodes wrote:
> fpetrogalli wrote:
> > I could do with an extra pair of eyes here: I can't figure out why the 
> > warning raised by this run is not detected by the `overload-bf16-warning` 
> > below... (Same for the same line I have added in the test for tbx).
> Ah, it works in the example I linked because `whilerw` / `whilewr` uses the 
> scalar `bfloat16_t`, whereas this is using sizeless type which is predicated 
> on `-D__ARM_FEATURE_SVE_BF16` so we get:
> 
> ```error: 'error' diagnostics seen but not expected:
>   File 
> /home/culrho01/llvm-project/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2-bfloat.c
>  Line 18: unknown type name 'svbfloat16_t'; did you mean 'svfloat16_t'?
>   File 
> /home/culrho01/llvm-project/clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_tbl2-bfloat.c
>  Line 18: unknown type name 'svbfloat16x2_t'; did you mean 'svfloat16x2_t'?```
> 
> I'm not sure if/how we can test this for the overloaded form
I'm not sure if what I suggested makes sense - trying to do what we've done in 
the sve2 acle tests where we expect an implicit declaration warning for 
overloaded/non-overloaded intrinsics if the sve2 feature isn't enabled. I guess 
it's different for BF16 as the types are guarded on the feature macro in the 
ACLE, for whatever reason we get the same warning for the non-overloaded 
intrinsics but an error for the overloaded ones. I think we can be pretty 
confident `+bf16` is required as the test will fail otherwise, but it's tricky 
trying to isolate an error implying the macro is missing on the intrinsic. FWIW 
we don't test this for SVE either, I think we can skip this test for the 
overloaded form, may as well keep the non-overloaded one in if it works.


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[PATCH] D82578: [AArch64][SVE2] Guard while intrinsics on scalar bfloat feature macro

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, fpetrogalli, kmclaughlin.
Herald added subscribers: danielkiss, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a reviewer: efriedma.
Herald added a project: clang.

`svwhilerw_bf16` and `svwhilewr_bf16` intrinsics use the scalar `bfloat16_t`
type which is predicated on `__ARM_FEATURE_BF16_SCALAR_ARITHMETIC`. This
patch changes the feature guard from `__ARM_FEATURE_SVE_BF16` to the
scalar bfloat feature macro.

The verify tests for `+bf16` are also removed in this patch. The purpose
of these checks was to match the SVE2 ACLE tests that look for an
implicit declaration warning if the feature isn't set. They worked when
the intrinsics were guarded on `__ARM_FEATURE_SVE_BF16` as the `bfloat16_t`
was guarded on a different macro, but with both the type and intrinsic
guarded on the same macro an earlier error is triggered in the ACLE
regarding the type and we don't get a warning as we do for SVE2.


Repository:
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Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilerw-bfloat.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c


Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
@@ -1,18 +1,7 @@
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple 
aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
-
-// Test expected warnings for implicit declaration when +sve2 is missing
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify 
-verify-ignore-unexpected=error %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
-
-// Test expected warnings for implicit declaration when +bf16 is missing
-// NOTE: +bf16 doesn't currently imply __ARM_FEATURE_SVE_BF16, once the
-// implementation is complete it will, at which point -target-feature +bf16
-// should be removed.
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu 
-target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns 
-fsyntax-only -verify -verify-ignore-unexpected=error %s
-
-// Test expected ambiguous call error for overloaded form when +bf16 is missing
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify=overload-bf16 
-verify-ignore-unexpected=note %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu 
-target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify 
-verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only 
-verify=overload -verify-ignore-unexpected=error %s
 
 #include 
 
@@ -29,8 +18,7 @@
   // CHECK: %[[INTRINSIC:.*]] = call  
@llvm.aarch64.sve.whilewr.h.nxv8i1.p0bf16(bfloat* %op1, bfloat* %op2)
   // CHECK: %[[IN

[PATCH] D82345: [sve][acle] Implement some of the C intrinsics for brain float.

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

@fpetrogalli thanks for updating! I have a few more comments, sorry I missed a 
few things yesterday




Comment at: clang/include/clang/Basic/arm_sve.td:725-727
+  def NAME   : SInst;
+  let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16)" in {
+def _BF16: SInst;

nit: could you fix the spacing? I don't think it's worth trying to keep the two 
defs inline, single spaces everywhere would do



Comment at: clang/include/clang/Basic/arm_sve.td:1198
 def SVDUPQ_LANE  : SInst<"svdupq_lane[_{d}]", "ddn",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_dupq_lane">;
+let ArchGuard = "defined(__ARM_FEATURE_SVE_BF16) && 
defined(__ARM_FEATURE_BF16_SCALAR_ARITHMETIC) " in {
+  def SVDUPQ_LANE_BF16  : SInst<"svdupq_lane[_{d}]", "ddn",  "b", MergeNone, 
"aarch64_sve_dupq_lane">;

`__ARM_FEATURE_BF16_SCALAR_ARITHMETIC` can be removed



Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:426-427
+  let Predicates = [HasSVE, HasBF16] in {
+def : Pat<(nxv8bf16 (AArch64dup (bf16 FPR16:$src))),
+  (DUP_ZZI_H (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), 0)>;
+  }

I think we're missing a test for this pattern in 
`llvm/test/CodeGen/AArch64/sve-vector-splat.ll`? Same applies to dup 0 patterns 
below.



Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:431-436
+  def : Pat<(nxv8f16  (AArch64dup (f16 fpimm0))),  (DUP_ZI_H 0, 0)>;
+  def : Pat<(nxv4f16  (AArch64dup (f16 fpimm0))),  (DUP_ZI_H 0, 0)>;
+  def : Pat<(nxv2f16  (AArch64dup (f16 fpimm0))),  (DUP_ZI_H 0, 0)>;
+  def : Pat<(nxv4f32  (AArch64dup (f32 fpimm0))),  (DUP_ZI_S 0, 0)>;
+  def : Pat<(nxv2f32  (AArch64dup (f32 fpimm0))),  (DUP_ZI_S 0, 0)>;
+  def : Pat<(nxv2f64  (AArch64dup (f64 fpimm0))),  (DUP_ZI_D 0, 0)>;

formatting changes can be reverted



Comment at: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td:1496-1498
+def : Pat<(nxv2i64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2i64 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
+def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;

missing tests in `llvm/test/CodeGen/AArch64/sve-bitcast.ll`


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[PATCH] D82578: [AArch64][SVE2] Guard while intrinsics on scalar bfloat feature macro

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd45cf9105b5a: [AArch64][SVE2] Guard while intrinsics on 
scalar bfloat feature macro (authored by c-rhodes).

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Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilerw-bfloat.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c


Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
===
--- clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
+++ clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilewr-bfloat.c
@@ -1,18 +1,7 @@
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 -triple 
aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -D__ARM_FEATURE_SVE_BF16 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve2 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
-
-// Test expected warnings for implicit declaration when +sve2 is missing
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only -verify 
-verify-ignore-unexpected=error %s
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-fsyntax-only -verify=overload -verify-ignore-unexpected=error %s
-
-// Test expected warnings for implicit declaration when +bf16 is missing
-// NOTE: +bf16 doesn't currently imply __ARM_FEATURE_SVE_BF16, once the
-// implementation is complete it will, at which point -target-feature +bf16
-// should be removed.
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu 
-target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns 
-fsyntax-only -verify -verify-ignore-unexpected=error %s
-
-// Test expected ambiguous call error for overloaded form when +bf16 is missing
-// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify=overload-bf16 
-verify-ignore-unexpected=note %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -triple aarch64-none-linux-gnu 
-target-feature +sve2 -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_SVE2 
-D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC -DSVE_OVERLOADED_FORMS -triple 
aarch64-none-linux-gnu -target-feature +sve2 -target-feature +bf16 
-fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | 
FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify 
-verify-ignore-unexpected=error %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -fsyntax-only 
-verify=overload -verify-ignore-unexpected=error %s
 
 #include 
 
@@ -29,8 +18,7 @@
   // CHECK: %[[INTRINSIC:.*]] = call  
@llvm.aarch64.sve.whilewr.h.nxv8i1.p0bf16(bfloat* %op1, bfloat* %op2)
   // CHECK: %[[INTRINSIC_REINT:.*]] = call  
@llvm.aarch64.sve.convert.to.svbool.nxv8i1( %[[INTRINSIC]])
   // CHECK: ret  %[[INTRINSIC_REINT]]
-  // overload-warning@+3 {{implicit declaration of function 'svwhilewr'}}
-  // expected-warning@+2 {{implicit declaration of function 'svwhilewr_bf16'}}
-  // overload-bf16-error@+1 {{call to 'svwhilewr' is ambiguous}}
+  // overload-warning@+2 {{implicit declaration of function 'svwhilewr'}}
+  // expected-warning@+1 {{implicit declaration of function 'svwhilewr_bf16'}}
   return SVE_ACLE_FUNC(svwhilewr,_bf16,,)(op1, op2);
 }
Index: clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_whilerw-bfloat.c
===
--- clang/test/CodeGen/aarch

[PATCH] D82391: [AArch64][SVE] Add bfloat16 support to svext intrinsic

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 273685.
c-rhodes added a comment.

Changes:

- Add tests for bfloat bitcast patterns.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82391/new/

https://reviews.llvm.org/D82391

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-bitcast.ll
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -516,6 +516,16 @@
   ret  %out
 }
 
+define  @ext_bf16( %a,  %b) #0 {
+; CHECK-LABEL: ext_bf16:
+; CHECK: ext z0.b, z0.b, z1.b, #6
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.ext.nxv8bf16( %a,
+%b,
+   i32 3)
+  ret  %out
+}
+
 define  @ext_f16( %a,  %b) {
 ; CHECK-LABEL: ext_f16:
 ; CHECK: ext z0.b, z0.b, z1.b, #6
@@ -1885,6 +1895,7 @@
 declare  @llvm.aarch64.sve.ext.nxv8i16(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv4i32(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv2i64(, , i32)
+declare  @llvm.aarch64.sve.ext.nxv8bf16(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv8f16(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv4f32(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv2f64(, , i32)
Index: llvm/test/CodeGen/AArch64/sve-bitcast.ll
===
--- llvm/test/CodeGen/AArch64/sve-bitcast.ll
+++ llvm/test/CodeGen/AArch64/sve-bitcast.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
-; RUN: not --crash llc -mtriple=aarch64_be -mattr=+sve < %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+bf16 < %s 2>%t | FileCheck %s
+; RUN: not --crash llc -mtriple=aarch64_be -mattr=+sve,+bf16 < %s
 ; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
 
 ; WARN-NOT: warning
@@ -53,6 +53,14 @@
   ret  %bc
 }
 
+define  @bitcast_bfloat_to_i8( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i8:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:ret
+  %bc = bitcast  %v to 
+  ret  %bc
+}
+
 define  @bitcast_i8_to_i16( %v) {
 ; CHECK-LABEL: bitcast_i8_to_i16:
 ; CHECK:   // %bb.0:
@@ -101,6 +109,14 @@
   ret  %bc
 }
 
+define  @bitcast_bfloat_to_i16( %v) {
+; CHECK-LABEL: bitcast_bfloat_to_i16:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:ret
+  %bc = bitcast  %v to 
+  ret  %bc
+}
+
 define  @bitcast_i8_to_i32( %v) {
 ; CHECK-LABEL: bitcast_i8_to_i32:
 ; CHECK:   // %bb.0:
@@ -340,3 +356,19 @@
   %bc = bitcast  %v to 
   ret  %bc
 }
+
+define  @bitcast_i8_to_bfloat( %v) {
+; CHECK-LABEL: bitcast_i8_to_bfloat:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:ret
+  %bc = bitcast  %v to 
+  ret  %bc
+}
+
+define  @bitcast_i16_to_bfloat( %v) {
+; CHECK-LABEL: bitcast_i16_to_bfloat:
+; CHECK:   // %bb.0:
+; CHECK-NEXT:ret
+  %bc = bitcast  %v to 
+  ret  %bc
+}
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1444,7 +1444,6 @@
 def : Pat<(nxv8i16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 def : Pat<(nxv8i16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 def : Pat<(nxv8i16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8i16 ZPR:$src)>;
-def : Pat<(nxv8i16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 def : Pat<(nxv8i16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 def : Pat<(nxv8i16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 
@@ -1464,7 +1463,6 @@
 
 def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>;
-def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>;
 def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>;
@@ -1483,6 +1481,16 @@
 def : Pat<(nxv2f64 (bitconvert (nxv2i64 ZPR:$src))), (nxv2f64 ZPR:$src)>;
 def : Pat<(nxv2f64 (bitconvert (nxv8f16 ZPR:$src))), (nxv2f64 ZPR:$src)>;
 def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>;
+
+  }
+
+  let Predicates = [IsLE, HasBF16] in {
+def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>;
+
+def : Pat<(nxv8i16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8i16 ZPR:$src)>;
+
+def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZP

[PATCH] D82665: [AArch64][SVE] Add bfloat16 to outstanding tuple vector intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, kmclaughlin, fpetrogalli.
Herald added subscribers: danielkiss, psnobl, rkruppe, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added projects: clang, LLVM.

- svget2/3/4
- svset2/3/4
- svcreate2/3/4
- svundef/2/3/4


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82665

Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4-bfloat.c
  llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple aarch64 -mattr=+sve -asm-verbose=1 < %s | FileCheck %s
+; RUN: llc -mtriple aarch64 -mattr=+sve,+bf16 -asm-verbose=1 < %s | FileCheck %s
 
 ;
 ; SVCREATE2 (i8)
@@ -94,6 +94,37 @@
 }
 
 ;
+; SVCREATE2 (bfloat)
+;
+
+define  @test_svcreate2_bf16_vec0(i1 %p,  %z0,  %z1) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate2_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16( %z0,  %z1)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate2_bf16_vec1(i1 %p,  %z0,  %z1) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate2_bf16_vec1:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16( %z0,  %z1)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16( %tuple, i32 1)
+  ret  %extract
+}
+
+;
 ; SVCREATE2 (i32)
 ;
 
@@ -278,6 +309,7 @@
   %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8i16.nxv24i16( %tuple, i32 2)
   ret  %extract
 }
+
 ;
 ; SVCREATE3 (half)
 ;
@@ -309,6 +341,36 @@
   ret  %extract
 }
 
+;
+; SVCREATE3 (bfloat)
+;
+
+define  @test_svcreate3_bf16_vec0(i1 %p,  %z0,  %z1,  %z2) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate3_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16( %z0,  %z1,  %z2)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate3_bf16_vec2(i1 %p,  %z0,  %z1,  %z2) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate3_bf16_vec2:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z2.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16( %z0,  %z1,  %z2)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16( %tuple, i32 2)
+  ret  %extract
+}
 
 ;
 ; SVCREATE3 (i32)
@@ -528,6 +590,37 @@
 }
 
 ;
+; SVCREATE4 (bfloat)
+;
+
+define  @test_svcreate4_bf16_vec0(i1 %p,  %z0,  %z1,  %z2,  %z3) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate4_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16( %z0,  %z1,  %z2,  %z3)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate4_bf16_vec3(i1 %p,  %z0,  %z1,  %z2,  %z3) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate4_bf16_vec3:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z3.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16( %z0,  %z1,  %z2,  %z3)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16( %tuple, i32 3)
+  ret  %extract
+}
+
+;
 ; SVCREATE4 (i32)
 ;
 
@@ -651,11 +744,12 @@
   ret  %extract
 }
 
-attributes #0 = { nounwind "target-features"="+sve" }
+attributes #0 = { nounwind "target-featur

[PATCH] D82668: [AArch64][SVE] clang: Add missing svbfloat16_t tests

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, kmclaughlin, fpetrogalli.
Herald added subscribers: danielkiss, psnobl, rkruppe, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: clang.

Patch adds tests for mangling of svbfloat16_t and several other type
related tests.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82668

Files:
  clang/test/CodeGen/aarch64-sve.c
  clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
  clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
  clang/test/CodeGenObjC/aarch64-sve-types.m
  clang/test/PCH/aarch64-sve-types.c
  clang/test/Sema/aarch64-sve-types.c
  clang/test/SemaObjC/aarch64-sve-types.m

Index: clang/test/SemaObjC/aarch64-sve-types.m
===
--- clang/test/SemaObjC/aarch64-sve-types.m
+++ clang/test/SemaObjC/aarch64-sve-types.m
@@ -18,5 +18,7 @@
 @property(nullable) __SVFloat32_t f32; // expected-error {{cannot be applied to non-pointer type}}
 @property(nullable) __SVFloat64_t f64; // expected-error {{cannot be applied to non-pointer type}}
 
+@property(nullable) __SVBFloat16_t bf16; // expected-error {{cannot be applied to non-pointer type}}
+
 @property(nullable) __SVBool_t b8; // expected-error {{cannot be applied to non-pointer type}}
 @end
Index: clang/test/Sema/aarch64-sve-types.c
===
--- clang/test/Sema/aarch64-sve-types.c
+++ clang/test/Sema/aarch64-sve-types.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 %s -triple aarch64-none-linux-gnu -target-feature +sve -fsyntax-only -verify
+// RUN: %clang_cc1 %s -triple aarch64-none-linux-gnu -target-feature +sve,+bf16 -fsyntax-only -verify
 
 void f() {
   int size_s8[sizeof(__SVInt8_t) == 0 ? 1 : -1];// expected-error {{invalid application of 'sizeof' to sizeless type '__SVInt8_t'}}
@@ -34,6 +34,9 @@
   int size_f64[sizeof(__SVFloat64_t) == 0 ? 1 : -1];// expected-error {{invalid application of 'sizeof' to sizeless type '__SVFloat64_t'}}
   int align_f64[__alignof__(__SVFloat64_t) == 16 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVFloat64_t'}}
 
+  int size_bf16[sizeof(__SVBFloat16_t) == 0 ? 1 : -1];// expected-error {{invalid application of 'sizeof' to sizeless type '__SVBFloat16_t'}}
+  int align_bf16[__alignof__(__SVBFloat16_t) == 16 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVBFloat16_t'}}
+
   int size_b8[sizeof(__SVBool_t) == 0 ? 1 : -1];   // expected-error {{invalid application of 'sizeof' to sizeless type '__SVBool_t'}}
   int align_b8[__alignof__(__SVBool_t) == 2 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVBool_t'}}
 }
Index: clang/test/PCH/aarch64-sve-types.c
===
--- clang/test/PCH/aarch64-sve-types.c
+++ clang/test/PCH/aarch64-sve-types.c
@@ -18,4 +18,6 @@
 __SVFloat32_t *f32;
 __SVFloat64_t *f64;
 
+__SVBFloat16_t *bf16;
+
 __SVBool_t *b8;
Index: clang/test/CodeGenObjC/aarch64-sve-types.m
===
--- clang/test/CodeGenObjC/aarch64-sve-types.m
+++ clang/test/CodeGenObjC/aarch64-sve-types.m
@@ -1,7 +1,7 @@
 // RUN: not %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
 // RUN:   2>&1 | FileCheck %s
 // RUN: not %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
-// RUN:   -target-feature +sve 2>&1 | FileCheck %s
+// RUN:   -target-feature +sve,+bf16 2>&1 | FileCheck %s
 
 // CHECK: error: cannot yet @encode type __SVInt8_t
 const char s8[] = @encode(__SVInt8_t);
@@ -28,5 +28,8 @@
 // CHECK: error: cannot yet @encode type __SVFloat64_t
 const char f64[] = @encode(__SVFloat64_t);
 
+// CHECK: error: cannot yet @encode type __SVBFloat16_t
+const char bf16[] = @encode(__SVBFloat16_t);
+
 // CHECK: error: cannot yet @encode type __SVBool_t
 const char b8[] = @encode(__SVBool_t);
Index: clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
===
--- clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
+++ clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
@@ -1,7 +1,7 @@
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
 // RUN:   | FileCheck %s
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
-// RUN:   -target-feature +sve | FileCheck %s
+// RUN:   -target-feature +sve,+bf16 | FileCheck %s
 
 namespace std { class type_info; };
 
@@ -19,6 +19,8 @@
 auto &f32 = typeid(__SVFloat32_t);
 auto &f64 = typeid(__SVFloat64_t);
 
+auto &bf16 = typeid(__SVBFloat16_t);
+
 auto &b8 = typeid(__SVBool_t);
 
 // CHECK-DAG: @_ZTSu10__SVInt8_t = {{.*}} c"u10__SVInt8_t\00"
@@ -53,6 +55,9 @@
 
 // CHECK-DAG: @_ZTSu13__SVFloat64_t = {{.*}} c"u13__SVFloat64_t\00"
 // CHECK-DAG: @_ZTIu13__SVFloat64_t = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, 

[PATCH] D82345: [sve][acle] Implement some of the C intrinsics for brain float.

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

@fpetrogalli thanks for updating, LGTM!


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[PATCH] D82391: [AArch64][SVE] Add bfloat16 support to svext intrinsic

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGd5fc592b7c26: [AArch64][SVE] Add bfloat16 support to svext 
intrinsic (authored by c-rhodes).

Changed prior to commit:
  https://reviews.llvm.org/D82391?vs=273685&id=274052#toc

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Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll


Index: llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
@@ -516,6 +516,16 @@
   ret  %out
 }
 
+define  @ext_bf16( %a,  %b) #0 {
+; CHECK-LABEL: ext_bf16:
+; CHECK: ext z0.b, z0.b, z1.b, #6
+; CHECK-NEXT: ret
+  %out = call  @llvm.aarch64.sve.ext.nxv8bf16( %a,
+%b,
+   i32 3)
+  ret  %out
+}
+
 define  @ext_f16( %a,  %b) {
 ; CHECK-LABEL: ext_f16:
 ; CHECK: ext z0.b, z0.b, z1.b, #6
@@ -1885,6 +1895,7 @@
 declare  @llvm.aarch64.sve.ext.nxv8i16(, 
, i32)
 declare  @llvm.aarch64.sve.ext.nxv4i32(, 
, i32)
 declare  @llvm.aarch64.sve.ext.nxv2i64(, 
, i32)
+declare  @llvm.aarch64.sve.ext.nxv8bf16(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv8f16(, 
, i32)
 declare  @llvm.aarch64.sve.ext.nxv4f32(, , i32)
 declare  @llvm.aarch64.sve.ext.nxv2f64(, , i32)
Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1446,7 +1446,6 @@
 def : Pat<(nxv8i16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 def : Pat<(nxv8i16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 def : Pat<(nxv8i16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8i16 ZPR:$src)>;
-def : Pat<(nxv8i16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 def : Pat<(nxv8i16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 def : Pat<(nxv8i16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8i16 ZPR:$src)>;
 
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
===
--- /dev/null
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_ext-bfloat.c
@@ -0,0 +1,26 @@
+// REQUIRES: aarch64-registered-target
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu 
-target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns 
-S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-D__ARM_FEATURE_SVE_BF16 -triple aarch64-none-linux-gnu -target-feature +sve 
-target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall 
-o - %s >/dev/null 2>%t
+// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t
+// RUN: %clang_cc1 -D__ARM_FEATURE_SVE -D__ARM_FEATURE_BF16_SCALAR_ARITHMETIC 
-triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 
-fallow-half-arguments-and-returns -fsyntax-only -verify 
-verify-ignore-unexpected=error -verify-ignore-unexpected=note %s
+
+// If this check fails please read test/CodeGen/aarch64-sve-intrinsics/README 
for instructions on how to resolve it.
+// ASM-NOT: warning
+#include 
+
+#ifdef SVE_OVERLOADED_FORMS
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else
+#define SVE_ACLE_FUNC(A1,A2,A3,A4) A1##A2##A3##A4
+#endif
+
+svbfloat16_t test_svext_bf16(svbfloat16_t op1, svbfloat16_t op2)
+{
+  // CHECK-LABEL: test_svext_bf16
+  // CHECK: %[[INTRINSIC:.*]] = call  
@llvm.aarch64.sve.ext.nxv8bf16( %op1,  %op2, i32 127)
+  // CHECK: ret  %[[INTRINSIC]]
+  // expected-warning@+1 {{implicit declaration of function 'svext_bf16'}}
+  return SVE_ACLE_FUNC(svext,_bf16,,)(op1, op2, 127);
+}
Index: clang/include/clang/Basic/arm_sve.td
===
--- clang/include/clang/Basic/arm_sve.td
+++ clang/include/clang/Basic/arm_sve.td
@@ -1208,6 +1208,7 @@
 def SVZIP2   : SInst<"svzip2[_{d}]",  "ddd",  "csilUcUsUiUlhfd", 
MergeNone, "aarch64_sve_zip2">;
 
 let ArchGuard = "defined(__ARM_FEATURE_SVE_B

[PATCH] D82665: [AArch64][SVE] Add bfloat16 to outstanding tuple vector intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: 
clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c:9
+// A simple used,unused... macro, long enough to represent any SVE builtin.
+#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
+#else

fpetrogalli wrote:
> Nit: these are all new files, so you can safely use clang-format on them, as 
> they will not modify the formatting of pre-existing tests. I know this is not 
> what we have done for most of the files in the ACLE tests, but it makes life 
> so much easier to just run a `git clang-format HEAD^` on a patch and kinda 
> forgetting about formatting! Since they are new files, they will not generate 
> conflicts with anything we might have downstream. FWIW, this is my personal 
> preference, so if you prefer to adhere with the manual formatting of other 
> files, I am happy with it.
I agree it's nice to be able to use clang-format and not think about it but in 
my opinion it's more important to be consistent in formatting across the ACLE 
tests. I'd prefer a follow-up patch once the ACLE is complete containing the 
diff produced from running clang-format on 
`clang/test/CodeGen/aarch64-sve-intrinsics` / 
`clang/test/CodeGen/aarch64-sve2-intrinsics`.



Comment at: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c:20
+  // expected-warning@+1 {{implicit declaration of function 'svget2_bf16'}}
+  return SVE_ACLE_FUNC(svget2,_bf16,,)(tuple, 0);
+}

fpetrogalli wrote:
> Shouldn't we test also values other then zero? 0,1 for get2, 0,1,2 for 
> get3... 
> Shouldn't we test also values other then zero? 0,1 for get2, 0,1,2 for get3...

We have coverage for all valid indexes in the test suite for these intrinsics, 
I was about to say it's the same code path regardless of type, which it is on 
the LLVM side but the intrinsic defs in clang are split so I guess that isn't 
covered. I'll add extra tests.


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[PATCH] D82668: [AArch64][SVE] clang: Add missing svbfloat16_t tests

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp:4
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
-// RUN:   -target-feature +sve | FileCheck %s
+// RUN:   -target-feature +sve,+bf16 | FileCheck %s
 

fpetrogalli wrote:
> I wonder if we should keep the bf16 tests separate, as +bf16 is not needed to 
> generate any of the other SVE types. I don't have strong opinions here, but 
> it seems a better thing to do to isolate the bfloat tests in SVE in a 
> separate file. What do you think, @c-rhodes?
> I wonder if we should keep the bf16 tests separate, as +bf16 is not needed to 
> generate any of the other SVE types. I don't have strong opinions here, but 
> it seems a better thing to do to isolate the bfloat tests in SVE in a 
> separate file. What do you think, @c-rhodes?

I don't think either `+sve` or `+bf16` are actually required in any of these 
tests since they're directly using the ACLE types and not including 
`arm_sve.h`. Where I've added `+bf16` I've done so to be consistent, but notice 
there's some tests with no target feature and some that have run lines covering 
both. I'd prefer to keep to tests together.


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[PATCH] D82665: [AArch64][SVE] Add bfloat16 to outstanding tuple vector intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 274081.
c-rhodes added a comment.

Changes:

- Cover all indexes in get/set ACLE tests


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Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4-bfloat.c
  llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple aarch64 -mattr=+sve -asm-verbose=1 < %s | FileCheck %s
+; RUN: llc -mtriple aarch64 -mattr=+sve,+bf16 -asm-verbose=1 < %s | FileCheck %s
 
 ;
 ; SVCREATE2 (i8)
@@ -94,6 +94,37 @@
 }
 
 ;
+; SVCREATE2 (bfloat)
+;
+
+define  @test_svcreate2_bf16_vec0(i1 %p,  %z0,  %z1) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate2_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16( %z0,  %z1)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate2_bf16_vec1(i1 %p,  %z0,  %z1) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate2_bf16_vec1:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16( %z0,  %z1)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16( %tuple, i32 1)
+  ret  %extract
+}
+
+;
 ; SVCREATE2 (i32)
 ;
 
@@ -278,6 +309,7 @@
   %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8i16.nxv24i16( %tuple, i32 2)
   ret  %extract
 }
+
 ;
 ; SVCREATE3 (half)
 ;
@@ -309,6 +341,36 @@
   ret  %extract
 }
 
+;
+; SVCREATE3 (bfloat)
+;
+
+define  @test_svcreate3_bf16_vec0(i1 %p,  %z0,  %z1,  %z2) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate3_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16( %z0,  %z1,  %z2)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate3_bf16_vec2(i1 %p,  %z0,  %z1,  %z2) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate3_bf16_vec2:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z2.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16( %z0,  %z1,  %z2)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16( %tuple, i32 2)
+  ret  %extract
+}
 
 ;
 ; SVCREATE3 (i32)
@@ -528,6 +590,37 @@
 }
 
 ;
+; SVCREATE4 (bfloat)
+;
+
+define  @test_svcreate4_bf16_vec0(i1 %p,  %z0,  %z1,  %z2,  %z3) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate4_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16( %z0,  %z1,  %z2,  %z3)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate4_bf16_vec3(i1 %p,  %z0,  %z1,  %z2,  %z3) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate4_bf16_vec3:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z3.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16( %z0,  %z1,  %z2,  %z3)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16( %tuple, i32 3)
+  ret  %extract
+}
+
+;
 ; SVCREATE4 (i32)
 ;
 
@@ -651,11 +744,12 @@
   ret  %extract
 }
 
-attributes #0 = { nounwind "target-features"="+sve" }
+attributes #0 = { nounwind "target-features"="+sve,+bf16" }
 
 declare   @llvm.aarch64.sve.tuple.create2.nxv4f64.nxv2f64(, )
 declare   @llvm.aarch64.sve.tuple.create2.nxv8f32.nxv4f32(, )
 decl

[PATCH] D82665: [AArch64][SVE] Add bfloat16 to outstanding tuple vector intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll:100
+
+define  @test_svcreate2_bf16_vec0(i1 %p,  %z0,  %z1) local_unnamed_addr #0 {
+; CHECK-LABEL: test_svcreate2_bf16_vec0:

fpetrogalli wrote:
> nit: remove `local_unnamed_addr ` from all tests you have added.
I copied these from the existing tests, not sure why we used 
`local_unnamed_addr` in the first place. I'll create a patch to remove it



Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll:109
+L2:
+  %extract = tail call  
@llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16( %tuple, 
i32 0)
+  ret  %extract

fpetrogalli wrote:
> out of curiosity why not test the create intrinsic directly?
to test we can copy tuple types between basic blocks


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[PATCH] D82665: [AArch64][SVE] Add bfloat16 to outstanding tuple vector intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 274138.
c-rhodes added a comment.

Changes:

- Use function attribute for `+bf16` target feature.


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Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4-bfloat.c
  llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
@@ -94,6 +94,37 @@
 }
 
 ;
+; SVCREATE2 (bfloat)
+;
+
+define  @test_svcreate2_bf16_vec0(i1 %p,  %z0,  %z1) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate2_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16( %z0,  %z1)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate2_bf16_vec1(i1 %p,  %z0,  %z1) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate2_bf16_vec1:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16( %z0,  %z1)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16( %tuple, i32 1)
+  ret  %extract
+}
+
+;
 ; SVCREATE2 (i32)
 ;
 
@@ -278,6 +309,7 @@
   %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8i16.nxv24i16( %tuple, i32 2)
   ret  %extract
 }
+
 ;
 ; SVCREATE3 (half)
 ;
@@ -309,6 +341,36 @@
   ret  %extract
 }
 
+;
+; SVCREATE3 (bfloat)
+;
+
+define  @test_svcreate3_bf16_vec0(i1 %p,  %z0,  %z1,  %z2) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate3_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16( %z0,  %z1,  %z2)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate3_bf16_vec2(i1 %p,  %z0,  %z1,  %z2) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate3_bf16_vec2:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z2.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16( %z0,  %z1,  %z2)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16( %tuple, i32 2)
+  ret  %extract
+}
 
 ;
 ; SVCREATE3 (i32)
@@ -528,6 +590,37 @@
 }
 
 ;
+; SVCREATE4 (bfloat)
+;
+
+define  @test_svcreate4_bf16_vec0(i1 %p,  %z0,  %z1,  %z2,  %z3) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate4_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16( %z0,  %z1,  %z2,  %z3)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate4_bf16_vec3(i1 %p,  %z0,  %z1,  %z2,  %z3) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate4_bf16_vec3:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z3.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16( %z0,  %z1,  %z2,  %z3)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16( %tuple, i32 3)
+  ret  %extract
+}
+
+;
 ; SVCREATE4 (i32)
 ;
 
@@ -652,10 +745,13 @@
 }
 
 attributes #0 = { nounwind "target-features"="+sve" }
+; +bf16 is required for the bfloat version.
+attributes #1 = { nounwind "target-features"="+sve,+bf16" }
 
 declare   @llvm.aarch64.sve.tuple.create2.nxv4f64.nxv2f64(, )
 declare   @llvm.aarch64.sve.tuple.create2.nxv8f32.nxv4f32(, )
 declare   @llvm.aarch64.sve.tuple.create2.nxv16f16.nxv8f16(, )
+declare   @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16(, )
 declare   @llvm.aarch64.sve.tupl

[PATCH] D82668: [AArch64][SVE] clang: Add missing svbfloat16_t tests

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1ef75f53e9e6: [AArch64][SVE] clang: Add missing svbfloat16_t 
tests (authored by c-rhodes).

Repository:
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Files:
  clang/test/CodeGen/aarch64-sve.c
  clang/test/CodeGenCXX/aarch64-mangle-sve-vectors.cpp
  clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
  clang/test/CodeGenObjC/aarch64-sve-types.m
  clang/test/PCH/aarch64-sve-types.c
  clang/test/Sema/aarch64-sve-types.c
  clang/test/SemaObjC/aarch64-sve-types.m

Index: clang/test/SemaObjC/aarch64-sve-types.m
===
--- clang/test/SemaObjC/aarch64-sve-types.m
+++ clang/test/SemaObjC/aarch64-sve-types.m
@@ -18,5 +18,7 @@
 @property(nullable) __SVFloat32_t f32; // expected-error {{cannot be applied to non-pointer type}}
 @property(nullable) __SVFloat64_t f64; // expected-error {{cannot be applied to non-pointer type}}
 
+@property(nullable) __SVBFloat16_t bf16; // expected-error {{cannot be applied to non-pointer type}}
+
 @property(nullable) __SVBool_t b8; // expected-error {{cannot be applied to non-pointer type}}
 @end
Index: clang/test/Sema/aarch64-sve-types.c
===
--- clang/test/Sema/aarch64-sve-types.c
+++ clang/test/Sema/aarch64-sve-types.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 %s -triple aarch64-none-linux-gnu -target-feature +sve -fsyntax-only -verify
+// RUN: %clang_cc1 %s -triple aarch64-none-linux-gnu -target-feature +sve,+bf16 -fsyntax-only -verify
 
 void f() {
   int size_s8[sizeof(__SVInt8_t) == 0 ? 1 : -1];// expected-error {{invalid application of 'sizeof' to sizeless type '__SVInt8_t'}}
@@ -34,6 +34,9 @@
   int size_f64[sizeof(__SVFloat64_t) == 0 ? 1 : -1];// expected-error {{invalid application of 'sizeof' to sizeless type '__SVFloat64_t'}}
   int align_f64[__alignof__(__SVFloat64_t) == 16 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVFloat64_t'}}
 
+  int size_bf16[sizeof(__SVBFloat16_t) == 0 ? 1 : -1];// expected-error {{invalid application of 'sizeof' to sizeless type '__SVBFloat16_t'}}
+  int align_bf16[__alignof__(__SVBFloat16_t) == 16 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVBFloat16_t'}}
+
   int size_b8[sizeof(__SVBool_t) == 0 ? 1 : -1];   // expected-error {{invalid application of 'sizeof' to sizeless type '__SVBool_t'}}
   int align_b8[__alignof__(__SVBool_t) == 2 ? 1 : -1]; // expected-error {{invalid application of '__alignof' to sizeless type '__SVBool_t'}}
 }
Index: clang/test/PCH/aarch64-sve-types.c
===
--- clang/test/PCH/aarch64-sve-types.c
+++ clang/test/PCH/aarch64-sve-types.c
@@ -18,4 +18,6 @@
 __SVFloat32_t *f32;
 __SVFloat64_t *f64;
 
+__SVBFloat16_t *bf16;
+
 __SVBool_t *b8;
Index: clang/test/CodeGenObjC/aarch64-sve-types.m
===
--- clang/test/CodeGenObjC/aarch64-sve-types.m
+++ clang/test/CodeGenObjC/aarch64-sve-types.m
@@ -1,7 +1,7 @@
 // RUN: not %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
 // RUN:   2>&1 | FileCheck %s
 // RUN: not %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
-// RUN:   -target-feature +sve 2>&1 | FileCheck %s
+// RUN:   -target-feature +sve,+bf16 2>&1 | FileCheck %s
 
 // CHECK: error: cannot yet @encode type __SVInt8_t
 const char s8[] = @encode(__SVInt8_t);
@@ -28,5 +28,8 @@
 // CHECK: error: cannot yet @encode type __SVFloat64_t
 const char f64[] = @encode(__SVFloat64_t);
 
+// CHECK: error: cannot yet @encode type __SVBFloat16_t
+const char bf16[] = @encode(__SVBFloat16_t);
+
 // CHECK: error: cannot yet @encode type __SVBool_t
 const char b8[] = @encode(__SVBool_t);
Index: clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
===
--- clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
+++ clang/test/CodeGenCXX/aarch64-sve-typeinfo.cpp
@@ -1,7 +1,7 @@
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
 // RUN:   | FileCheck %s
 // RUN: %clang_cc1 -triple aarch64-none-linux-gnu %s -emit-llvm -o - \
-// RUN:   -target-feature +sve | FileCheck %s
+// RUN:   -target-feature +sve,+bf16 | FileCheck %s
 
 namespace std { class type_info; };
 
@@ -19,6 +19,8 @@
 auto &f32 = typeid(__SVFloat32_t);
 auto &f64 = typeid(__SVFloat64_t);
 
+auto &bf16 = typeid(__SVBFloat16_t);
+
 auto &b8 = typeid(__SVBool_t);
 
 // CHECK-DAG: @_ZTSu10__SVInt8_t = {{.*}} c"u10__SVInt8_t\00"
@@ -53,6 +55,9 @@
 
 // CHECK-DAG: @_ZTSu13__SVFloat64_t = {{.*}} c"u13__SVFloat64_t\00"
 // CHECK-DAG: @_ZTIu13__SVFloat64_t = {{.*}} @_ZTVN10__cxxabiv123__fundamental_type_infoE, {{.*}} @_ZTSu13__SVFloat64_t
+//
+// CHECK-DAG: @_ZTSu14__SVBFloat16_t = {{.

[PATCH] D82665: [AArch64][SVE] Add bfloat16 to outstanding tuple vector intrinsics

[Cullen Rhodes via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe73c3bb06b5a: [AArch64][SVE] Add bfloat16 to outstanding 
tuple vector intrinsics (authored by c-rhodes).

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/include/clang/Basic/arm_sve.td
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef2-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef3-bfloat.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_undef4-bfloat.c
  llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll

Index: llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
===
--- llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
+++ llvm/test/CodeGen/AArch64/sve-intrinsics-create-tuple.ll
@@ -94,6 +94,37 @@
 }
 
 ;
+; SVCREATE2 (bfloat)
+;
+
+define  @test_svcreate2_bf16_vec0(i1 %p,  %z0,  %z1) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate2_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16( %z0,  %z1)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate2_bf16_vec1(i1 %p,  %z0,  %z1) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate2_bf16_vec1:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z1.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create2.nxv16bf16.nxv8bf16( %z0,  %z1)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv16bf16( %tuple, i32 1)
+  ret  %extract
+}
+
+;
 ; SVCREATE2 (i32)
 ;
 
@@ -278,6 +309,7 @@
   %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8i16.nxv24i16( %tuple, i32 2)
   ret  %extract
 }
+
 ;
 ; SVCREATE3 (half)
 ;
@@ -309,6 +341,36 @@
   ret  %extract
 }
 
+;
+; SVCREATE3 (bfloat)
+;
+
+define  @test_svcreate3_bf16_vec0(i1 %p,  %z0,  %z1,  %z2) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate3_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16( %z0,  %z1,  %z2)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate3_bf16_vec2(i1 %p,  %z0,  %z1,  %z2) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate3_bf16_vec2:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z2.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create3.nxv24bf16.nxv8bf16( %z0,  %z1,  %z2)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv24bf16( %tuple, i32 2)
+  ret  %extract
+}
 
 ;
 ; SVCREATE3 (i32)
@@ -528,6 +590,37 @@
 }
 
 ;
+; SVCREATE4 (bfloat)
+;
+
+define  @test_svcreate4_bf16_vec0(i1 %p,  %z0,  %z1,  %z2,  %z3) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate4_bf16_vec0:
+; CHECK: // %L2
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16( %z0,  %z1,  %z2,  %z3)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16( %tuple, i32 0)
+  ret  %extract
+}
+
+define  @test_svcreate4_bf16_vec3(i1 %p,  %z0,  %z1,  %z2,  %z3) local_unnamed_addr #1 {
+; CHECK-LABEL: test_svcreate4_bf16_vec3:
+; CHECK: // %L2
+; CHECK-NEXT: mov z0.d, z3.d
+; CHECK-NEXT: ret
+  %tuple = tail call  @llvm.aarch64.sve.tuple.create4.nxv32bf16.nxv8bf16( %z0,  %z1,  %z2,  %z3)
+  br i1 %p, label %L1, label %L2
+L1:
+  ret  undef
+L2:
+  %extract = tail call  @llvm.aarch64.sve.tuple.get.nxv8bf16.nxv32bf16( %tuple, i32 3)
+  ret  %extract
+}
+
+;
 ; SVCREATE4 (i32)
 ;
 
@@ -652,10 +745,13 @@
 }
 
 attributes #0 = { nounwind "target-features"="+sve" }
+; +bf16 is required for the bfloat version.
+attributes #1 = { nounwind "target-features"="+sve,+bf16" }
 
 declare   @llvm.aarch64.sve.tuple.create2.nxv4f64.nxv2f64(, )
 declare   @llvm.aarch64.sve.tuple.create2.nxv8f32.nxv4f32(, )
 declare   @llvm.aarch64.sve.tuple.create2.nxv16f16.nxv8f16(, )

[PATCH] D83553: [PATCH 3/4][Sema][AArch64] Add codegen for arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes abandoned this revision.
c-rhodes added a comment.

I've posted a prototype D85128  with an 
alternative implementation, given it's quite different to this patch I've 
posted it as a separate patch and am abandoning this one. See new patch for 
more details, cheers


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[PATCH] D85128: [Prototype][SVE] Support arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

In D85128#2191108 , @tschuett wrote:

> Stupid questions.
>
> - Is it for convenience? You get arrays, global variables, structs, ... . 
> Vectorization becomes easier ...

Yes, this allows the definition of types that can be used in constructs 
sizeless types cannot. In earlier revisions of the ACLE there was the concept 
of sizeless structs defined by a `__sizeless_struct` keyword that could have 
members of sizeless type in addition to members of sized type, although there 
was push back on the idea of sizeless aggregates in general and that idea was 
dropped. If you're interested in the background there's more information here 
[1][2].

[1] https://gcc.gnu.org/legacy-ml/gcc/2019-11/msg00088.html
[2] https://gcc.gnu.org/legacy-ml/gcc-patches/2018-10/msg00868.html

> - Are there any potential performance benefits over scalable vectors?

If VLSTs are represented as fixed-length vectors in LLVM as they are in this 
prototype then hopefully we can take advantage of existing optimisations, 
although I think there is work to be done there especially around the 
interaction with scalable vectors and supporting those in existing passes. This 
patch required a few changes to existing passes to bail out for scalable 
vectors so we're already hitting parts of the codebase we've yet to hit that 
would be good candidates for optimisation work. This also ties into the 
fixed-length code generation work @paulwalker-arm has been doing which is still 
early days. I'm not sure if that answers your question, but ultimately the 
compiler should have more information about these types given the vector size 
is explicit so it should be able to do a better job at optimisation.

> - Is it compatible with GCC?

Support for this attribute landed in GCC 10 and it's more complete than what 
this patch implements. We've yet to implement the behaviour guarded by the 
`__ARM_FEATURE_SVE_VECTOR_OPERATORS` and 
`__ARM_FEATURE_SVE_PREDICATE_OPERATORS` feature macros, so the GNU 
`__attribute__((vector_size))` extension is not available and operators such as 
binary '+' are not supported for VLSTs. Support for this is intended to be 
addressed by later patches.


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[PATCH] D85128: [Prototype][SVE] Support arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

In D85128#2191401 , @efriedma wrote:

> Not going to write detailed review comments, but this looks like the right 
> approach in general.

Thanks for taking a look! I'll split this up into separate patches soon.

> One high-level thing to consider: we could still decide that in IR 
> generation, we want to represent VLSTs registers using scalable vector types, 
> like the original patch did.  This would allow avoiding the awkward "bitcast" 
> implementation.  That interacts with a relatively narrow slice of clang 
> CodeGen, though; we could easily change it later without impacting the rest 
> of the changes.

Yeah now that the VLST is part of the canonical type with the new vector kinds 
we have more information if we were to go the CodeGenTypes route if that's what 
you're referring to as the narrow slice of CodeGen. That would still require 
converting between VLAT/VLST, I quite like this approach as it gives me more 
confidence we're not missing bitcasts when doing it as part of a cast 
operation. I guess with what you're suggesting the bitcast could still be 
emitted there but the cast operations could be limited in Sema to cases where 
ultimately `ConvertType` would return a type that requires bitcasting, or are 
you saying that could be avoided completely?


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[PATCH] D85128: [Prototype][SVE] Support arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

In D85128#2192867 , @c-rhodes wrote:

> In D85128#2191108 , @tschuett wrote:
>
>> - Is it compatible with GCC?
>
> Support for this attribute landed in GCC 10 and it's more complete than what 
> this patch implements. We've yet to implement the behaviour guarded by the 
> `__ARM_FEATURE_SVE_VECTOR_OPERATORS` and 
> `__ARM_FEATURE_SVE_PREDICATE_OPERATORS` feature macros, so the GNU 
> `__attribute__((vector_size))` extension is not available and operators such 
> as binary '+' are not supported for VLSTs. Support for this is intended to be 
> addressed by later patches.

Just to clarify, GCC doesn't have support for vectors of booleans or operations 
on them (`__ARM_FEATURE_SVE_PREDICATE_OPERATORS`) yet either but does support 
the behaviour indicated by the other macro.


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[PATCH] D85128: [Prototype][SVE] Support arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added a comment.

In D85128#2193309 , @tschuett wrote:

> Sorry. I meant ABI. Can link GCC .o files with Clang .o files using the 
> attributes?

Yes they should be compatible. The machine-level ABI distinguishes 4 types of 
SVE vector [1]:

- VG×64-bit vector of 8-bit elements
- VG×64-bit vector of 16-bit elements
- VG×64-bit vector of 32-bit elements
- VG×64-bit vector of 64-bit elements

The VLS and VLA types are defined by the ACLE to map to the same machine-level 
SVE vectors (in both compilers). Hence the mangling changes in this patch.

[1] 
https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#fundamental-data-types


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[PATCH] D85736: [Sema][AArch64] Support arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: efriedma, sdesmalen, rsandifo-arm, aaron.ballman, 
paulwalker-arm.
Herald added subscribers: danielkiss, kristof.beyls, tschuett.
Herald added a reviewer: rengolin.
Herald added a project: clang.
c-rhodes requested review of this revision.

This patch implements the semantics for the 'arm_sve_vector_bits' type
attribute, defined by the Arm C Language Extensions (ACLE) for SVE [1].
The purpose of this attribute is to define vector-length-specific (VLS)
versions of existing vector-length-agnostic (VLA) types.

The semantics were already implemented by D83551 
, although the
implementation approach has since changed to represent VLSTs as
VectorType in the AST and fixed-length vectors in the IR everywhere
except in function args/returns. This is described in the prototype
patch D85128  demonstrating the new approach.

The semantic changes added in D83551  are 
changed since the
AttributedType is replaced by VectorType in the AST. Minimal changes
were necessary in the previous patch as the canonical type for both VLA
and VLS was the same (i.e. sizeless), except in constructs such as
globals and structs where sizeless types are unsupported. This patch
reverts the changes that permitted VLS types that were represented as
sizeless types in such circumstances, and adds support for implicit
casting between VLA <-> VLS types as described in section 3.7.3.2 of the
ACLE.

Since the SVE builtin types for bool and uint8 are both represented as
BuiltinType::UChar in VLSTs, two new vector kinds are implemented to
distinguish predicate and data vectors.

[1] https://developer.arm.com/documentation/100987/latest


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D85736

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/JSONNodeDumper.cpp
  clang/lib/AST/TextNodeDumper.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c

Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -102,8 +102,11 @@
   svint8_t ss8;
 
   void *sel __attribute__((unused));
-  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types ('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
-  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types ('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}
+  sel = c ? ss8 : fs8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
+  sel = c ? fs8 : ss8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
+
+  sel = fs8 + ss8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
+  sel = ss8 + fs8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
 }
 
 // --//
@@ -192,14 +195,18 @@
 TEST_CAST(bool)
 
 // Test the implicit conversion only applies to valid types
-fixed_int8_t to_fixed_int8_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_int8_t' (aka '__SVInt8_t')}}
-fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (aka '__SVBool_t')}}
+fixed_int8_t to_fixed_int8_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error-re {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_int8_t' (vector of {{[0-9]+}} 'signed char' values)}}
+fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
+
+// Test conversion between predicate and uint8 is invalid, both have the same
+// memory representation.
+fixed_bool_t to_fixed_bool_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error-re {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
 
 // Test the implicit conversion only applies to fixed-length types
 typedef signed int vSInt32 __attribute__((__vector_size__(16)));
-svint32_t to_svint32_t_from_gnut(vSInt32 x) { return x; } // expected

[PATCH] D85736: [Sema][AArch64] Support arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 285124.
c-rhodes added a comment.

Added missing implicit conversions for C++. I considered handling this with the
existing implicit vector conversion although one side of the conversion will be
an SVE builtin, so instead I've added a new conversion specifically for SVE. I
suspect the existing one could support this but I wasn't sure if that was a good
idea (?). In C++ implicit conversions between VLA/VLS have a rank just below
derived-to-base conversion.


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https://reviews.llvm.org/D85736

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Overload.h
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/JSONNodeDumper.cpp
  clang/lib/AST/TextNodeDumper.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaExprCXX.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c
  clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// expected-no-diagnostics
+
+#define N __ARM_FEATURE_SVE_BITS_EXPERIMENTAL
+
+typedef __SVInt8_t svint8_t;
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+
+template struct S { T var; };
+
+S s;
+
+svint8_t to_svint8_t(fixed_int8_t x) { return x; }
+fixed_int8_t from_svint8_t(svint8_t x) { return x; }
Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -102,8 +102,11 @@
   svint8_t ss8;
 
   void *sel __attribute__((unused));
-  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types ('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
-  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types ('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}
+  sel = c ? ss8 : fs8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
+  sel = c ? fs8 : ss8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
+
+  sel = fs8 + ss8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
+  sel = ss8 + fs8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
 }
 
 // --//
@@ -192,14 +195,18 @@
 TEST_CAST(bool)
 
 // Test the implicit conversion only applies to valid types
-fixed_int8_t to_fixed_int8_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_int8_t' (aka '__SVInt8_t')}}
-fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (aka '__SVBool_t')}}
+fixed_int8_t to_fixed_int8_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error-re {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_int8_t' (vector of {{[0-9]+}} 'signed char' values)}}
+fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
+
+// Test conversion between predicate and uint8 is invalid, both have the same
+// memory representation.
+fixed_bool_t to_fixed_bool_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error-re {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
 
 // Test the implicit conversion only applies to fixed-length types
 typedef signed int vSInt32 __attribute__((__vector_size__(16)));
-svint32_t to_svint32_t_from_gnut(vSInt32 x) { return x; } // expected-error {{returning 'vSInt32' (vector of 4 'int' values) from a function with incompatible result type 'svint32_t' (aka '__SVInt32_t')}}
+svint32_t to_svint32_t_from_gnut(vSInt32 x) { return x; } // expected-error-re {{returning 'vSInt32' (vector of {{[0-9]+}} 'int' values) from a function with incompatible result type 'svint32_t' (aka '__SVInt32_t')}}
 
-vSInt32 to_gnut_f

[PATCH] D85736: [Sema][AArch64] Support arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 285285.
c-rhodes marked an inline comment as not done.
c-rhodes added a comment.

Address @rsandifo-arm comments.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D85736/new/

https://reviews.llvm.org/D85736

Files:
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/Type.h
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Overload.h
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTContext.cpp
  clang/lib/AST/JSONNodeDumper.cpp
  clang/lib/AST/TextNodeDumper.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Sema/SemaDecl.cpp
  clang/lib/Sema/SemaExpr.cpp
  clang/lib/Sema/SemaExprCXX.cpp
  clang/lib/Sema/SemaOverload.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/Sema/attr-arm-sve-vector-bits.c
  clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp

Index: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
===
--- /dev/null
+++ clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +bf16 -fsyntax-only -verify -std=c++11 -msve-vector-bits=512 -fallow-half-arguments-and-returns %s
+// expected-no-diagnostics
+
+#define N __ARM_FEATURE_SVE_BITS_EXPERIMENTAL
+
+typedef __SVInt8_t svint8_t;
+typedef svint8_t fixed_int8_t __attribute__((arm_sve_vector_bits(N)));
+
+template struct S { T var; };
+
+S s;
+
+svint8_t to_svint8_t(fixed_int8_t x) { return x; }
+fixed_int8_t from_svint8_t(svint8_t x) { return x; }
Index: clang/test/Sema/attr-arm-sve-vector-bits.c
===
--- clang/test/Sema/attr-arm-sve-vector-bits.c
+++ clang/test/Sema/attr-arm-sve-vector-bits.c
@@ -102,8 +102,11 @@
   svint8_t ss8;
 
   void *sel __attribute__((unused));
-  sel = c ? ss8 : fs8; // expected-error {{incompatible operand types ('svint8_t' (aka '__SVInt8_t') and 'fixed_int8_t' (aka '__SVInt8_t'))}}
-  sel = c ? fs8 : ss8; // expected-error {{incompatible operand types ('fixed_int8_t' (aka '__SVInt8_t') and 'svint8_t' (aka '__SVInt8_t'))}}
+  sel = c ? ss8 : fs8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
+  sel = c ? fs8 : ss8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
+
+  sel = fs8 + ss8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
+  sel = ss8 + fs8; // expected-error {{cannot convert between fixed-length and sizeless vector}}
 }
 
 // --//
@@ -192,14 +195,18 @@
 TEST_CAST(bool)
 
 // Test the implicit conversion only applies to valid types
-fixed_int8_t to_fixed_int8_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_int8_t' (aka '__SVInt8_t')}}
-fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (aka '__SVBool_t')}}
+fixed_int8_t to_fixed_int8_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error-re {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_int8_t' (vector of {{[0-9]+}} 'signed char' values)}}
+fixed_bool_t to_fixed_bool_t__from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
+
+// Test conversion between predicate and uint8 is invalid, both have the same
+// memory representation.
+fixed_bool_t to_fixed_bool_t__from_svuint8_t(svuint8_t x) { return x; } // expected-error-re {{returning 'svuint8_t' (aka '__SVUint8_t') from a function with incompatible result type 'fixed_bool_t' (vector of {{[0-9]+}} 'unsigned char' values)}}
 
 // Test the implicit conversion only applies to fixed-length types
 typedef signed int vSInt32 __attribute__((__vector_size__(16)));
-svint32_t to_svint32_t_from_gnut(vSInt32 x) { return x; } // expected-error {{returning 'vSInt32' (vector of 4 'int' values) from a function with incompatible result type 'svint32_t' (aka '__SVInt32_t')}}
+svint32_t to_svint32_t_from_gnut(vSInt32 x) { return x; } // expected-error-re {{returning 'vSInt32' (vector of {{[0-9]+}} 'int' values) from a function with incompatible result type 'svint32_t' (aka '__SVInt32_t')}}
 
-vSInt32 to_gnut_from_svint32_t(svint32_t x) { return x; } // expected-error {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible result type 'vSInt32' (vector of 4 'int' values)}}
+vSInt32 to_gnut_from_svint32_t(svint32_t x) { return x; } // expected-error-re {{returning 'svint32_t' (aka '__SVInt32_t') from a function with incompatible 

[PATCH] D85736: [Sema][AArch64] Support arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked 4 inline comments as done.
c-rhodes added inline comments.



Comment at: clang/lib/AST/ASTContext.cpp:1941
+// Adjust the alignment for fixed-length SVE predicates.
+if (VT->getVectorKind() == VectorType::SveFixedLengthPredicateVector)
+  Align = 16;

rsandifo-arm wrote:
> The alignment of the SVE data vectors should be 128 too (see the alignof 
> stuff in the ACLE doc).  FWIW, there were two reasons for defining it like 
> that:
>   - the fixed-length types map to the same ABI machine type as the 
> variable-length types
>   - the length isn't required to be a power of 2: an implementation that 
> supports fixed-length 384-bit vectors could define `__ARM_FEATURE_SVE_BITS` 
> to 384.
> 
> 
> 
> The alignment of the SVE data vectors should be 128 too (see the alignof 
> stuff in the ACLE doc).

Ah, good point. This would've bitten us when when we come to supporting 
non-power-of-2 vector lengths.



Comment at: clang/lib/AST/Type.cpp:2338
+  case BuiltinType::SveUint32:
+return Ctx.UnsignedIntTy;
+  case BuiltinType::SveInt64:

rsandifo-arm wrote:
> This is just a note, not sure what can be done about it, but:
> 
> The element types are defined in terms of the stdint.h types.  One snag is 
> that ILP32 newlib defines `int32_t` to be UnsignedLongTy instead of 
> UnsignedIntTy, and defines `uint64_t` to UnsignedLongLongTy.
> 
> In GCC we got away with this because GCC already has hard-coded knowledge 
> about the target C library's choices.  I don't think that information is 
> available here though.
> 
> Like I say, there's nothing that necessarily needs to be “fixed”/dealt-with 
> now, just thought it was worth mentioning.
Thanks for the heads up! I'm not familiar with ILP32 so that's good to know. So 
if `-mabi=ilp32` is passed then I guess we should handle that here. I'll make a 
note of this and address it in a later patch.



Comment at: clang/lib/Sema/SemaExpr.cpp:8934
+  ASTContext &Context) {
+  auto IsValidCast = [](QualType LHSType, QualType RHSType,
+ASTContext &Context) {

rsandifo-arm wrote:
> I guess this is personal preference, but it seems more natural to use `[&]` 
> and not pass the context.  Maybe different names from LHSType and RHSType 
> would be better for the nested function, since it's called with both orders.
> I guess this is personal preference, but it seems more natural to use [&] and 
> not pass the context.

Agreed, that's nicer.

> Maybe different names from LHSType and RHSType would be better for the nested 
> function, since it's called with both orders.

I've renamed them to first/second.




Comment at: clang/lib/Sema/SemaExpr.cpp:8942
+VT->getVectorKind() == VectorType::SveFixedLengthPredicateVector &&
+isVector(RHSType, LHSType->getFixedLengthSveEltType(Context)))
+  return true;

rsandifo-arm wrote:
> Is the isVector just being defensive?  I'd have expected it to be redundant, 
> since we shouldn't create SveFixedLengthPredicateVectors with invalid element 
> types.
> Is the isVector just being defensive? I'd have expected it to be redundant, 
> since we shouldn't create SveFixedLengthPredicateVectors with invalid element 
> types.

Yeah although as you say it's not really necessary, fixed.



Comment at: clang/lib/Sema/SemaExpr.cpp:8945
+
+if (VT->getVectorKind() == VectorType::SveFixedLengthDataVector &&
+isVector(RHSType, LHSType->getFixedLengthSveEltType(Context)))

rsandifo-arm wrote:
> It looks like this could still trigger for SveBools.  Maybe it would be 
> better to have:
> 
>   if (BT->getKind() == BuiltinType::SveBool) {
> …
>   } else {
> …
>   }
> 
> instead.  Perhaps it'd also be worth having an assert to show that we've 
> already checked that any builtin type is an SVE type.
I've simplified this somewhat although I'm not sure if it's what you meant. If 
it's a predicate vector kind then it's compatible if the builtin is an SVE 
bool, otherwise it compares the types. Worth noting I've moved this to 
ASTContext also since it's used for the C++ conversions.


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[PATCH] D85743: [CodeGen][AArch64] Support arm_sve_vector_bits attribute

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes marked 2 inline comments as done.
c-rhodes added inline comments.



Comment at: clang/lib/AST/ItaniumMangle.cpp:3330
+// appendices to the Procedure Call Standard for the Arm Architecture, see:
+// 
https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#appendix-c-mangling
+void CXXNameMangler::mangleAArch64FixedSveVectorType(const VectorType *T) {

efriedma wrote:
> Mangling them the same way is going to cause practical issues; they're 
> different types from a C++ perspective, so they need distinct manglings.  For 
> example, you'll crash the compiler if you refer to both foo and 
> foo.
> Mangling them the same way is going to cause practical issues; they're 
> different types from a C++ perspective, so they need distinct manglings. For 
> example, you'll crash the compiler if you refer to both foo and 
> foo.

The ACLE is yet to define the mangling scheme for fixed-length SVE types so I 
kept the mangling the same, which is also what GCC currently does. After 
speaking with @rsandifo-arm yesterday we agreed to come up with a mangling 
scheme where the types are mangled in the same way as:

```__SVE_VLS```

where the first argument is the underlying variable-length type and the second 
argument is the SVE vector length in bits.  For example:

```#if __ARM_FEATURE_SVE_BITS==512
// Mangled as 9__SVE_VLSIu11__SVInt32_tLj512EE
typedef svint32_t vec __attribute__((arm_sve_vector_bits(512)));  
// Mangled as 9__SVE_VLSIu10__SVBool_tLj512EE  
typedef svbool_t pred __attribute__((arm_sve_vector_bits(512)));  
#endif```

let us know if you have any feedback/concerns about this approach.



Comment at: clang/lib/CodeGen/CGCall.cpp:1361
+Tmp.getAlignment().getAsAlign(),
+llvm::ConstantInt::get(CGF.IntPtrTy, DstSize.getKnownMinSize()));
   }

@efriedma If we're happy with the element bitcast above this can also be fixed 
but I wasn't if that was ok, although it's pretty much what was implemented in 
the original codegen patch.


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[PATCH] D86100: [Clang][SVE] NFC: Move info about ACLE types into separate function.

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes accepted this revision.
c-rhodes added a comment.
This revision is now accepted and ready to land.

LGTM, just one minor nit but seems like a nice improvement




Comment at: clang/include/clang/AST/ASTContext.h:1318
+  BuiltinVectorTypeInfo
+  getElementTypeForBuiltinVector(const BuiltinType *VecTy) const;
+

nit: not sure on the name here since it's returning more than the element type, 
how about `getBuiltinVectorTypeInfo`?


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[PATCH] D130984: [clang][AArch64][SVE] Add unary +/- operators for SVE types

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes accepted this revision.
c-rhodes added a comment.
This revision is now accepted and ready to land.

LGTM, just one minor comment




Comment at: clang/test/CodeGen/aarch64-sve-vector-arith-ops.c:1654
+
+// UNARY PROMOTION
+

should we add FP tests as well?


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[PATCH] D106333: [AArch64][SVE] Handle svbool_t VLST <-> VLAT/GNUT conversion

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/lib/AST/ASTContext.cpp:8673
 
+/// getSVETypeSize - Return SVE vector or perdicate register size.
+static uint64_t getSVETypeSize(ASTContext &Context, const BuiltinType *Ty) {

s/perdicate/predicate



Comment at: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp:13-14
 typedef svfloat32_t sve_fixed_float32_t SVE_FIXED_ATTR;
 typedef svint32_t sve_fixed_int32_t SVE_FIXED_ATTR;
+typedef svbool_t sve_fixed_bool_t SVE_FIXED_ATTR;
 typedef float gnu_fixed_float32_t GNU_FIXED_ATTR;

unused?



Comment at: clang/test/SemaCXX/aarch64-sve-lax-vector-conversions.cpp:17
 typedef int gnu_fixed_int32_t GNU_FIXED_ATTR;
+typedef int8_t gnu_fixed_bool_t GNU_BOOL_FIXED_ATTR;
 

also unused?



Comment at: clang/test/SemaCXX/attr-arm-sve-vector-bits.cpp:32
+
+// Test implicit casts between VLA and VLS perdicates
+svbool_t to_svbool_t(fixed_bool_t x) { return x; }

s/perdicates/predicates


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[PATCH] D106860: [clang][AArch64][SVE] Avoid going through memory for fixed/scalable predicate casts

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/lib/CodeGen/CGExprScalar.cpp:2065
 if (const auto *FixedSrc = dyn_cast(SrcTy)) {
   if (const auto *ScalableDst = dyn_cast(DstTy)) 
{
+// If we are casting a fixed i8 vector to a scalable 16 x i1 predicate

should const be dropped now the type might change?



Comment at: clang/lib/CodeGen/CGExprScalar.cpp:2110-2129
 // Perform VLAT <-> VLST bitcast through memory.
 // TODO: since the llvm.experimental.vector.{insert,extract} intrinsics
 //   require the element types of the vectors to be the same, we
 //   need to keep this around for casting between predicates, or more
 //   generally for bitcasts between VLAT <-> VLST where the element
 //   types of the vectors are not the same, until we figure out a 
better
 //   way of doing these casts.

With the predicate casting now using the intrinsics I don't think this is 
needed any longer. Perhaps we should add an unreachable above if the element 
type doesn't match?


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[PATCH] D106860: [clang][AArch64][SVE] Avoid going through memory for fixed/scalable predicate casts

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes added inline comments.



Comment at: clang/lib/CodeGen/CGExprScalar.cpp:2110-2129
 // Perform VLAT <-> VLST bitcast through memory.
 // TODO: since the llvm.experimental.vector.{insert,extract} intrinsics
 //   require the element types of the vectors to be the same, we
 //   need to keep this around for casting between predicates, or more
 //   generally for bitcasts between VLAT <-> VLST where the element
 //   types of the vectors are not the same, until we figure out a 
better
 //   way of doing these casts.

bsmith wrote:
> c-rhodes wrote:
> > With the predicate casting now using the intrinsics I don't think this is 
> > needed any longer. Perhaps we should add an unreachable above if the 
> > element type doesn't match?
> Don't we still need this for casting between vectors with different element 
> types, or are these guaranteed to not hit this code path?
> Don't we still need this for casting between vectors with different element 
> types, or are these guaranteed to not hit this code path?

Apologies I was wrong, you're right we'll still need it for casting between 
vectors with different element types to support lax vector conversions, 
although it's no longer tested. Might be worth adding a codegen test for ~:

```svint64_t lax_cast(fixed_int32_t t) {
return t;
}```

and the comment could also be updated


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[PATCH] D129476: [AArch64][SVE] Prefer SIMD&FP variant of clast[ab]

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes created this revision.
c-rhodes added reviewers: paulwalker-arm, bsmith, peterwaller-arm, DavidTruby.
Herald added subscribers: psnobl, hiraditya, kristof.beyls, tschuett.
Herald added a reviewer: efriedma.
Herald added a project: All.
c-rhodes requested review of this revision.
Herald added projects: clang, LLVM.
Herald added a subscriber: cfe-commits.

The scalar variant with GPR source/dest has considerably higher latency
than the SIMD&FP scalar variant across a variety of micro-architectures:

  Core   ScalarSIMD&FP
  
  Neoverse V1 9 cyc  3 cyc
  Neoverse N2 8 cyc  3 cyc
  Cortex A510 8 cyc  4 cyc


Repository:
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https://reviews.llvm.org/D129476

Files:
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-clast.ll

Index: llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-clast.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-clast.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+
+target triple = "aarch64"
+
+define i16 @clastb_n_i16( %pg, i16 %a,  %b) {
+; CHECK-LABEL: @clastb_n_i16(
+; CHECK-NEXT:[[TMP1:%.*]] = bitcast i16 [[A:%.*]] to half
+; CHECK-NEXT:[[TMP2:%.*]] = bitcast  [[B:%.*]] to 
+; CHECK-NEXT:[[TMP3:%.*]] = call half @llvm.aarch64.sve.clastb.n.nxv8f16( [[PG:%.*]], half [[TMP1]],  [[TMP2]])
+; CHECK-NEXT:[[TMP4:%.*]] = bitcast half [[TMP3]] to i16
+; CHECK-NEXT:ret i16 [[TMP4]]
+;
+  %out = call i16 @llvm.aarch64.sve.clastb.n.nxv8i16( %pg, i16 %a,  %b)
+  ret i16 %out
+}
+
+define i32 @clastb_n_i32( %pg, i32 %a,  %b) {
+; CHECK-LABEL: @clastb_n_i32(
+; CHECK-NEXT:[[TMP1:%.*]] = bitcast i32 [[A:%.*]] to float
+; CHECK-NEXT:[[TMP2:%.*]] = bitcast  [[B:%.*]] to 
+; CHECK-NEXT:[[TMP3:%.*]] = call float @llvm.aarch64.sve.clastb.n.nxv4f32( [[PG:%.*]], float [[TMP1]],  [[TMP2]])
+; CHECK-NEXT:[[TMP4:%.*]] = bitcast float [[TMP3]] to i32
+; CHECK-NEXT:ret i32 [[TMP4]]
+;
+  %out = call i32 @llvm.aarch64.sve.clastb.n.nxv4i32( %pg, i32 %a,  %b)
+  ret i32 %out
+}
+
+define i64 @clastb_n_i64( %pg, i64 %a,  %b) {
+; CHECK-LABEL: @clastb_n_i64(
+; CHECK-NEXT:[[TMP1:%.*]] = bitcast i64 [[A:%.*]] to double
+; CHECK-NEXT:[[TMP2:%.*]] = bitcast  [[B:%.*]] to 
+; CHECK-NEXT:[[TMP3:%.*]] = call double @llvm.aarch64.sve.clastb.n.nxv2f64( [[PG:%.*]], double [[TMP1]],  [[TMP2]])
+; CHECK-NEXT:[[TMP4:%.*]] = bitcast double [[TMP3]] to i64
+; CHECK-NEXT:ret i64 [[TMP4]]
+;
+  %out = call i64 @llvm.aarch64.sve.clastb.n.nxv2i64( %pg, i64 %a,  %b)
+  ret i64 %out
+}
+
+declare i16 @llvm.aarch64.sve.clastb.n.nxv8i16(, i16, )
+declare i32 @llvm.aarch64.sve.clastb.n.nxv4i32(, i32, )
+declare i64 @llvm.aarch64.sve.clastb.n.nxv2i64(, i64, )
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -796,6 +796,44 @@
   return IC.replaceInstUsesWith(II, Extract);
 }
 
+static Optional instCombineSVECondLast(InstCombiner &IC,
+  IntrinsicInst &II) {
+  // Replace scalar integer CLAST[AB] intrinsic with optimal SIMD&FP variant.
+  IRBuilder<> Builder(II.getContext());
+  Builder.SetInsertPoint(&II);
+  Value *Pg = II.getArgOperand(0);
+  Value *Fallback = II.getArgOperand(1);
+  Value *Vec = II.getArgOperand(2);
+  Type *Ty = II.getType();
+
+  if (!Ty->isIntegerTy())
+return None;
+
+  Type *FPTy;
+  switch (cast(Ty)->getBitWidth()) {
+  default:
+return None;
+  case 16:
+FPTy = Builder.getHalfTy();
+break;
+  case 32:
+FPTy = Builder.getFloatTy();
+break;
+  case 64:
+FPTy = Builder.getDoubleTy();
+break;
+  }
+
+  Value *FPFallBack = Builder.CreateBitCast(Fallback, FPTy);
+  auto *FPVTy = VectorType::get(
+  FPTy, cast(Vec->getType())->getElementCount());
+  Value *FPVec = Builder.CreateBitCast(Vec, FPVTy);
+  auto *FPII = Builder.CreateIntrinsic(II.getIntrinsicID(), {FPVec->getType()},
+   {Pg, FPFallBack, FPVec});
+  Value *FPIItoInt = Builder.CreateBitCast(FPII, II.getType());
+  return IC.replaceInstUsesWith(II, FPIItoInt);
+}
+
 static Optional instCombineRDFFR(InstCombiner &IC,
 IntrinsicInst &II) {
   LLVMContext &Ctx = II.getContext();
@@ -1294,6 +1332,9 @@
   case Intrinsic::aarch64_sve_lasta:
   case Intrinsic::aarch64_sve_lastb:
 return instCombineSVELast(IC, II);
+  case Intrinsic::aarch64_sv

[PATCH] D129476: [AArch64][SVE] Prefer SIMD&FP variant of clast[ab]

[Cullen Rhodes via Phabricator via cfe-commits]

c-rhodes updated this revision to Diff 443594.
c-rhodes added a comment.

Add full patch context.


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Files:
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clasta.c
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c
  llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
  llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-clast.ll

Index: llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-clast.ll
===
--- /dev/null
+++ llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-opts-clast.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=instcombine -S < %s | FileCheck %s
+
+target triple = "aarch64"
+
+define i16 @clastb_n_i16( %pg, i16 %a,  %b) {
+; CHECK-LABEL: @clastb_n_i16(
+; CHECK-NEXT:[[TMP1:%.*]] = bitcast i16 [[A:%.*]] to half
+; CHECK-NEXT:[[TMP2:%.*]] = bitcast  [[B:%.*]] to 
+; CHECK-NEXT:[[TMP3:%.*]] = call half @llvm.aarch64.sve.clastb.n.nxv8f16( [[PG:%.*]], half [[TMP1]],  [[TMP2]])
+; CHECK-NEXT:[[TMP4:%.*]] = bitcast half [[TMP3]] to i16
+; CHECK-NEXT:ret i16 [[TMP4]]
+;
+  %out = call i16 @llvm.aarch64.sve.clastb.n.nxv8i16( %pg, i16 %a,  %b)
+  ret i16 %out
+}
+
+define i32 @clastb_n_i32( %pg, i32 %a,  %b) {
+; CHECK-LABEL: @clastb_n_i32(
+; CHECK-NEXT:[[TMP1:%.*]] = bitcast i32 [[A:%.*]] to float
+; CHECK-NEXT:[[TMP2:%.*]] = bitcast  [[B:%.*]] to 
+; CHECK-NEXT:[[TMP3:%.*]] = call float @llvm.aarch64.sve.clastb.n.nxv4f32( [[PG:%.*]], float [[TMP1]],  [[TMP2]])
+; CHECK-NEXT:[[TMP4:%.*]] = bitcast float [[TMP3]] to i32
+; CHECK-NEXT:ret i32 [[TMP4]]
+;
+  %out = call i32 @llvm.aarch64.sve.clastb.n.nxv4i32( %pg, i32 %a,  %b)
+  ret i32 %out
+}
+
+define i64 @clastb_n_i64( %pg, i64 %a,  %b) {
+; CHECK-LABEL: @clastb_n_i64(
+; CHECK-NEXT:[[TMP1:%.*]] = bitcast i64 [[A:%.*]] to double
+; CHECK-NEXT:[[TMP2:%.*]] = bitcast  [[B:%.*]] to 
+; CHECK-NEXT:[[TMP3:%.*]] = call double @llvm.aarch64.sve.clastb.n.nxv2f64( [[PG:%.*]], double [[TMP1]],  [[TMP2]])
+; CHECK-NEXT:[[TMP4:%.*]] = bitcast double [[TMP3]] to i64
+; CHECK-NEXT:ret i64 [[TMP4]]
+;
+  %out = call i64 @llvm.aarch64.sve.clastb.n.nxv2i64( %pg, i64 %a,  %b)
+  ret i64 %out
+}
+
+declare i16 @llvm.aarch64.sve.clastb.n.nxv8i16(, i16, )
+declare i32 @llvm.aarch64.sve.clastb.n.nxv4i32(, i32, )
+declare i64 @llvm.aarch64.sve.clastb.n.nxv2i64(, i64, )
Index: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
===
--- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -796,6 +796,44 @@
   return IC.replaceInstUsesWith(II, Extract);
 }
 
+static Optional instCombineSVECondLast(InstCombiner &IC,
+  IntrinsicInst &II) {
+  // Replace scalar integer CLAST[AB] intrinsic with optimal SIMD&FP variant.
+  IRBuilder<> Builder(II.getContext());
+  Builder.SetInsertPoint(&II);
+  Value *Pg = II.getArgOperand(0);
+  Value *Fallback = II.getArgOperand(1);
+  Value *Vec = II.getArgOperand(2);
+  Type *Ty = II.getType();
+
+  if (!Ty->isIntegerTy())
+return None;
+
+  Type *FPTy;
+  switch (cast(Ty)->getBitWidth()) {
+  default:
+return None;
+  case 16:
+FPTy = Builder.getHalfTy();
+break;
+  case 32:
+FPTy = Builder.getFloatTy();
+break;
+  case 64:
+FPTy = Builder.getDoubleTy();
+break;
+  }
+
+  Value *FPFallBack = Builder.CreateBitCast(Fallback, FPTy);
+  auto *FPVTy = VectorType::get(
+  FPTy, cast(Vec->getType())->getElementCount());
+  Value *FPVec = Builder.CreateBitCast(Vec, FPVTy);
+  auto *FPII = Builder.CreateIntrinsic(II.getIntrinsicID(), {FPVec->getType()},
+   {Pg, FPFallBack, FPVec});
+  Value *FPIItoInt = Builder.CreateBitCast(FPII, II.getType());
+  return IC.replaceInstUsesWith(II, FPIItoInt);
+}
+
 static Optional instCombineRDFFR(InstCombiner &IC,
 IntrinsicInst &II) {
   LLVMContext &Ctx = II.getContext();
@@ -1294,6 +1332,9 @@
   case Intrinsic::aarch64_sve_lasta:
   case Intrinsic::aarch64_sve_lastb:
 return instCombineSVELast(IC, II);
+  case Intrinsic::aarch64_sve_clasta_n:
+  case Intrinsic::aarch64_sve_clastb_n:
+return instCombineSVECondLast(IC, II);
   case Intrinsic::aarch64_sve_cntd:
 return instCombineSVECntElts(IC, II, 2);
   case Intrinsic::aarch64_sve_cntw:
Index: clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c
===
--- clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c
+++ clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clastb.c
@@ -215,14 +215,20 @@
 // CHECK-LABEL: @test_svclastb_n_s16(
 // CHECK-NEXT:  ent