[PATCH] D121915: [RISCV][1/2]Add IR intrinsic for Zbb extension

2022-03-17 Thread Chang Hu via Phabricator via cfe-commits 
joker881 created this revision.
joker881 added a reviewer: craig.topper.
Herald added subscribers: s, VincentWu, luke957, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, 
arichardson.
Herald added a project: All.
joker881 requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

clz


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121915

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
  llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll

Index: llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -54,3 +54,14 @@
   %tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
   ret i64 %tmp
 }
+
+declare i64 @llvm.riscv.clz.i64(i64)
+
+define i64 @clz64(i64 %a) nounwind {
+; RV64ZBB-LABEL: clz64:
+; RV64ZBB:   # %bb.0:
+; RV64ZBB-NEXT:clz a0, a0
+; RV64ZBB-NEXT:ret
+  %tmp = call i64 @llvm.riscv.clz.i64(i64 %a)
+  ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
===
--- llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
@@ -12,3 +12,13 @@
   %tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
   ret i32 %tmp
 }
+declare i32 @llvm.riscv.clz.i32(i32)
+
+define i32 @clz(i32 %a) nounwind {
+; RV32ZBB-LABEL: clz:
+; RV32ZBB:   # %bb.0:
+; RV32ZBB-NEXT:clz a0, a0
+; RV32ZBB-NEXT:ret
+  %tmp = call i32 @llvm.riscv.clz.i32(i32 %a)
+  ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1213,3 +1213,7 @@
 def : PatGprGpr;
 def : PatGprGpr;
 }
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr;
+}
+
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -87,6 +87,7 @@
 
   // Zbb
   def int_riscv_orc_b : BitManipGPRIntrinsics;
+  def int_riscv_clz : BitManipGPRIntrinsics;
 
   // Zbc or Zbkc
   def int_riscv_clmul  : BitManipGPRGPRIntrinsics;
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -25,3 +25,27 @@
 long orc_b_64(long a) {
   return __builtin_riscv_orc_b_64(a);
 }
+
+// RV64ZBB-LABEL: @clz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.clz.i32(i32 [[TMP0]])
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
+
+// RV64ZBB-LABEL: @clz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.riscv.clz.i64(i64 [[TMP0]])
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long clz_64(long a) {
+  return __builtin_riscv_clz_64(a);
+}
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -13,3 +13,14 @@
 int orc_b_32(int a) {
   return __builtin_riscv_orc_b_32(a);
 }
+// RV32ZBB-LABEL: @clz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.clz.i32(i32 [[TMP0]])
+// RV32ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ cl

[PATCH] D121915: [RISCV] CLZ Instruction

2022-04-11 Thread Chang Hu via Phabricator via cfe-commits 
joker881 updated this revision to Diff 421931.
joker881 added a comment.
Herald added subscribers: sunshaoce, StephenFan.

[RISCV]CLZ instruction


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121915/new/

https://reviews.llvm.org/D121915

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -25,3 +25,28 @@
 long orc_b_64(long a) {
   return __builtin_riscv_orc_b_64(a);
 }
+
+
+// RV64ZBB-LABEL: @clz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.clz.i32(i32 [[TMP0]])
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
+
+// RV64ZBB-LABEL: @clz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.riscv.clz.i64(i64 [[TMP0]])
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long clz_64(long a) {
+  return __builtin_riscv_clz_64(a);
+}
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -13,3 +13,14 @@
 int orc_b_32(int a) {
   return __builtin_riscv_orc_b_32(a);
 }
+// RV32ZBB-LABEL: @clz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.clz.i32(i32 [[TMP0]])
+// RV32ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18906,7 +18906,11 @@
 case RISCV::BI__builtin_riscv_orc_b_64:
   ID = Intrinsic::riscv_orc_b;
   break;
-
+case RISCV::BI__builtin_riscv_clz_32:
+case RISCV::BI__builtin_riscv_clz_64:{
+  Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
+  return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+  }
 // Zbc
 case RISCV::BI__builtin_riscv_clmul:
   ID = Intrinsic::riscv_clmul;
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,7 +18,8 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
-
+TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")
 TARGET_BUILTIN(__builtin_riscv_clmulh, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -25,3 +25,28 @@
 long orc_b_64(long a) {
   return __builtin_riscv_orc_b_64(a);
 }
+
+
+// RV64ZBB-LABEL: @clz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.riscv.clz.i32(i32 [[TMP0]])
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
+
+// RV64ZBB-LABEL: @clz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.riscv.clz.i64(i64 [[TMP0]])
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long clz_64(long a) {
+  return __builtin_riscv_clz_64(a);
+}
Index: clang/test/CodeGen/RISCV/rvb-in

[PATCH] D121915: [RISCV] CLZ Instruction

2022-04-13 Thread Chang Hu via Phabricator via cfe-commits 
joker881 added a comment.

wait ,It seems the format problem have not solved,sorry


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121915/new/

https://reviews.llvm.org/D121915

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[PATCH] D121915: [RISCV] CLZ Instruction

2022-04-13 Thread Chang Hu via Phabricator via cfe-commits 
joker881 updated this revision to Diff 422487.
joker881 added a comment.

upadated test files, fixed the format problem


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121915/new/

https://reviews.llvm.org/D121915

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -25,3 +25,27 @@
 long orc_b_64(long a) {
   return __builtin_riscv_orc_b_64(a);
 }
+
+// RV64ZBB-LABEL: @clz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
+
+// RV64ZBB-LABEL: @clz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long clz_64(long a) {
+  return __builtin_riscv_clz_64(a);
+}
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -13,3 +13,15 @@
 int orc_b_32(int a) {
   return __builtin_riscv_orc_b_32(a);
 }
+
+// RV32ZBB-LABEL: @clz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
+// RV32ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
\ No newline at end of file
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18861,6 +18861,8 @@
   default: llvm_unreachable("unexpected builtin ID");
   case RISCV::BI__builtin_riscv_orc_b_32:
   case RISCV::BI__builtin_riscv_orc_b_64:
+  case RISCV::BI__builtin_riscv_clz_32:
+  case RISCV::BI__builtin_riscv_clz_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
@@ -18906,6 +18908,11 @@
 case RISCV::BI__builtin_riscv_orc_b_64:
   ID = Intrinsic::riscv_orc_b;
   break;
+case RISCV::BI__builtin_riscv_clz_32:
+case RISCV::BI__builtin_riscv_clz_64: {
+  Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
+  return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+}
 
 // Zbc
 case RISCV::BI__builtin_riscv_clmul:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,6 +18,8 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -25,3 +25,27 @@
 long orc_b_64(long a) {
   return __builtin_riscv_orc_b_64(a);
 }
+
+// RV64ZBB-LABEL: @clz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
+
+// RV64ZBB-LABEL: @clz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]],

[PATCH] D121915: RISCV] Add clang builtins for CLZ instruction.

2022-04-13 Thread Chang Hu via Phabricator via cfe-commits 
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa4f47a99aafe: RISCV] Add clang builtins for CLZ instruction. 
(authored by joker881).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121915/new/

https://reviews.llvm.org/D121915

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -25,3 +25,27 @@
 long orc_b_64(long a) {
   return __builtin_riscv_orc_b_64(a);
 }
+
+// RV64ZBB-LABEL: @clz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
+
+// RV64ZBB-LABEL: @clz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.ctlz.i64(i64 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long clz_64(long a) {
+  return __builtin_riscv_clz_64(a);
+}
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -13,3 +13,15 @@
 int orc_b_32(int a) {
   return __builtin_riscv_orc_b_32(a);
 }
+
+// RV32ZBB-LABEL: @clz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 
false)
+// RV32ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
\ No newline at end of file
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18992,6 +18992,8 @@
   default: llvm_unreachable("unexpected builtin ID");
   case RISCV::BI__builtin_riscv_orc_b_32:
   case RISCV::BI__builtin_riscv_orc_b_64:
+  case RISCV::BI__builtin_riscv_clz_32:
+  case RISCV::BI__builtin_riscv_clz_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
@@ -19037,6 +19039,11 @@
 case RISCV::BI__builtin_riscv_orc_b_64:
   ID = Intrinsic::riscv_orc_b;
   break;
+case RISCV::BI__builtin_riscv_clz_32:
+case RISCV::BI__builtin_riscv_clz_64: {
+  Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
+  return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+}
 
 // Zbc
 case RISCV::BI__builtin_riscv_clmul:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,6 +18,8 @@
 // Zbb extension
 TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -25,3 +25,27 @@
 long orc_b_64(long a) {
   return __builtin_riscv_orc_b_64(a);
 }
+
+// RV64ZBB-LABEL: @clz_32(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+  return __builtin_riscv_clz_32(a);
+}
+
+// RV64ZBB-LABEL: @clz_64(
+// RV64ZBB

[PATCH] D124348: [1/2][RISCV]Add Intrinsics for B extension in Clang

2022-04-24 Thread Chang Hu via Phabricator via cfe-commits 
joker881 created this revision.
Herald added subscribers: sunshaoce, VincentWu, luke957, vkmr, frasercrmck, 
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zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
joker881 requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D124348

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  llvm/include/llvm/IR/IntrinsicsRISCV.td

Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -87,6 +87,14 @@
 
   // Zbb
   def int_riscv_orc_b : BitManipGPRIntrinsics;
+  def int_riscv_andn : BitManipGPRGPRGRIntrinsics;
+  def int_riscv_clzw : BitManipGPRIntrinsics;
+  def int_riscv_cpop : BitManipGPRIntrinsics;
+  def int_riscv_cpopw : BitManipGPRIntrinsics;
+  def int_riscv_ctz : BitManipGPRIntrinsics;
+  def int_riscv_max : BitManipGPRGPRIntrinsics;
+  def int_riscv_maxu : BitManipGPRGPRIntrinsics;
+  def int_riscv_orn : BitManipGPRGPRIntrinsics;
 
   // Zbc or Zbkc
   def int_riscv_clmul  : BitManipGPRGPRIntrinsics;
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18994,6 +18994,20 @@
   case RISCV::BI__builtin_riscv_orc_b_64:
   case RISCV::BI__builtin_riscv_clz_32:
   case RISCV::BI__builtin_riscv_clz_64:
+  case RISCV::BI__builtin_riscv_andn_32:
+  case RISCV::BI__builtin_riscv_andn_64:
+  case RISCV::BI__builtin_riscv_clzw_64:
+  case RISCV::BI__builtin_riscv_cpop_32:
+  case RISCV::BI__builtin_riscv_cpop_64:
+  case RISCV::BI__builtin_riscv_cpopw_64:
+  case RISCV::BI__builtin_riscv_ctz_32:
+  case RISCV::BI__builtin_riscv_ctz_64:
+  case RISCV::BI__builtin_riscv_max_32:
+  case RISCV::BI__builtin_riscv_max_64:
+  case RISCV::BI__builtin_riscv_maxu_32:
+  case RISCV::BI__builtin_riscv_maxu_64:
+  case RISCV::BI__builtin_riscv_orn_32:
+  case RISCV::BI__builtin_riscv_orn_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
@@ -19044,6 +19058,36 @@
   Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
   return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
 }
+case RISCV::BI__builtin_riscv_andn_32:
+case RISCV::BI__builtin_riscv_andn_64:
+  ID = Intrinsic::riscv_andn;
+  break;
+case RISCV::BI__builtin_riscv_clzw_64:
+  ID = Intrinsic::riscv_clzw;
+  break;
+case RISCV::BI__builtin_riscv_cpop_32:
+case RISCV::BI__builtin_riscv_cpop_64:
+  ID = Intrinsic::riscv_cpop;
+  break;
+case RISCV::BI__builtin_riscv_cpopw_64:
+  ID = Intrinsic::riscv_cpopw;
+  break;
+case RISCV::BI__builtin_riscv_ctz_32:
+case RISCV::BI__builtin_riscv_ctz_64:
+  ID = Intrinsic::riscv_ctz;
+  break;
+case RISCV::BI__builtin_riscv_max_32:
+case RISCV::BI__builtin_riscv_max_64:
+  ID = Intrinsic::riscv_max;
+  break;
+case RISCV::BI__builtin_riscv_maxu_32:
+case RISCV::BI__builtin_riscv_maxu_64:
+  ID = Intrinsic::riscv_maxu;
+  break;
+case RISCV::BI__builtin_riscv_orn_32:
+case RISCV::BI__builtin_riscv_orn_64:
+  ID = Intrinsic::riscv_orn;
+  break;
 
 // Zbc
 case RISCV::BI__builtin_riscv_clmul:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -20,6 +20,21 @@
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
 TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_andn_32, "ZiZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_andn_64, "WiWiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clzw_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_cpop_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_cpop_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_cpopw_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctzw_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_max_32, "ZiZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_max_64, "WiWiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_maxu_32, "ZiZiZi", "nc", "zbb")
+TARGET_BUILT

[PATCH] D124348: [1/2][RISCV]Add Intrinsics for B extension in Clang

2022-04-25 Thread Chang Hu via Phabricator via cfe-commits 
joker881 added a comment.

In D124348#3470612 , @craig.topper 
wrote:

> The "B extension" terminology no longer exists.

Thank you for your comments. I will consider them carefully. And I want to know 
that do you have any documents about intrinsic of bitmanip extension, like 
RISC-V Vector Extension Intrinsic Document.


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[PATCH] D124348: [1/2][RISCV]Add Intrinsics for B extension in Clang

2022-04-28 Thread Chang Hu via Phabricator via cfe-commits 
joker881 added a comment.

In D124348#3470612 , @craig.topper 
wrote:

> The "B extension" terminology no longer exists.

And I decide to ctz_32 and ctz_64 like clz.


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[PATCH] D124348: [1/2][RISCV]Add Intrinsics for B extension in Clang

2022-04-28 Thread Chang Hu via Phabricator via cfe-commits 
joker881 updated this revision to Diff 425793.
joker881 added a comment.

Implement intrinsic ctz for bitmanip extension


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124348/new/

https://reviews.llvm.org/D124348

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -48,4 +48,16 @@
 //
 long clz_64(long a) {
   return __builtin_riscv_clz_64(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long clz_64(long a) {
+  return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -24,4 +24,16 @@
 //
 int clz_32(int a) {
   return __builtin_riscv_clz_32(a);
+}
+
+// RV32ZBB-LABEL: @ctz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
+// RV32ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19012,6 +19012,8 @@
   case RISCV::BI__builtin_riscv_orc_b_64:
   case RISCV::BI__builtin_riscv_clz_32:
   case RISCV::BI__builtin_riscv_clz_64:
+  case RISCV::BI__builtin_riscv_ctz_32:
+  case RISCV::BI__builtin_riscv_ctz_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
@@ -19062,6 +19064,11 @@
   Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
   return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
 }
+case RISCV::BI__builtin_riscv_ctz_32:
+case RISCV::BI__builtin_riscv_ctz_64: {
+  Function *F = CGM.getIntrinsic(Intrinsic::cttz, Ops[0]->getType());
+  return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+}
 
 // Zbc
 case RISCV::BI__builtin_riscv_clmul:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -20,6 +20,8 @@
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
 TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -48,4 +48,16 @@
 //
 long clz_64(long a) {
   return __builtin_riscv_clz_64(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long clz_64(long a) {
+  return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -24,4 +24,16 @@
 //
 int clz_32(int a) {
   return __builtin_riscv_clz_32(a);
+}
+
+// RV32ZBB-LABEL: @ctz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [

[PATCH] D124348: [RISCV]Add CTZ Intrinsic for ZBB in Clang

2022-04-29 Thread Chang Hu via Phabricator via cfe-commits 
joker881 updated this revision to Diff 426187.
joker881 added a comment.

update test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124348/new/

https://reviews.llvm.org/D124348

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -48,4 +48,16 @@
 //
 long clz_64(long a) {
   return __builtin_riscv_clz_64(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long ctz_64(long a) {
+  return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -24,4 +24,16 @@
 //
 int clz_32(int a) {
   return __builtin_riscv_clz_32(a);
+}
+
+// RV32ZBB-LABEL: @ctz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
+// RV32ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19012,6 +19012,8 @@
   case RISCV::BI__builtin_riscv_orc_b_64:
   case RISCV::BI__builtin_riscv_clz_32:
   case RISCV::BI__builtin_riscv_clz_64:
+  case RISCV::BI__builtin_riscv_ctz_32:
+  case RISCV::BI__builtin_riscv_ctz_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
@@ -19062,6 +19064,11 @@
   Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
   return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
 }
+case RISCV::BI__builtin_riscv_ctz_32:
+case RISCV::BI__builtin_riscv_ctz_64: {
+  Function *F = CGM.getIntrinsic(Intrinsic::cttz, Ops[0]->getType());
+  return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+}
 
 // Zbc
 case RISCV::BI__builtin_riscv_clmul:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -20,6 +20,8 @@
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
 TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -48,4 +48,16 @@
 //
 long clz_64(long a) {
   return __builtin_riscv_clz_64(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long ctz_64(long a) {
+  return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -24,4 +24,16 @@
 //
 int clz_32(int a) {
   return __builtin_riscv_clz_32(a);
+}
+
+// RV32ZBB-LABEL: @ctz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4

[PATCH] D124348: [RISCV]Add CTZ Intrinsic for ZBB in Clang

2022-04-29 Thread Chang Hu via Phabricator via cfe-commits 
This revision was automatically updated to reflect the committed changes.
Closed by commit rG19978e08749f: [RISCV]Add CTZ Intrinsic for ZBB in Clang 
(authored by joker881).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124348/new/

https://reviews.llvm.org/D124348

Files:
  clang/include/clang/Basic/BuiltinsRISCV.def
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
  clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -48,4 +48,16 @@
 //
 long clz_64(long a) {
   return __builtin_riscv_clz_64(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 
false)
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long ctz_64(long a) {
+  return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -24,4 +24,16 @@
 //
 int clz_32(int a) {
   return __builtin_riscv_clz_32(a);
+}
+
+// RV32ZBB-LABEL: @ctz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT:store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT:[[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 
false)
+// RV32ZBB-NEXT:ret i32 [[TMP1]]
+//
+int ctz_32(int a) {
+  return __builtin_riscv_ctz_32(a);
 }
\ No newline at end of file
Index: clang/lib/CodeGen/CGBuiltin.cpp
===
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -19024,6 +19024,8 @@
   case RISCV::BI__builtin_riscv_orc_b_64:
   case RISCV::BI__builtin_riscv_clz_32:
   case RISCV::BI__builtin_riscv_clz_64:
+  case RISCV::BI__builtin_riscv_ctz_32:
+  case RISCV::BI__builtin_riscv_ctz_64:
   case RISCV::BI__builtin_riscv_clmul:
   case RISCV::BI__builtin_riscv_clmulh:
   case RISCV::BI__builtin_riscv_clmulr:
@@ -19074,6 +19076,11 @@
   Function *F = CGM.getIntrinsic(Intrinsic::ctlz, Ops[0]->getType());
   return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
 }
+case RISCV::BI__builtin_riscv_ctz_32:
+case RISCV::BI__builtin_riscv_ctz_64: {
+  Function *F = CGM.getIntrinsic(Intrinsic::cttz, Ops[0]->getType());
+  return Builder.CreateCall(F, {Ops[0], Builder.getInt1(false)});
+}
 
 // Zbc
 case RISCV::BI__builtin_riscv_clmul:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -20,6 +20,8 @@
 TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
 TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb")
 TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_ctz_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_ctz_64, "WiWi", "nc", "zbb,64bit")
 
 // Zbc or Zbkc extension
 TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")


Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -48,4 +48,16 @@
 //
 long clz_64(long a) {
   return __builtin_riscv_clz_64(a);
+}
+
+// RV64ZBB-LABEL: @ctz_64(
+// RV64ZBB-NEXT:  entry:
+// RV64ZBB-NEXT:[[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT:store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT:[[TMP1:%.*]] = call i64 @llvm.cttz.i64(i64 [[TMP0]], i1 false)
+// RV64ZBB-NEXT:ret i64 [[TMP1]]
+//
+long ctz_64(long a) {
+  return __builtin_riscv_ctz_64(a);
 }
\ No newline at end of file
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -24,4 +24,16 @@
 //
 int clz_32(int a) {
   return __builtin_riscv_clz_32(a);
+}
+
+// RV32ZBB-LABEL: @ctz_32(
+// RV32ZBB-NEXT:  entry:
+// RV32ZBB-NEXT:[[A_ADDR:%.*]] =

[PATCH] D98922: Delete Redundant parameters in clang/unittests/AST/CMakeLists.txt

2021-03-18 Thread Chang Hu via Phabricator via cfe-commits 
joker881 created this revision.
joker881 added a reviewer: Jessica.
Herald added a subscriber: mgorny.
joker881 requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

There is a redundant ASTTraverserTest.cpp in “clang/unittests/AST/ 
CMakeLists.txt”


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D98922

Files:
  clang/unittests/AST/CMakeLists.txt


Index: clang/unittests/AST/CMakeLists.txt
===
--- clang/unittests/AST/CMakeLists.txt
+++ clang/unittests/AST/CMakeLists.txt
@@ -13,7 +13,6 @@
   ASTImporterVisibilityTest.cpp
   ASTTraverserTest.cpp
   ASTTypeTraitsTest.cpp
-  ASTTraverserTest.cpp
   ASTVectorTest.cpp
   CommentLexer.cpp
   CommentParser.cpp


Index: clang/unittests/AST/CMakeLists.txt
===
--- clang/unittests/AST/CMakeLists.txt
+++ clang/unittests/AST/CMakeLists.txt
@@ -13,7 +13,6 @@
   ASTImporterVisibilityTest.cpp
   ASTTraverserTest.cpp
   ASTTypeTraitsTest.cpp
-  ASTTraverserTest.cpp
   ASTVectorTest.cpp
   CommentLexer.cpp
   CommentParser.cpp
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