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clz
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D121915
Files:
clang/include/clang/Basic/BuiltinsRISCV.def
clang/lib/CodeGen/CGBuiltin.cpp
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
llvm/include/llvm/IR/IntrinsicsRISCV.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
Index: llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv64zbb-intrinsic.ll
@@ -54,3 +54,14 @@
%tmp = call i64 @llvm.riscv.orc.b.i64(i64 %a)
ret i64 %tmp
}
+
+declare i64 @llvm.riscv.clz.i64(i64)
+
+define i64 @clz64(i64 %a) nounwind {
+; RV64ZBB-LABEL: clz64:
+; RV64ZBB: # %bb.0:
+; RV64ZBB-NEXT: clz a0, a0
+; RV64ZBB-NEXT: ret
+ %tmp = call i64 @llvm.riscv.clz.i64(i64 %a)
+ ret i64 %tmp
+}
Index: llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
+++ llvm/test/CodeGen/RISCV/rv32zbb-intrinsic.ll
@@ -12,3 +12,13 @@
%tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a)
ret i32 %tmp
}
+declare i32 @llvm.riscv.clz.i32(i32)
+
+define i32 @clz(i32 %a) nounwind {
+; RV32ZBB-LABEL: clz:
+; RV32ZBB: # %bb.0:
+; RV32ZBB-NEXT: clz a0, a0
+; RV32ZBB-NEXT: ret
+ %tmp = call i32 @llvm.riscv.clz.i32(i32 %a)
+ ret i32 %tmp
+}
Index: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1213,3 +1213,7 @@
def : PatGprGpr<int_riscv_xperm4, XPERM4>;
def : PatGprGpr<int_riscv_xperm8, XPERM8>;
}
+let Predicates = [HasStdExtZbb] in {
+def : PatGpr<int_riscv_clz, CLZ>;
+}
+
Index: llvm/include/llvm/IR/IntrinsicsRISCV.td
===================================================================
--- llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -87,6 +87,7 @@
// Zbb
def int_riscv_orc_b : BitManipGPRIntrinsics;
+ def int_riscv_clz : BitManipGPRIntrinsics;
// Zbc or Zbkc
def int_riscv_clmul : BitManipGPRGPRIntrinsics;
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv64-zbb.c
@@ -25,3 +25,27 @@
long orc_b_64(long a) {
return __builtin_riscv_orc_b_64(a);
}
+
+// RV64ZBB-LABEL: @clz_32(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV64ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.clz.i32(i32 [[TMP0]])
+// RV64ZBB-NEXT: ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+ return __builtin_riscv_clz_32(a);
+}
+
+// RV64ZBB-LABEL: @clz_64(
+// RV64ZBB-NEXT: entry:
+// RV64ZBB-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
+// RV64ZBB-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
+// RV64ZBB-NEXT: [[TMP1:%.*]] = call i64 @llvm.riscv.clz.i64(i64 [[TMP0]])
+// RV64ZBB-NEXT: ret i64 [[TMP1]]
+//
+long clz_64(long a) {
+ return __builtin_riscv_clz_64(a);
+}
Index: clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
===================================================================
--- clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
+++ clang/test/CodeGen/RISCV/rvb-intrinsics/riscv32-zbb.c
@@ -13,3 +13,14 @@
int orc_b_32(int a) {
return __builtin_riscv_orc_b_32(a);
}
+// RV32ZBB-LABEL: @clz_32(
+// RV32ZBB-NEXT: entry:
+// RV32ZBB-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
+// RV32ZBB-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
+// RV32ZBB-NEXT: [[TMP1:%.*]] = call i32 @llvm.riscv.clz.i32(i32 [[TMP0]])
+// RV32ZBB-NEXT: ret i32 [[TMP1]]
+//
+int clz_32(int a) {
+ return __builtin_riscv_clz_32(a);
+}
Index: clang/lib/CodeGen/CGBuiltin.cpp
===================================================================
--- clang/lib/CodeGen/CGBuiltin.cpp
+++ clang/lib/CodeGen/CGBuiltin.cpp
@@ -18799,6 +18799,8 @@
default: llvm_unreachable("unexpected builtin ID");
case RISCV::BI__builtin_riscv_orc_b_32:
case RISCV::BI__builtin_riscv_orc_b_64:
+ case RISCV::BI__builtin_riscv_clz_32:
+ case RISCV::BI__builtin_riscv_clz_64:
case RISCV::BI__builtin_riscv_clmul:
case RISCV::BI__builtin_riscv_clmulh:
case RISCV::BI__builtin_riscv_clmulr:
@@ -18844,6 +18846,10 @@
case RISCV::BI__builtin_riscv_orc_b_64:
ID = Intrinsic::riscv_orc_b;
break;
+ case RISCV::BI__builtin_riscv_clz_32:
+ case RISCV::BI__builtin_riscv_clz_64:
+ ID = Intrinsic::riscv_clz;
+ break;
// Zbc
case RISCV::BI__builtin_riscv_clmul:
Index: clang/include/clang/Basic/BuiltinsRISCV.def
===================================================================
--- clang/include/clang/Basic/BuiltinsRISCV.def
+++ clang/include/clang/Basic/BuiltinsRISCV.def
@@ -18,6 +18,8 @@
// Zbb extension
TARGET_BUILTIN(__builtin_riscv_orc_b_32, "ZiZi", "nc", "zbb")
TARGET_BUILTIN(__builtin_riscv_orc_b_64, "WiWi", "nc", "zbb,64bit")
+TARGET_BUILTIN(__builtin_riscv_clz_32, "ZiZi", "nc", "zbb")
+TARGET_BUILTIN(__builtin_riscv_clz_64, "WiWi", "nc", "zbb,64bit")
// Zbc or Zbkc extension
TARGET_BUILTIN(__builtin_riscv_clmul, "LiLiLi", "nc", "zbc|zbkc")
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