from:"Brandon Wu via Phabricator via cfe\-commits"

[PATCH] D122370: Split up large test files under clang/test/CodeGen/RISCV

2022-03-23 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: s, VincentWu, luke957, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

The llvm pre-merge test got timeout due to large test files, this commit
split up some files based on "element width(EEW)" under clang/test/CodeGen/RISCV
into even smaller ones.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122370

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei_ei32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei_ei64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxei_ei8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_ei32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_ei64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_ei8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_ei32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_ei64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_ei8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf_ei32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf_ei64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf_ei8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf_ei32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf_ei64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf_ei8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_e16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_e32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_e64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_e8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask_e16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask_e32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask_e64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask_e8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_e16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_e32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_e64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_e8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask_e16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask_e32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask_e64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask_e8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg_e16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg_e32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg_e64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsseg_e8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei_ei32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei_ei64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxei_ei8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_ei32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_ei64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_ei8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_ei32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_ei64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_ei8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf_ei32.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf_ei64.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf_ei8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf_ei16.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf_ei32.c

[PATCH] D122370: Split up large test files under clang/test/CodeGen/RISCV

2022-03-23 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

In D122370#3404590 , @MaskRay wrote:

> I assume this is to improve test parallelism. Do you have runtime comparison?

actually, this is to prevent single file from timeout due to many test cases, 
such as https://reviews.llvm.org/D122205#3403925


Repository:
  rG LLVM Github Monorepo

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[PATCH] D122370: Split up large test files under clang/test/CodeGen/RISCV

2022-03-28 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

In D122370#3412522 , @luismarques 
wrote:

> What's the timeout value that is being exceeded?

I guess it’s 60 seconds?


Repository:
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[PATCH] D121431: Split up large test files(over 10k lines) under clang/test/CodeGen/RISCV including:

2022-03-10 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, kito-cheng, niosHD, sabuasal, simoncook, 
johnrusso, rbar, asb.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

The llvm pre-merge test got timeout due to large test files, this commit
split up the files that have over 10k lines under clang/test/CodeGen/RISCV
into even smaller ones.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D121431

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg_mask.c

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[PATCH] D121431: Split up large test files(over 10k lines) under clang/test/CodeGen/RISCV including:

2022-03-10 Thread Brandon Wu via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG25df633c243f: Split up large test files(over 10k lines) 
under clang/test/CodeGen/RISCV… (authored by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D121431/new/

https://reviews.llvm.org/D121431

Files:
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsoxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vsuxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vloxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vlsegff_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mask_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vluxseg_mf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsoxseg_mask.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsuxseg_mask.c

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[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2022-12-19 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 483884.
4vtomat added a comment.

Address most of Eric's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/rv64zvkb.s
  llvm/test/MC/RISCV/rvv/rv64zvkg.s
  llvm/test/MC/RISCV/rvv/rv64zvknha.s
  llvm/test/MC/RISCV/rvv/rv64zvknhb.s
  llvm/test/MC/RISCV/rvv/rv64zvkns.s
  llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksed.s
  llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksh.s

Index: llvm/test/MC/RISCV/rvv/rv64zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/rv64zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
Index: llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vaeskf1.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [1, 10]
+
+vaeskf2.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [2, 14]
Index: llvm/test/MC/RISCV/rvv/rv64zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns.s
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| Fi

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2022-12-19 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 484154.
4vtomat marked 22 inline comments as done.
4vtomat added a comment.

Replace llvm/test/MC/RISCV/rvv/rv64zvknhb.s and 
llvm/test/MC/RISCV/rvv/rv64zvknhb.s with a single 
llvm/test/MC/RISCV/rvv/rv64zvknh.s


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/rv64zvkb.s
  llvm/test/MC/RISCV/rvv/rv64zvkg.s
  llvm/test/MC/RISCV/rvv/rv64zvknh.s
  llvm/test/MC/RISCV/rvv/rv64zvkns.s
  llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksed.s
  llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksh.s

Index: llvm/test/MC/RISCV/rvv/rv64zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/rv64zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
Index: llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vaeskf1.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [1, 10]
+
+vaeskf2.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [2, 14]
Index: llvm/test/MC/RISCV/rvv/rv64zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns.s
@@ -0,0 +1,75 @@
+# RUN: l

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2022-12-20 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 484217.
4vtomat added a comment.

Update to final draft 20221208


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/rv64zvkb.s
  llvm/test/MC/RISCV/rvv/rv64zvkg.s
  llvm/test/MC/RISCV/rvv/rv64zvknh.s
  llvm/test/MC/RISCV/rvv/rv64zvkns.s
  llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksed.s
  llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksh.s

Index: llvm/test/MC/RISCV/rvv/rv64zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed_invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/rv64zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vaeskf1.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [1, 10]
+
+vaeskf2.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [2, 14]
Index: llvm/test/MC/RISCV/rvv/rv64zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2022-12-20 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 484224.
4vtomat added a comment.

Address Eop's comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/rv64zvkb.s
  llvm/test/MC/RISCV/rvv/rv64zvkg.s
  llvm/test/MC/RISCV/rvv/rv64zvknh.s
  llvm/test/MC/RISCV/rvv/rv64zvkns.s
  llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksed.s
  llvm/test/MC/RISCV/rvv/rv64zvksh.s

Index: llvm/test/MC/RISCV/rvv/rv64zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/rv64zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/rv64zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vaeskf1.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [1, 10]
+
+vaeskf2.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [2, 14]
Index: llvm/test/MC/RISCV/rvv/rv64zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zv

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2022-12-20 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 484226.
4vtomat added a comment.

Correct OPERAND_LAST_RISCV_IMM in OperandType


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/rv64zvkb.s
  llvm/test/MC/RISCV/rvv/rv64zvkg.s
  llvm/test/MC/RISCV/rvv/rv64zvknh.s
  llvm/test/MC/RISCV/rvv/rv64zvkns.s
  llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/rv64zvksed.s
  llvm/test/MC/RISCV/rvv/rv64zvksh.s

Index: llvm/test/MC/RISCV/rvv/rv64zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/rv64zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/rv64zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns_invalid.s
@@ -0,0 +1,8 @@
+# RUN: not llvm-mc -triple=riscv64 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vaeskf1.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [1, 10]
+
+vaeskf2.vi v10, v9, 0
+# CHECK-ERROR: immediate must be an integer in the range [2, 14]
Index: llvm/test/MC/RISCV/rvv/rv64zvkns.s
===
--- /dev/null
+++ llvm/t

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2023-01-03 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 486169.
4vtomat added a comment.

Address Eric's comments!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvkns-invalid.s
  llvm/test/MC/RISCV/rvv/zvkns.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkns.s
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkns  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# R

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

2023-01-31 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 493826.
4vtomat added a comment.

NFC, some indentation fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141672/new/

https://reviews.llvm.org/D141672

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvkns-invalid.s
  llvm/test/MC/RISCV/rvv/zvkns.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkns.s
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkns  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+#

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2023-01-13 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 488916.
4vtomat marked 8 inline comments as done.
4vtomat added a comment.

[NFC] Refactor the code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvkns-invalid.s
  llvm/test/MC/RISCV/rvv/zvkns.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkns.s
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkns  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zv

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2023-01-13 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 488918.
4vtomat added a comment.

NFC


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvkns-invalid.s
  llvm/test/MC/RISCV/rvv/zvkns.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkns.s
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkns  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| llvm-obj

[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2023-01-13 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 488924.
4vtomat added a comment.

NFC, refactoring the code.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvkns-invalid.s
  llvm/test/MC/RISCV/rvv/zvkns.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkns.s
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkns  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkns %s \
+#

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

2023-01-13 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, jdoerfert, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

LLVM implements the 0.1 draft specification:
https://github.com/riscv/riscv-crypto/releases/download/v20221220/riscv-crypto-spec-vector.pdf
, and current vector crypto extension version can be found in:
https://github.com/riscv/riscv-crypto.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141672

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvkns-invalid.s
  llvm/test/MC/RISCV/rvv/zvkns.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

2023-01-13 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

Since there's some accidentally pushed code. The old revision is moved to this 
one, sorry..


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141672/new/

https://reviews.llvm.org/D141672

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[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

2023-09-18 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 556995.
4vtomat added a comment.

Add VRM2, VRM4 and VRM8 to CalleeSaved register list.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154576/new/

https://reviews.llvm.org/D154576

Files:
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/Specifiers.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
  clang/test/CodeGen/RISCV/riscv-vector-callingconv.cpp
  llvm/include/llvm/AsmParser/LLToken.h
  llvm/include/llvm/IR/CallingConv.h
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/Target/RISCV/RISCVCallingConv.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll

Index: llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
@@ -0,0 +1,95 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+m -mattr=+v -O2 < %s \
+; RUN:| FileCheck --check-prefix=SPILL-O2 %s
+
+define  @test_vector_std( %va) nounwind {
+; SPILL-O2-LABEL: test_vector_std:
+; SPILL-O2:   # %bb.0: # %entry
+; SPILL-O2-NEXT:addi sp, sp, -16
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 1
+; SPILL-O2-NEXT:sub sp, sp, a0
+; SPILL-O2-NEXT:addi a0, sp, 16
+; SPILL-O2-NEXT:vs1r.v v8, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:#APP
+; SPILL-O2-NEXT:#NO_APP
+; SPILL-O2-NEXT:vl1r.v v8, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 1
+; SPILL-O2-NEXT:add sp, sp, a0
+; SPILL-O2-NEXT:addi sp, sp, 16
+; SPILL-O2-NEXT:ret
+entry:
+  call void asm sideeffect "",
+  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
+
+  ret  %va
+}
+
+define riscv_vector_cc  @test_vector_callee( %va) nounwind {
+; SPILL-O2-LABEL: test_vector_callee:
+; SPILL-O2:   # %bb.0: # %entry
+; SPILL-O2-NEXT:addi sp, sp, -16
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 4
+; SPILL-O2-NEXT:sub sp, sp, a0
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a1, a0, 4
+; SPILL-O2-NEXT:sub a0, a1, a0
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v1, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 13
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs2r.v v2, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a1, a0, 3
+; SPILL-O2-NEXT:add a0, a1, a0
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs4r.v v4, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs8r.v v24, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:addi a0, sp, 16
+; SPILL-O2-NEXT:vs1r.v v8, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:#APP
+; SPILL-O2-NEXT:#NO_APP
+; SPILL-O2-NEXT:vl1r.v v8, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a1, a0, 4
+; SPILL-O2-NEXT:sub a0, a1, a0
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vl1r.v v1, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 13
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vl2r.v v2, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a1, a0, 3
+; SPILL-O2-NEXT:add a0, a1, a0
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vl4r.v v4, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vl8r.v v24, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 4
+; SPILL-O2-NEXT:add sp, sp, a0
+; SPILL-O2-NEXT:addi sp, sp, 16
+; SPILL-O2-NEXT:

[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

2023-09-19 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added inline comments.

Comment at: llvm/lib/Target/RISCV/RISCVCallingConv.td:52
 // Same as CSR_Interrupt, but including all 64-bit FP registers.
 def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add CSR_Interrupt,
  (sequence "F%u_D", 0, 31))>;

wangpc wrote:
> Should we add CSRs for interrupt functions? And Should we save `vtype`, 
> `vstart`, `vxrm`, `vxsat`, etc. registers?
Yeah, we should also handle these in interrupt function, but seems it's not 
related to this patch. Am I right? @kito-cheng

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[PATCH] D156223: [RISCV] Resolve a few bugs in RISCVVIntrinsicUtils.cpp

2023-07-25 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay.
Herald added a project: clang.

This patch does a few things:

1. Add a new type called Undefined to ScalarTypeKind.
2. Make RVVType::applyModifier early return when encounter invalid ScalarType, 
otherwise it could be modified to "non-invalid" type in the following code.
3. When FixedLMULType::SmallerThan is applied, the lmul should be "<" than 
specified one, so lmuls which are ">=" should be marked as invalid.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156223

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -742,6 +742,10 @@
 break;
   }
 
+  // Early return if the current type modifier is already invalid.
+  if (ScalarType == Invalid)
+return;
+
   for (unsigned TypeModifierMaskShift = 0;
TypeModifierMaskShift <= static_cast(TypeModifier::MaxOffset);
++TypeModifierMaskShift) {
@@ -803,13 +807,13 @@
 void RVVType::applyFixedLog2LMUL(int Log2LMUL, enum FixedLMULType Type) {
   switch (Type) {
   case FixedLMULType::LargerThan:
-if (Log2LMUL < LMUL.Log2LMUL) {
+if (Log2LMUL <= LMUL.Log2LMUL) {
   ScalarType = ScalarTypeKind::Invalid;
   return;
 }
 break;
   case FixedLMULType::SmallerThan:
-if (Log2LMUL > LMUL.Log2LMUL) {
+if (Log2LMUL >= LMUL.Log2LMUL) {
   ScalarType = ScalarTypeKind::Invalid;
   return;
 }
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -133,6 +133,7 @@
 }
 break;
   case Invalid:
+  case Undefined:
 llvm_unreachable("Unhandled type.");
   }
   if (Type->isVector()) {
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -218,6 +218,7 @@
   UnsignedInteger,
   Float,
   Invalid,
+  Undefined,
 };
 
 // Exponential LMUL
@@ -240,7 +241,7 @@
   friend class RVVTypeCache;
 
   BasicType BT;
-  ScalarTypeKind ScalarType = Invalid;
+  ScalarTypeKind ScalarType = Undefined;
   LMULType LMUL;
   bool IsPointer = false;
   // IsConstant indices are "int", but have the constant expression.


Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -742,6 +742,10 @@
 break;
   }
 
+  // Early return if the current type modifier is already invalid.
+  if (ScalarType == Invalid)
+return;
+
   for (unsigned TypeModifierMaskShift = 0;
TypeModifierMaskShift <= static_cast(TypeModifier::MaxOffset);
++TypeModifierMaskShift) {
@@ -803,13 +807,13 @@
 void RVVType::applyFixedLog2LMUL(int Log2LMUL, enum FixedLMULType Type) {
   switch (Type) {
   case FixedLMULType::LargerThan:
-if (Log2LMUL < LMUL.Log2LMUL) {
+if (Log2LMUL <= LMUL.Log2LMUL) {
   ScalarType = ScalarTypeKind::Invalid;
   return;
 }
 break;
   case FixedLMULType::SmallerThan:
-if (Log2LMUL > LMUL.Log2LMUL) {
+if (Log2LMUL >= LMUL.Log2LMUL) {
   ScalarType = ScalarTypeKind::Invalid;
   return;
 }
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -133,6 +133,7 @@
 }
 break;
   case Invalid:
+  case Undefined:
 llvm_unreachable("Unhandled type.");
   }
   if (Type->isVector()) {
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -218,6 +218,7 @@
   UnsignedInteger,
   Float,
   Invalid,
+  Undefined,
 };
 
 // Exponential LMUL
@@ -240,7 +241,7 @@
   friend class RVVTypeCache;
 
   BasicType BT;
-  ScalarTypeKind ScalarType = Invalid;
+  ScalarTypeKind ScalarType = Undefined;
   LMULType LMUL;
   bool IsPointer = false;
   // IsConstant indi

[PATCH] D156223: [RISCV] Resolve a few bugs in RISCVVIntrinsicUtils.cpp

2023-07-26 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 544254.
4vtomat added a comment.

Add a test case for invalid example.


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Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v_invalid.c


Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v_invalid.c
===
--- /dev/null
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v_invalid.c
@@ -0,0 +1,21 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +zvfh -disable-O0-optnone %s -fsyntax-only -verify
+
+#include 
+
+vuint64m2_t test_vlmul_trunc_v_u64m2_u64m2(vuint64m2_t op1) { // expected-note 
{{'test_vlmul_trunc_v_u64m2_u64m2' declared here}}
+  return __riscv_vlmul_trunc_v_u64m2_u64m2(op1); // expected-error {{call to 
undeclared function '__riscv_vlmul_trunc_v_u64m2_u64m2'; ISO C99 and later do 
not support implicit function declarations}} expected-error {{returning 'int' 
from a function with incompatible result type 'vuint64m2_t' (aka 
'__rvv_uint64m2_t')}} expected-note {{did you mean 
'test_vlmul_trunc_v_u64m2_u64m2'?}}
+}
+
+vuint64m4_t test_vlmul_trunc_v_u64m4_u64m4(vuint64m4_t op1) { // expected-note 
{{'test_vlmul_trunc_v_u64m4_u64m4' declared here}}
+  return __riscv_vlmul_trunc_v_u64m4_u64m4(op1); // expected-error {{call to 
undeclared function '__riscv_vlmul_trunc_v_u64m4_u64m4'; ISO C99 and later do 
not support implicit function declarations}} expected-error {{returning 'int' 
from a function with incompatible result type 'vuint64m4_t' (aka 
'__rvv_uint64m4_t')}} expected-note {{did you mean 
'test_vlmul_trunc_v_u64m4_u64m4'?}}
+}
+
+vuint64m1_t test_vlmul_trunc_v_u64m1_u64m1(vuint64m1_t op1) { // expected-note 
{{'test_vlmul_trunc_v_u64m1_u64m1' declared here}}
+  return __riscv_vlmul_trunc_v_u64m1_u64m1(op1); // expected-error {{call to 
undeclared function '__riscv_vlmul_trunc_v_u64m1_u64m1'; ISO C99 and later do 
not support implicit function declarations}} expected-error {{returning 'int' 
from a function with incompatible result type 'vuint64m1_t' (aka 
'__rvv_uint64m1_t')}} expected-note {{did you mean 
'test_vlmul_trunc_v_u64m1_u64m1'?}}
+}
+
+vuint64m8_t test_vlmul_trunc_v_u64m8_u64m8(vuint64m8_t op1) { // expected-note 
{{'test_vlmul_trunc_v_u64m8_u64m8' declared here}}
+  return __riscv_vlmul_trunc_v_u64m8_u64m8(op1); // expected-error {{call to 
undeclared function '__riscv_vlmul_trunc_v_u64m8_u64m8'; ISO C99 and later do 
not support implicit function declarations}} expected-error {{returning 'int' 
from a function with incompatible result type 'vuint64m8_t' (aka 
'__rvv_uint64m8_t')}} expected-note {{did you mean 
'test_vlmul_trunc_v_u64m8_u64m8'?}}
+}
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -742,6 +742,10 @@
 break;
   }
 
+  // Early return if the current type modifier is already invalid.
+  if (ScalarType == Invalid)
+return;
+
   for (unsigned TypeModifierMaskShift = 0;
TypeModifierMaskShift <= static_cast(TypeModifier::MaxOffset);
++TypeModifierMaskShift) {
@@ -803,13 +807,13 @@
 void RVVType::applyFixedLog2LMUL(int Log2LMUL, enum FixedLMULType Type) {
   switch (Type) {
   case FixedLMULType::LargerThan:
-if (Log2LMUL < LMUL.Log2LMUL) {
+if (Log2LMUL <= LMUL.Log2LMUL) {
   ScalarType = ScalarTypeKind::Invalid;
   return;
 }
 break;
   case FixedLMULType::SmallerThan:
-if (Log2LMUL > LMUL.Log2LMUL) {
+if (Log2LMUL >= LMUL.Log2LMUL) {
   ScalarType = ScalarTypeKind::Invalid;
   return;
 }
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -133,6 +133,7 @@
 }
 break;
   case Invalid:
+  case Undefined:
 llvm_unreachable("Unhandled type.");
   }
   if (Type->isVector()) {
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -218,6 +218,7 @@
   UnsignedInteger,
   Float,
   Invalid,
+  Undefined,
 };
 
 // Exponential LMUL
@@ -240,7 +241,7 @@
   friend class RVVTypeCache;
 
   BasicType BT;
-  ScalarTypeKind ScalarType = Invalid;
+  ScalarTypeKind ScalarType = Undefined;
   LMULTy

[PATCH] D156223: [RISCV] Resolve a few bugs in RISCVVIntrinsicUtils.cpp

2023-07-26 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added inline comments.



Comment at: clang/lib/Sema/SemaRISCVVectorLookup.cpp:136
   case Invalid:
+  case Undefined:
 llvm_unreachable("Unhandled type.");

eopXD wrote:
> Could we just reuse `Invalid`?
We can't reuse Invalid, since `ScalarType` in `RVVType` class is default to 
`Invalid`, we are not able to determine whether it's really invalid or not 
during `applyModifier` function, so that's the reason why I added `Undefined` 
to differentiate between `default` and `really invalid`.


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-07-26 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 544624.
4vtomat marked 5 inline comments as done.
4vtomat added a comment.

After discusstion in 
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234,
we will have multiple lmuls for scalar type operands.
Currently the test cases for those instructions are only presented in vaesdf,
all other instructions test cases will be copied from rvv-intrinsic-doc once
they're ready.
Also added test case for sema checking for checking valid lmul.


Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Basic/riscv_vector_common.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8

[PATCH] D157651: [RISCV] Rewrite CheckInvalidVLENandLMUL to avoid floating point.

2023-08-11 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat accepted this revision.
4vtomat added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!




Comment at: clang/lib/Sema/SemaChecking.cpp:4484
+  unsigned EGS = EGW / ElemSize;
+  // If EGS is more than our minimum number of elements we're done.
+  if (EGS <= ElemCount)

Does the `EGS` here mean the `ElemCount`?
If it does, can we change the `EGS` in the comment to other name, since when I 
first see this comment, I just thought the `EGS` here means the argument name 
lol~


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[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-08-13 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

Ping


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[PATCH] D157474: [RISCV] Add missing Xsfvcp extension check in clang sema

2023-08-13 Thread Brandon Wu via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
4vtomat marked an inline comment as done.
Closed by commit rGa23d65ac89ce: [RISCV] Add missing Xsfvcp extension check in 
clang sema (authored by 4vtomat).

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Files:
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/rvv-required-features-invalid.c
  clang/test/Sema/rvv-required-features.c


Index: clang/test/Sema/rvv-required-features.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp 
%s -fsyntax-only -verify
+
+// expected-no-diagnostics
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t 
vl) {
+  return __riscv_vloxei64(base, bindex, vl);
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, 
size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl);
+}
+
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl);
+}
Index: clang/test/Sema/rvv-required-features-invalid.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features-invalid.c
@@ -0,0 +1,17 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v %s -fsyntax-only -verify
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t 
vl) {
+  return __riscv_vloxei64(base, bindex, vl); // expected-error {{call to 
undeclared function '__riscv_vloxei64'}} expected-error {{returning 'int' from 
a function with incompatible result type 'vint8m1_t'}}
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, 
size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl); // expected-error {{call to 
undeclared function '__riscv_vsoxei64'}}
+}
+
+void test_xsfvcp_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); // expected-error {{call to 
undeclared function '__riscv_sf_vc_x_se_u64m1'}}
+}
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -202,10 +202,20 @@
 void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
 ArrayRef Recs, IntrinsicKind K) {
   const TargetInfo &TI = Context.getTargetInfo();
-  bool HasRV64 = TI.hasFeature("64bit");
+  static const std::pair FeatureCheckList[] = {
+  {"64bit", RVV_REQ_RV64},
+  {"xsfvcp", RVV_REQ_Xsfvcp}};
+
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : Recs) {
+// Check requirements.
+if (llvm::any_of(FeatureCheckList, [&](const auto &Item) {
+  return (Record.RequiredExtensions & Item.second) == Item.second &&
+ !TI.hasFeature(Item.first);
+}))
+  continue;
+
 // Create Intrinsics for each type and LMUL.
 BasicType BaseType = BasicType::Unknown;
 ArrayRef BasicProtoSeq =
@@ -251,11 +261,6 @@
   if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
 continue;
 
-  // Check requirement.
-  if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) &&
-  !HasRV64)
-continue;
-
   // Expanded with different LMUL.
   for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
 if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3


Index: clang/test/Sema/rvv-required-features.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp %s -fsyntax-only -verify
+
+// expected-no-diagnostics
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
+  return __riscv_vloxei64(base, bindex, vl);
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl);
+}
+
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl);
+}
Index: clang/test/Sema/rvv-required-features-invalid.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features-invalid.c
@@ -0,0 +1,17 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v %s -fsyntax-only -verify
+
+#include 
+#include 
+
+vint8m1_t test_vlo

[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-08-14 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat marked 2 inline comments as done.
4vtomat added a comment.

In D146054#4586067 , @MaskRay wrote:

> I think the best place to test `RISCVISAInfo.cpp` is 
> `llvm/unittests/Support/RISCVISAInfoTest.cpp`.
>
> `clang/test/Driver/print-supported-extensions.c` can test just a few lines 
> (there will be some overlap with the testing in 
> `llvm/unittests/Support/RISCVISAInfoTest.cpp`), so that changes to RISC-V 
> extensions will generally not require updates to 
> `clang/test/Driver/print-supported-extensions.c`

The goal of this patch is to list the supported extensions and their versions 
by providing an option, so I guess 
`clang/test/Driver/print-supported-extensions.c` aims differently with 
`llvm/unittests/Support/RISCVISAInfoTest.cpp` which is testing the 
functionalities in `RISCVISAInfoTest.cpp`.
`clang/test/Driver/print-supported-extensions.c` only tracks the extensions 
added and the their version changes and `riscvExtensionsHelp` in 
`llvm/lib/Support/RISCVISAInfo.cpp` doesn't have any input or output as well as 
any side effect, it only reads `SupportedExtensions` and 
`SupportedExperimentalExtensions` and dump the information.
So I think `clang/test/Driver/print-supported-extensions.c` is enough for this 
patch?

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[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-08-14 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 550185.
4vtomat added a comment.

1. Apply clang-format for this patch
2. Replace FileCheck --implicit-check-not=warning: with %clang -Werror


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Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-extensions.c
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -208,6 +208,29 @@
 #endif
 }
 
+void llvm::riscvExtensionsHelp() {
+  outs() << "All available -march extensions for RISC-V\n\n";
+  outs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions)
+ExtMap[E.Name] = {E.Version.Major, E.Version.Minor};
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nUse -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -22,6 +22,8 @@
   unsigned MinorVersion;
 };
 
+void riscvExtensionsHelp();
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
Index: clang/tools/driver/cc1_main.cpp
===
--- clang/tools/driver/cc1_main.cpp
+++ clang/tools/driver/cc1_main.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TimeProfiler.h"
@@ -221,6 +222,10 @@
   if (Clang->getFrontendOpts().PrintSupportedCPUs)
 return PrintSupportedCPUs(Clang->getTargetOpts().Triple);
 
+  // --print-supported-extensions takes priority over the actual compilation.
+  if (Clang->getFrontendOpts().PrintSupportedExtensions)
+return llvm::riscvExtensionsHelp(), 0;
+
   // Infer the builtin include path if unspecified.
   if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
   Clang->getHeaderSearchOpts().ResourceDir.empty())
Index: clang/test/Driver/print-supported-extensions.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-extensions.c
@@ -0,0 +1,129 @@
+/// Test that --print-supported-extensions lists supported extensions.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang -Werror --target=riscv64 --print-supported-extensions 2>&1 | \
+// RUN:   FileCheck --strict-whitespace --match-full-lines %s
+
+//   CHECK:Target: riscv64
+//   CHECK:All available -march extensions for RISC-V
+//   CHECK:	NameVersion
+//  CHECK-NEXT:	i   2.1
+//  CHECK-NEXT:	e   2.0
+//  CHECK-NEXT:	m   2.0
+//  CHECK-NEXT:	a   2.1
+//  CHECK-NEXT:	f   2.2
+//  CHECK-NEXT:	d   2.2
+//  CHECK-NEXT:	c   2.0
+//  CHECK-NEXT:	v   1.0
+//  CHECK-NEXT:	h   1.0
+//  CHECK-NEXT:	zicbom  1.0
+//  CHECK-NEXT:	zicbop  1.0
+//  CHECK-NEXT:	zicboz  1.0
+//  CHECK-NEXT:	zicntr  1.0
+//  CHECK-NEXT:	zicsr   2.0
+//  CHECK-NEXT:	zifencei2.0
+//  CHECK-NEXT:	zihintpause 2.0
+//  CHECK-NEXT:	zihpm   1.0
+//  CHECK-NEXT:	zmmul   1.0
+//  CHECK-NEXT:	zawrs   1.0
+//  CHECK-NEXT:	zfh 1.0
+//  CHECK-NEXT:	zfhmin  1.0
+//  CHECK-NEXT:	zfinx   1.0
+//  CHECK-NEXT:	zdinx   1.0
+//  CHECK-NEXT:	zca 1.0
+//  CHECK-NEXT:	zcb 1.0
+//  CHECK-NEXT:	zcd 1.0
+//  CHECK-NEXT:	zce 1.0
+//  CHECK-NEXT:	zcf 1.0
+//  CHECK-NEXT:	zcmp1.0
+//  CHECK-NEXT:	zcmt

[PATCH] D158050: [RISCV] RISCV vector calling convention (2/2)

2023-08-15 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay.
Herald added a project: clang.

This patch handles vector type and tuple type arguments
calling convention. Vector type arguments can be passed
directly by register or by reference, however tuple type
arguments are split into multiple vector type arguments,
all of these arguments should be either passed by references
or passed by registers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158050

Files:
  clang/include/clang/AST/Type.h
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c

Index: clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
@@ -0,0 +1,26 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
+// RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
+
+#include 
+
+// CHECK-LLVM: void @call1( %v0,  %v1.coerce0,  %v1.coerce1,  %v2,  %v3)
+void call1(vint32m2_t v0, vint32m4x2_t v1, vint32m4_t v2, vint32m1_t v3) {}
+
+// CHECK-LLVM: void @call2( %v0.coerce0,  %v0.coerce1,  %v0.coerce2,  %v1.coerce0,  %v1.coerce1,  %v2, ptr noundef %0)
+void call2(vint32m1x3_t v0, vint32m4x2_t v1, vint32m4_t v2, vint32m2_t v3) {}
+
+// CHECK-LLVM: void @call3( %v0.coerce0,  %v0.coerce1, ptr noundef %0,  %v2.coerce0,  %v2.coerce1)
+void call3(vint32m4x2_t v0, vint32m1_t v1, vint32m4x2_t v2) {}
+
+// CHECK-LLVM: void @call4( %v0, ptr noundef %0,  %v2)
+void call4(vint32m8_t v0, vint32m1_t v1, vint32m8_t v2) {}
+
+// CHECK-LLVM: void @call5(ptr noundef %0,  %v1, ptr noundef %1,  %v3)
+void call5(vint32m1_t v0, vint32m8_t v1, vint32m1_t v2, vint32m8_t v3) {}
+
+// CHECK-LLVM: void @call6( %v0,  %v1,  %v2,  %v3)
+void call6(vint8mf8_t v0, vint8m8_t v1, vint32m1_t v2, vint8mf8_t v3) {}
+
+// CHECK-LLVM: void @call7(ptr noundef %0,  %v1,  %v2, ptr noundef %1)
+void call7(vint8mf8_t v0, vint8m8_t v1, vint32m8_t v2, vint8mf8_t v3) {}
Index: clang/lib/CodeGen/Targets/RISCV.cpp
===
--- clang/lib/CodeGen/Targets/RISCV.cpp
+++ clang/lib/CodeGen/Targets/RISCV.cpp
@@ -8,6 +8,7 @@
 
 #include "ABIInfoImpl.h"
 #include "TargetInfo.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
 
 using namespace clang;
 using namespace clang::CodeGen;
@@ -19,6 +20,9 @@
 namespace {
 class RISCVABIInfo : public DefaultABIInfo {
 private:
+  using ArgRegPair = std::pair;
+  using ArgRegPairs = llvm::SmallVector;
+
   // Size of the integer ('x') registers in bits.
   unsigned XLen;
   // Size of the floating point ('f') registers in bits. Note that the target
@@ -27,11 +31,15 @@
   unsigned FLen;
   static const int NumArgGPRs = 8;
   static const int NumArgFPRs = 8;
+  static const int NumArgVRs = 16;
   bool detectFPCCEligibleStructHelper(QualType Ty, CharUnits CurOff,
   llvm::Type *&Field1Ty,
   CharUnits &Field1Off,
   llvm::Type *&Field2Ty,
   CharUnits &Field2Off) const;
+  unsigned
+  computeMaxAssignedRegs(ArgRegPairs &RVVArgRegPairs,
+ std::vector> &MaxRegs) const;
 
 public:
   RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen)
@@ -41,6 +49,9 @@
   // non-virtual, but computeInfo is virtual, so we overload it.
   void computeInfo(CGFunctionInfo &FI) const override;
 
+  ArgRegPairs calculateRVVArgVRegs(CGFunctionInfo &FI) const;
+  void classifyRVVArgumentType(ArgRegPairs RVVArgRegPairs) const;
+
   ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed, int &ArgGPRsLeft,
   int &ArgFPRsLeft) const;
   ABIArgInfo classifyReturnType(QualType RetTy) const;
@@ -92,9 +103,98 @@
   int ArgNum = 0;
   for (auto &ArgInfo : FI.arguments()) {
 bool IsFixed = ArgNum < NumFixedArgs;
+ArgNum++;
+
+if (ArgInfo.type.getTypePtr()->isRVVType())
+  continue;
+
 ArgInfo.info =
 classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft, ArgFPRsLeft);
-ArgNum++;
+  }
+
+  classifyRVVArgumentType(calculateRVVArgVRegs(FI));
+}
+
+// Calculate total vregs each RVV argument needs.
+RISCVABIInfo::ArgRegPairs
+RISCVABIInfo::calculateRVVArgVRegs(CGFunctionInfo &FI) const {
+  RISCVABIInfo::ArgRegPairs RVVArgRegPairs;
+  for (auto &ArgInfo : FI.arguments()) {
+const QualType &Ty = ArgInfo.

[PATCH] D158067: [RISCV] Bump vector crypto to v1.0 RC2

2023-08-17 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 551364.
4vtomat added a comment.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Address Craig's comments.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
  llvm/docs/RISCVUsage.rst
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rvv/vandn.ll
  llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
  llvm/test/CodeGen/RISCV/rvv/vrev8.ll
  llvm/test/CodeGen/RISCV/rvv/vrol.ll
  llvm/test/CodeGen/RISCV/rvv/vror.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvbb.s
  llvm/test/MC/RISCV/rvv/zvkb.s

Index: llvm/test/MC/RISCV/rvv/zvkb.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkb.s
@@ -0,0 +1,63 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vandn.vv v10, v9, v8, v0.t
+# CHECK-INST: vandn.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 04   
+
+vandn.vx v10, v9, a0, v0.t
+# CHECK-INST: vandn.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 04   
+
+vbrev8.v v10, v9, v0.t
+# CHECK-INST: vbrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x25,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 25 94 48   
+
+vrev8.v v10, v9, v0.t
+# CHECK-INST: vrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0xa5,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 a5 94 48   
+
+vrol.vv v10, v9, v8, v0.t
+# CHECK-INST: vrol.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 54   
+
+vrol.vx v10, v9, a0, v0.t
+# CHECK-INST: vrol.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 5

[PATCH] D158067: [RISCV] Bump vector crypto to v1.0 RC2

2023-08-17 Thread Brandon Wu via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG29f11e4fb704: [RISCV] Bump vector crypto to v1.0 RC2 
(authored by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158067/new/

https://reviews.llvm.org/D158067

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vrol.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vror.c
  llvm/docs/RISCVUsage.rst
  llvm/include/llvm/IR/IntrinsicsRISCV.td
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/CodeGen/RISCV/rvv/vandn.ll
  llvm/test/CodeGen/RISCV/rvv/vbrev8.ll
  llvm/test/CodeGen/RISCV/rvv/vrev8.ll
  llvm/test/CodeGen/RISCV/rvv/vrol.ll
  llvm/test/CodeGen/RISCV/rvv/vror.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvbb.s
  llvm/test/MC/RISCV/rvv/zvkb.s

Index: llvm/test/MC/RISCV/rvv/zvkb.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvkb.s
@@ -0,0 +1,63 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vandn.vv v10, v9, v8, v0.t
+# CHECK-INST: vandn.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 04   
+
+vandn.vx v10, v9, a0, v0.t
+# CHECK-INST: vandn.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x04]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 45 95 04   
+
+vbrev8.v v10, v9, v0.t
+# CHECK-INST: vbrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0x25,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 25 94 48   
+
+vrev8.v v10, v9, v0.t
+# CHECK-INST: vrev8.v v10, v9, v0.t
+# CHECK-ENCODING: [0x57,0xa5,0x94,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 a5 94 48   
+
+vrol.vv v10, v9, v8, v0.t
+# CHECK-INST: vrol.vv v10, v9, v8, v0.t
+# CHECK-ENCODING: [0x57,0x05,0x94,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}}
+# CHECK-UNKNOWN: 57 05 94 54   
+
+vrol.vx v10, v9, a0, v0.t
+# CHECK-INST: vrol.vx v10, v9, a0, v0.t
+# CHECK-ENCODING: [0x57,0x45,0x95,0x54]
+# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation

[PATCH] D158257: [RISCV] Add feature checks for vector crypto C intrinsics

2023-08-18 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, sunshaoce, VincentWu, vkmr, 
frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158257

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c
  clang/test/Sema/zvk-invalid-features.c
  clang/test/Sema/zvk-invalid-vlen.c
  clang/test/Sema/zvk-invalid.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -656,6 +656,14 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
+  .Case("Zvbb", RVV_REQ_Zvbb)
+  .Case("Zvbc", RVV_REQ_Zvbc)
+  .Case("Zvkb", RVV_REQ_Zvkb)
+  .Case("Zvkg", RVV_REQ_Zvkg)
+  .Case("Zvkned", RVV_REQ_Zvkned)
+  .Case("Zvknha", RVV_REQ_Zvknha)
+  .Case("Zvksed", RVV_REQ_Zvksed)
+  .Case("Zvksh", RVV_REQ_Zvksh)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
   SR.RequiredExtensions |= RequireExt;
Index: clang/test/Sema/zvk-invalid-vlen.c
===
--- clang/test/Sema/zvk-invalid-vlen.c
+++ clang/test/Sema/zvk-invalid-vlen.c
@@ -1,5 +1,6 @@
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -fsyntax-only -verify
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvkned \
+// RUN:   %s -fsyntax-only -verify
 
 #include 
 
Index: clang/test/Sema/zvk-invalid-features.c
===
--- /dev/null
+++ clang/test/Sema/zvk-invalid-features.c
@@ -0,0 +1,48 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 %s -fsyntax-only -verify
+
+void test_zvk_features() {
+  // zvbb
+  __riscv_vbrev(); // expected-error {{call to undeclared function '__riscv_vbrev'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vclz(); // expected-error {{call to undeclared function '__riscv_vclz'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vctz(); // expected-error {{call to undeclared function '__riscv_vctz'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vcpopv(); // expected-error {{call to undeclared function '__riscv_vcpopv'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vwsll(); // expected-error {{call to undeclared function '__riscv_vwsll'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvbc
+  __riscv_vclmul(); // expected-error {{call to undeclared function '__riscv_vclmul'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vclmulh(); // expected-error {{call to undeclared function '__riscv_vclmulh'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkb
+  __riscv_vandn(); // expected-error {{call to undeclared function '__riscv_vandn'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vbrev8(); // expected-error {{call to undeclared function '__riscv_vbrev8'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vrev8(); // expected-error {{call to undeclared function '__riscv_vrev8'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vrol(); // expected-error {{call to undeclared function '__riscv_vrol'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vror(); // expected-error {{call to undeclared function '__riscv_vror'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkg
+  __riscv_vghsh(); // expected-error {{call to undeclared function '__riscv_vghsh'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vgmul(); // expected

[PATCH] D158257: [RISCV] Add feature checks for vector crypto C intrinsics

2023-08-18 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 551419.
4vtomat added a comment.

Update test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158257/new/

https://reviews.llvm.org/D158257

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c
  clang/test/Sema/zvk-invalid-features.c
  clang/test/Sema/zvk-invalid-vlen.c
  clang/test/Sema/zvk-invalid.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -656,6 +656,14 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
+  .Case("Zvbb", RVV_REQ_Zvbb)
+  .Case("Zvbc", RVV_REQ_Zvbc)
+  .Case("Zvkb", RVV_REQ_Zvkb)
+  .Case("Zvkg", RVV_REQ_Zvkg)
+  .Case("Zvkned", RVV_REQ_Zvkned)
+  .Case("Zvknha", RVV_REQ_Zvknha)
+  .Case("Zvksed", RVV_REQ_Zvksed)
+  .Case("Zvksh", RVV_REQ_Zvksh)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
   SR.RequiredExtensions |= RequireExt;
Index: clang/test/Sema/zvk-invalid-vlen.c
===
--- clang/test/Sema/zvk-invalid-vlen.c
+++ clang/test/Sema/zvk-invalid-vlen.c
@@ -1,5 +1,6 @@
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -fsyntax-only -verify
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvkned \
+// RUN:   -target-feature +experimental-zvksh %s -fsyntax-only -verify
 
 #include 
 
Index: clang/test/Sema/zvk-invalid-features.c
===
--- /dev/null
+++ clang/test/Sema/zvk-invalid-features.c
@@ -0,0 +1,48 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 %s -fsyntax-only -verify
+
+void test_zvk_features() {
+  // zvbb
+  __riscv_vbrev(); // expected-error {{call to undeclared function '__riscv_vbrev'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vclz(); // expected-error {{call to undeclared function '__riscv_vclz'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vctz(); // expected-error {{call to undeclared function '__riscv_vctz'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vcpopv(); // expected-error {{call to undeclared function '__riscv_vcpopv'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vwsll(); // expected-error {{call to undeclared function '__riscv_vwsll'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvbc
+  __riscv_vclmul(); // expected-error {{call to undeclared function '__riscv_vclmul'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vclmulh(); // expected-error {{call to undeclared function '__riscv_vclmulh'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkb
+  __riscv_vandn(); // expected-error {{call to undeclared function '__riscv_vandn'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vbrev8(); // expected-error {{call to undeclared function '__riscv_vbrev8'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vrev8(); // expected-error {{call to undeclared function '__riscv_vrev8'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vrol(); // expected-error {{call to undeclared function '__riscv_vrol'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vror(); // expected-error {{call to undeclared function '__riscv_vror'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkg
+  __riscv_vghsh(); // expected-error {{call to undeclared function '__riscv_vghsh'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vgmul(); // expected-error {{call to undeclared function '__riscv_vgmul'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkned
+  __riscv_vaesdf(); // expected-error {{call to u

[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

2023-07-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

In D154576#4483919 , @lhtin wrote:

> In D154576#4476300 , @4vtomat wrote:
>
>> In D154576#4476291 , @craig.topper 
>> wrote:
>>
>>> Does this only change the calling convention when 
>>> `__attribute__((riscv_vector_cc))` is used? The attribute should be 
>>> mentioned in the patch description.
>>
>> Yes it only changes when `__attribute__((riscv_vector_cc))` is used, thanks 
>> for reminding, I will mention in the description.
>
> In addition to using attributes, functions that use vector registers to pass 
> arguments or return values also need to comply with the new calling 
> convention.

Thanks for pointing this out! However, since it would make a tons of test cases 
change, I will make it in another patch!


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[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

2023-07-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat marked 2 inline comments as done.
4vtomat added inline comments.



Comment at: clang/lib/AST/ItaniumMangle.cpp:3267
   case CC_PreserveAll:
+  case CC_RISCVVectorCall:
 // FIXME: we should be mangling all of the above.

aaron.ballman wrote:
> Is it possible to use this calling convention on Windows where we'd hit the 
> Microsoft name mangler?
Thanks for reviewing. However since RISCV target currently only supports `elf`, 
so maybe we will do this in the future!



Comment at: clang/test/CodeGen/RISCV/riscv-vector-cc-attr.c:1
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// REQUIRES: riscv-registered-target

aaron.ballman wrote:
> You should also have Sema tests for various things (attribute accepts no 
> arguments, only applies to functions, does/doesn't silently convert to cdecl, 
> etc). You should also have some tests using the attribute as a type attribute 
> instead of a declaration attribute.
> 
> You should also have C++ tests for Sema and codegen for things like putting 
> the calling convention on a member function or a lambda to ensure those do 
> reasonable things with the convention.
Good idea, thanks for your review, I will add some tests for Sema!


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[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-07-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 545411.
4vtomat marked 6 inline comments as done.
4vtomat added a comment.

Resolved MaskRay's comments, thanks for reviewing!!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146054/new/

https://reviews.llvm.org/D146054

Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-extensions.c
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -198,6 +198,29 @@
 #endif
 }
 
+void llvm::riscvExtensionsHelp() {
+  outs() << "All available -march extensions for RISC-V\n\n";
+  outs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nUse -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -22,6 +22,8 @@
   unsigned MinorVersion;
 };
 
+void riscvExtensionsHelp();
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
Index: clang/tools/driver/cc1_main.cpp
===
--- clang/tools/driver/cc1_main.cpp
+++ clang/tools/driver/cc1_main.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TimeProfiler.h"
@@ -182,6 +183,12 @@
   return 0;
 }
 
+/// Print supported extensions of the RISCV target.
+static void printSupportedExtensions() {
+  llvm::riscvExtensionsHelp();
+}
+
+
 int cc1_main(ArrayRef Argv, const char *Argv0, void *MainAddr) {
   ensureSufficientStack();
 
@@ -221,6 +228,10 @@
   if (Clang->getFrontendOpts().PrintSupportedCPUs)
 return PrintSupportedCPUs(Clang->getTargetOpts().Triple);
 
+  // --print-supported-extensions takes priority over the actual compilation.
+  if (Clang->getFrontendOpts().PrintSupportedExtensions)
+return printSupportedExtensions(), 0;
+
   // Infer the builtin include path if unspecified.
   if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
   Clang->getHeaderSearchOpts().ResourceDir.empty())
Index: clang/test/Driver/print-supported-extensions.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-extensions.c
@@ -0,0 +1,122 @@
+/// Test that --print-supported-extensions lists supported extensions.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang --target=riscv64 --print-supported-extensions 2>&1 | \
+// RUN:   FileCheck --implicit-check-not=warning: --strict-whitespace --match-full-lines %s
+
+//  CHECK:Target: riscv64
+//  CHECK:All available -march extensions for RISC-V
+//  CHECK:	NameVersion
+// CHECK-NEXT:	i   2.1
+// CHECK-NEXT:	e   2.0
+// CHECK-NEXT:	m   2.0
+// CHECK-NEXT:	a   2.1
+// CHECK-NEXT:	f   2.2
+// CHECK-NEXT:	d   2.2
+// CHECK-NEXT:	c   2.0
+// CHECK-NEXT:	v   1.0
+// CHECK-NEXT:	h   1.0
+// CHECK-NEXT:	zicbom  1.0
+// CHECK-NEXT:	zicbop  1.0
+// CHECK-NEXT:	zicboz  1.0
+// CHECK-NEXT:	zicntr  1.0
+// CHECK-NEXT:	zicsr   2.0
+// CHECK-NEXT:	zifencei2.0
+// CHECK-NEXT:	zihintpause 2.0
+// CHECK-NEXT:	zihpm   1.0
+// CHECK-NEXT:	zmmul   1.0
+// CHECK-NEXT:	zawrs   1.0
+// CHECK-NEXT:	zfh 1.0
+// CHECK-NEXT:	zfhmin  1.0
+// CHECK-NEXT:	zfinx   1.0
+// CHECK-NEXT:	zdinx   1.0
+// CHECK-NEXT:	zca

[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-07-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 545412.
4vtomat added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146054/new/

https://reviews.llvm.org/D146054

Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-extensions.c
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -208,6 +208,29 @@
 #endif
 }
 
+void llvm::riscvExtensionsHelp() {
+  outs() << "All available -march extensions for RISC-V\n\n";
+  outs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nUse -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -22,6 +22,8 @@
   unsigned MinorVersion;
 };
 
+void riscvExtensionsHelp();
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
Index: clang/tools/driver/cc1_main.cpp
===
--- clang/tools/driver/cc1_main.cpp
+++ clang/tools/driver/cc1_main.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TimeProfiler.h"
@@ -182,6 +183,12 @@
   return 0;
 }
 
+/// Print supported extensions of the RISCV target.
+static void printSupportedExtensions() {
+  llvm::riscvExtensionsHelp();
+}
+
+
 int cc1_main(ArrayRef Argv, const char *Argv0, void *MainAddr) {
   ensureSufficientStack();
 
@@ -221,6 +228,10 @@
   if (Clang->getFrontendOpts().PrintSupportedCPUs)
 return PrintSupportedCPUs(Clang->getTargetOpts().Triple);
 
+  // --print-supported-extensions takes priority over the actual compilation.
+  if (Clang->getFrontendOpts().PrintSupportedExtensions)
+return printSupportedExtensions(), 0;
+
   // Infer the builtin include path if unspecified.
   if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
   Clang->getHeaderSearchOpts().ResourceDir.empty())
Index: clang/test/Driver/print-supported-extensions.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-extensions.c
@@ -0,0 +1,122 @@
+/// Test that --print-supported-extensions lists supported extensions.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang --target=riscv64 --print-supported-extensions 2>&1 | \
+// RUN:   FileCheck --implicit-check-not=warning: --strict-whitespace --match-full-lines %s
+
+//  CHECK:Target: riscv64
+//  CHECK:All available -march extensions for RISC-V
+//  CHECK:	NameVersion
+// CHECK-NEXT:	i   2.1
+// CHECK-NEXT:	e   2.0
+// CHECK-NEXT:	m   2.0
+// CHECK-NEXT:	a   2.1
+// CHECK-NEXT:	f   2.2
+// CHECK-NEXT:	d   2.2
+// CHECK-NEXT:	c   2.0
+// CHECK-NEXT:	v   1.0
+// CHECK-NEXT:	h   1.0
+// CHECK-NEXT:	zicbom  1.0
+// CHECK-NEXT:	zicbop  1.0
+// CHECK-NEXT:	zicboz  1.0
+// CHECK-NEXT:	zicntr  1.0
+// CHECK-NEXT:	zicsr   2.0
+// CHECK-NEXT:	zifencei2.0
+// CHECK-NEXT:	zihintpause 2.0
+// CHECK-NEXT:	zihpm   1.0
+// CHECK-NEXT:	zmmul   1.0
+// CHECK-NEXT:	zawrs   1.0
+// CHECK-NEXT:	zfh 1.0
+// CHECK-NEXT:	zfhmin  1.0
+// CHECK-NEXT:	zfinx   1.0
+// CHECK-NEXT:	zdinx   1.0
+// CHECK-NEXT:	zca 1.0
+// CHECK-NEXT:	zcb 1.0
+// CHECK-NEXT:	zcd

[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

2023-07-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 545413.
4vtomat marked 2 inline comments as done.
4vtomat added a comment.

Resolved Aaron's comments.
Also group some code and refactoring some code to make it much clear.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154576/new/

https://reviews.llvm.org/D154576

Files:
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/Specifiers.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
  clang/test/CodeGen/RISCV/riscv-vector-callingconv.cpp
  llvm/include/llvm/AsmParser/LLToken.h
  llvm/include/llvm/IR/CallingConv.h
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/Target/RISCV/RISCVCallingConv.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll

Index: llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
@@ -0,0 +1,221 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+m -mattr=+v -O2 < %s \
+; RUN:| FileCheck --check-prefix=SPILL-O2 %s
+
+define  @test_vector_std( %va) nounwind {
+; SPILL-O2-LABEL: test_vector_std:
+; SPILL-O2:   # %bb.0: # %entry
+; SPILL-O2-NEXT:addi sp, sp, -16
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 1
+; SPILL-O2-NEXT:sub sp, sp, a0
+; SPILL-O2-NEXT:addi a0, sp, 16
+; SPILL-O2-NEXT:vs1r.v v8, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:#APP
+; SPILL-O2-NEXT:#NO_APP
+; SPILL-O2-NEXT:vl1r.v v8, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 1
+; SPILL-O2-NEXT:add sp, sp, a0
+; SPILL-O2-NEXT:addi sp, sp, 16
+; SPILL-O2-NEXT:ret
+entry:
+  call void asm sideeffect "",
+  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
+
+  ret  %va
+}
+
+define riscv_vector_cc  @test_vector_callee( %va) nounwind {
+; SPILL-O2-LABEL: test_vector_callee:
+; SPILL-O2:   # %bb.0: # %entry
+; SPILL-O2-NEXT:addi sp, sp, -16
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 4
+; SPILL-O2-NEXT:sub sp, sp, a0
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a1, a0, 4
+; SPILL-O2-NEXT:sub a0, a1, a0
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v1, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 14
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v2, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 13
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v3, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 12
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v4, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 11
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v5, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 10
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v6, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a1, a0, 3
+; SPILL-O2-NEXT:add a0, a1, a0
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v7, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 3
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v24, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a1, a0, 3
+; SPILL-O2-NEXT:sub a0, a1, a0
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v25,

[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-07-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 545499.
4vtomat marked 6 inline comments as done.
4vtomat added a comment.

Resolved MaskRay's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146054/new/

https://reviews.llvm.org/D146054

Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-extensions.c
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -208,6 +208,29 @@
 #endif
 }
 
+void llvm::riscvExtensionsHelp() {
+  outs() << "All available -march extensions for RISC-V\n\n";
+  outs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nUse -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -22,6 +22,8 @@
   unsigned MinorVersion;
 };
 
+void riscvExtensionsHelp();
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
Index: clang/tools/driver/cc1_main.cpp
===
--- clang/tools/driver/cc1_main.cpp
+++ clang/tools/driver/cc1_main.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TimeProfiler.h"
@@ -221,6 +222,10 @@
   if (Clang->getFrontendOpts().PrintSupportedCPUs)
 return PrintSupportedCPUs(Clang->getTargetOpts().Triple);
 
+  // --print-supported-extensions takes priority over the actual compilation.
+  if (Clang->getFrontendOpts().PrintSupportedExtensions)
+return llvm::riscvExtensionsHelp(), 0;
+
   // Infer the builtin include path if unspecified.
   if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
   Clang->getHeaderSearchOpts().ResourceDir.empty())
Index: clang/test/Driver/print-supported-extensions.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-extensions.c
@@ -0,0 +1,122 @@
+/// Test that --print-supported-extensions lists supported extensions.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang --target=riscv64 --print-supported-extensions 2>&1 | \
+// RUN:   FileCheck --implicit-check-not=warning: --strict-whitespace --match-full-lines %s
+
+//  CHECK:Target: riscv64
+//  CHECK:All available -march extensions for RISC-V
+//  CHECK:	NameVersion
+// CHECK-NEXT:	i   2.1
+// CHECK-NEXT:	e   2.0
+// CHECK-NEXT:	m   2.0
+// CHECK-NEXT:	a   2.1
+// CHECK-NEXT:	f   2.2
+// CHECK-NEXT:	d   2.2
+// CHECK-NEXT:	c   2.0
+// CHECK-NEXT:	v   1.0
+// CHECK-NEXT:	h   1.0
+// CHECK-NEXT:	zicbom  1.0
+// CHECK-NEXT:	zicbop  1.0
+// CHECK-NEXT:	zicboz  1.0
+// CHECK-NEXT:	zicntr  1.0
+// CHECK-NEXT:	zicsr   2.0
+// CHECK-NEXT:	zifencei2.0
+// CHECK-NEXT:	zihintpause 2.0
+// CHECK-NEXT:	zihpm   1.0
+// CHECK-NEXT:	zmmul   1.0
+// CHECK-NEXT:	zawrs   1.0
+// CHECK-NEXT:	zfh 1.0
+// CHECK-NEXT:	zfhmin  1.0
+// CHECK-NEXT:	zfinx   1.0
+// CHECK-NEXT:	zdinx   1.0
+// CHECK-NEXT:	zca 1.0
+// CHECK-NEXT:	zcb 1.0
+// CHECK-NEXT:	zcd 1.0
+// CHECK-NEXT:	zcf 1.0
+// CHECK-NEXT:	zcmp1.0
+// CHECK-NEXT:	zcmt1.0
+// CHECK-NEXT:	zba 1.0
+// CHECK-NEXT:	zbb

[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-07-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added inline comments.



Comment at: clang/include/clang/Frontend/FrontendOptions.h:290
+  /// Output time trace profile.
+  unsigned TimeTrace : 1;
+

MaskRay wrote:
> stray change?
Oh, maybe it was added accidentally during rebase lol~



Comment at: clang/test/Driver/print-supported-extensions.c:10
+// CHECK:All available -march extensions for RISC-V
+// CHECK:  NameVersion
+// CHECK-NEXT: i   2.1

MaskRay wrote:
> For `--strict-whitespace --match-full-lines` testing, we usually right align 
> `CHECK` and `CHECK-NEXT`.
Oh, I got it, thanks!



Comment at: clang/tools/driver/cc1_main.cpp:187
+/// Print supported extensions of the RISCV target.
+static void printSupportedExtensions() {
+  llvm::riscvExtensionsHelp();

MaskRay wrote:
> The call site should just call riscvExtensionsHelp so that this internal 
> linkage function can be avoided.
Yeah, good idea!



Comment at: clang/tools/driver/cc1_main.cpp:187
+/// Print supported extensions of the RISCV target.
+static int print_supported_extensions() {
+  llvm::riscvExtensionsHelp();

MaskRay wrote:
> `printSupportedExtensions`. Why does this function return a dummy return 
> value?
> 
> You can do `return printSupportedExtensions(), 0` below to save some lines.
This is a good idea, return in its caller is much clear for it's intension!



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:202
+void llvm::riscvExtensionsHelp() {
+  errs() << "All available -march extensions for RISC-V\n\n";
+  errs() << '\t' << left_justify("Name", 20) << "Version\n";

MaskRay wrote:
> I think `outs()` is more conventional. Most `gcc --print-*` options go to 
> stdout. `clang --print-supported-cpus` deviates and we should not copy its 
> issue.
Sure, I agree to keep it conventional, since I was following 
`--print-supported-cpus` so I made it this way, thank you for pointing out this!


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[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-07-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 545500.
4vtomat added a comment.

Updated test case.


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Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-extensions.c
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -208,6 +208,29 @@
 #endif
 }
 
+void llvm::riscvExtensionsHelp() {
+  outs() << "All available -march extensions for RISC-V\n\n";
+  outs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+outs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  outs() << "\nUse -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -22,6 +22,8 @@
   unsigned MinorVersion;
 };
 
+void riscvExtensionsHelp();
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
Index: clang/tools/driver/cc1_main.cpp
===
--- clang/tools/driver/cc1_main.cpp
+++ clang/tools/driver/cc1_main.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TimeProfiler.h"
@@ -221,6 +222,10 @@
   if (Clang->getFrontendOpts().PrintSupportedCPUs)
 return PrintSupportedCPUs(Clang->getTargetOpts().Triple);
 
+  // --print-supported-extensions takes priority over the actual compilation.
+  if (Clang->getFrontendOpts().PrintSupportedExtensions)
+return llvm::riscvExtensionsHelp(), 0;
+
   // Infer the builtin include path if unspecified.
   if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
   Clang->getHeaderSearchOpts().ResourceDir.empty())
Index: clang/test/Driver/print-supported-extensions.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-extensions.c
@@ -0,0 +1,129 @@
+/// Test that --print-supported-extensions lists supported extensions.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang --target=riscv64 --print-supported-extensions 2>&1 | \
+// RUN:   FileCheck --implicit-check-not=warning: --strict-whitespace --match-full-lines %s
+
+//   CHECK:Target: riscv64
+//   CHECK:All available -march extensions for RISC-V
+//   CHECK:	NameVersion
+//  CHECK-NEXT:	i   2.1
+//  CHECK-NEXT:	e   2.0
+//  CHECK-NEXT:	m   2.0
+//  CHECK-NEXT:	a   2.1
+//  CHECK-NEXT:	f   2.2
+//  CHECK-NEXT:	d   2.2
+//  CHECK-NEXT:	c   2.0
+//  CHECK-NEXT:	v   1.0
+//  CHECK-NEXT:	h   1.0
+//  CHECK-NEXT:	zicbom  1.0
+//  CHECK-NEXT:	zicbop  1.0
+//  CHECK-NEXT:	zicboz  1.0
+//  CHECK-NEXT:	zicntr  1.0
+//  CHECK-NEXT:	zicsr   2.0
+//  CHECK-NEXT:	zifencei2.0
+//  CHECK-NEXT:	zihintpause 2.0
+//  CHECK-NEXT:	zihpm   1.0
+//  CHECK-NEXT:	zmmul   1.0
+//  CHECK-NEXT:	zawrs   1.0
+//  CHECK-NEXT:	zfh 1.0
+//  CHECK-NEXT:	zfhmin  1.0
+//  CHECK-NEXT:	zfinx   1.0
+//  CHECK-NEXT:	zdinx   1.0
+//  CHECK-NEXT:	zca 1.0
+//  CHECK-NEXT:	zcb 1.0
+//  CHECK-NEXT:	zcd 1.0
+//  CHECK-NEXT:	zce 1.0
+//  CHECK-NEXT:	zcf 1.0
+//  CHECK-NEXT:	zcmp1.0
+//  CHECK-NEXT:	zcmt1.0
+//  CHECK-NEXT:	zba 1.0
+//  CHEC

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-08-02 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 546671.
4vtomat marked 3 inline comments as done.
4vtomat added a comment.

This update does a few things:

1. Update Craig's comments.
2. Make `LMUL=8` 
valid(https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234#discussion_r1282568330).
3. Rebase.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Basic/riscv_vector_common.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
  
clang/test/Co

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-08-02 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:2405
+  defvar suffix = !if(IsVV, "vv", "vi");
+  defvar prototype = !if(IsVV, "UvUvUvUv", "UvUvUvKz");
+  defm "" : RVVBuiltinSet;

craig.topper wrote:
> Can we split this into two classes and get rid of IsVV?
Sure, good idea~



Comment at: clang/lib/Sema/SemaChecking.cpp:4693
+  }
+  case RISCVVector::BI__builtin_rvv_vaesdf_vv:
+  case RISCVVector::BI__builtin_rvv_vaesdf_vs:

craig.topper wrote:
> Are there `tu` versions of these builtins?
Yes, there are, thanks for reminding!



Comment at: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c:12
+//
+vint16mf4_t test_vwsll_vv_i16mf4(vint8mf8_t op1, vint8mf8_t op2, size_t vl) {
+  return __riscv_vwsll_vv_i16mf4(op1, op2, vl);

craig.topper wrote:
> craig.topper wrote:
> > It doesn't make sense for op2 to be signed. It's a shift amount, its always 
> > a positive number
> The spec doesn't define signed versions of these instrinsics from what I can 
> see.
You are right, maybe it should only be signed version!



Comment at: clang/test/Sema/zvk-invalid.c:19
+  __riscv_vaesdf_vv_u32mf2(vd, vs2, vl); // expected-error {{RISC-V type 
'vuint32mf2_t' (aka '__rvv_uint32mf2_t') requires the 'zvl256b' extension}}
+}

craig.topper wrote:
> Test a _vs intrinsic since the vs operand has a different type than the 
> result?
Sure~


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-08-02 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 546677.
4vtomat added a comment.

Update missing comment.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Basic/riscv_vector_common.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intr

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-08-03 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 546746.
4vtomat added a comment.

This update does a few things:

1. Update test cases based on rvv-intrinsic-doc.
2. Add checks for "zvknh[a|b]" instructions.
3. Rename and restructure the function from CheckInvalidEGW to 
CheckInvalidVLENandLMUL.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Basic/riscv_vector_common.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
  
clang/test/CodeGen/R

[PATCH] D156223: [RISCV] Resolve a few bugs in RISCVVIntrinsicUtils.cpp

2023-08-03 Thread Brandon Wu via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf3ce925083d2: [RISCV] Resolve a few bugs in 
RISCVVIntrinsicUtils.cpp (authored by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156223/new/

https://reviews.llvm.org/D156223

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v_invalid.c


Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v_invalid.c
===
--- /dev/null
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vlmul_trunc_v_invalid.c
@@ -0,0 +1,21 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
+// RUN:   -target-feature +zvfh -disable-O0-optnone %s -fsyntax-only -verify
+
+#include 
+
+vuint64m2_t test_vlmul_trunc_v_u64m2_u64m2(vuint64m2_t op1) { // expected-note 
{{'test_vlmul_trunc_v_u64m2_u64m2' declared here}}
+  return __riscv_vlmul_trunc_v_u64m2_u64m2(op1); // expected-error {{call to 
undeclared function '__riscv_vlmul_trunc_v_u64m2_u64m2'; ISO C99 and later do 
not support implicit function declarations}} expected-error {{returning 'int' 
from a function with incompatible result type 'vuint64m2_t' (aka 
'__rvv_uint64m2_t')}} expected-note {{did you mean 
'test_vlmul_trunc_v_u64m2_u64m2'?}}
+}
+
+vuint64m4_t test_vlmul_trunc_v_u64m4_u64m4(vuint64m4_t op1) { // expected-note 
{{'test_vlmul_trunc_v_u64m4_u64m4' declared here}}
+  return __riscv_vlmul_trunc_v_u64m4_u64m4(op1); // expected-error {{call to 
undeclared function '__riscv_vlmul_trunc_v_u64m4_u64m4'; ISO C99 and later do 
not support implicit function declarations}} expected-error {{returning 'int' 
from a function with incompatible result type 'vuint64m4_t' (aka 
'__rvv_uint64m4_t')}} expected-note {{did you mean 
'test_vlmul_trunc_v_u64m4_u64m4'?}}
+}
+
+vuint64m1_t test_vlmul_trunc_v_u64m1_u64m1(vuint64m1_t op1) { // expected-note 
{{'test_vlmul_trunc_v_u64m1_u64m1' declared here}}
+  return __riscv_vlmul_trunc_v_u64m1_u64m1(op1); // expected-error {{call to 
undeclared function '__riscv_vlmul_trunc_v_u64m1_u64m1'; ISO C99 and later do 
not support implicit function declarations}} expected-error {{returning 'int' 
from a function with incompatible result type 'vuint64m1_t' (aka 
'__rvv_uint64m1_t')}} expected-note {{did you mean 
'test_vlmul_trunc_v_u64m1_u64m1'?}}
+}
+
+vuint64m8_t test_vlmul_trunc_v_u64m8_u64m8(vuint64m8_t op1) { // expected-note 
{{'test_vlmul_trunc_v_u64m8_u64m8' declared here}}
+  return __riscv_vlmul_trunc_v_u64m8_u64m8(op1); // expected-error {{call to 
undeclared function '__riscv_vlmul_trunc_v_u64m8_u64m8'; ISO C99 and later do 
not support implicit function declarations}} expected-error {{returning 'int' 
from a function with incompatible result type 'vuint64m8_t' (aka 
'__rvv_uint64m8_t')}} expected-note {{did you mean 
'test_vlmul_trunc_v_u64m8_u64m8'?}}
+}
Index: clang/lib/Support/RISCVVIntrinsicUtils.cpp
===
--- clang/lib/Support/RISCVVIntrinsicUtils.cpp
+++ clang/lib/Support/RISCVVIntrinsicUtils.cpp
@@ -742,6 +742,10 @@
 break;
   }
 
+  // Early return if the current type modifier is already invalid.
+  if (ScalarType == Invalid)
+return;
+
   for (unsigned TypeModifierMaskShift = 0;
TypeModifierMaskShift <= static_cast(TypeModifier::MaxOffset);
++TypeModifierMaskShift) {
@@ -803,13 +807,13 @@
 void RVVType::applyFixedLog2LMUL(int Log2LMUL, enum FixedLMULType Type) {
   switch (Type) {
   case FixedLMULType::LargerThan:
-if (Log2LMUL < LMUL.Log2LMUL) {
+if (Log2LMUL <= LMUL.Log2LMUL) {
   ScalarType = ScalarTypeKind::Invalid;
   return;
 }
 break;
   case FixedLMULType::SmallerThan:
-if (Log2LMUL > LMUL.Log2LMUL) {
+if (Log2LMUL >= LMUL.Log2LMUL) {
   ScalarType = ScalarTypeKind::Invalid;
   return;
 }
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -133,6 +133,7 @@
 }
 break;
   case Invalid:
+  case Undefined:
 llvm_unreachable("Unhandled type.");
   }
   if (Type->isVector()) {
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -218,6 +218,7 @@
   UnsignedInteger,
   Float,
   Invalid,
+  Undefined,
 };
 
 // Exponential LMUL
@@ -240,7 +241,7 @@
   frien

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-08-08 Thread Brandon Wu via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2a05a5215f69: [RISCV] Support vector crypto extension C 
intrinsics (authored by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138810/new/

https://reviews.llvm.org/D138810

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Basic/riscv_vector_common.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaChecking.cpp
  clang/lib/Support/RISCVVIntrinsicUtils.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/ove

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-08-08 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

In D138810#4571579 , @dyung wrote:

> The test you added clang/test/Sema/zvk-invalid.c is failing on bots, for 
> example https://lab.llvm.org/buildbot/#/builders/139/builds/47055.
>
> Is the test missing a `REQUIRES: riscv-registered-target` line by any chance?

Yeah, you are right, I will have a patch to fix it, thanks!


Repository:
  rG LLVM Github Monorepo

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[PATCH] D157467: [RISCV] Add missing REQUIRES for zvk-invalid.c test

2023-08-08 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, VincentWu, vkmr, luismarques, 
sameer.abuasal, s.egerton, Jim, benna, psnobl, rogfer01, shiva0217, kito-cheng, 
simoncook, asb, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157467

Files:
  clang/test/Sema/zvk-invalid.c


Index: clang/test/Sema/zvk-invalid.c
===
--- clang/test/Sema/zvk-invalid.c
+++ clang/test/Sema/zvk-invalid.c
@@ -1,3 +1,4 @@
+// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -fsyntax-only -verify
 
 #include 


Index: clang/test/Sema/zvk-invalid.c
===
--- clang/test/Sema/zvk-invalid.c
+++ clang/test/Sema/zvk-invalid.c
@@ -1,3 +1,4 @@
+// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -fsyntax-only -verify
 
 #include 
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[PATCH] D157467: [RISCV] Add missing REQUIRES for zvk-invalid.c test

2023-08-08 Thread Brandon Wu via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGadb76c31ec42: [RISCV] Add missing REQUIRES for zvk-invalid.c 
test (authored by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D157467/new/

https://reviews.llvm.org/D157467

Files:
  clang/test/Sema/zvk-invalid.c


Index: clang/test/Sema/zvk-invalid.c
===
--- clang/test/Sema/zvk-invalid.c
+++ clang/test/Sema/zvk-invalid.c
@@ -1,3 +1,4 @@
+// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -fsyntax-only -verify
 
 #include 


Index: clang/test/Sema/zvk-invalid.c
===
--- clang/test/Sema/zvk-invalid.c
+++ clang/test/Sema/zvk-invalid.c
@@ -1,3 +1,4 @@
+// REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -fsyntax-only -verify
 
 #include 
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[PATCH] D157474: [RISCV] Add missing Xsfvcp extension check in clang sema

2023-08-08 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, wangpc, eopXD, MaskRay.
Herald added a project: clang.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D157474

Files:
  clang/lib/Sema/SemaRISCVVectorLookup.cpp


Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -202,10 +202,20 @@
 void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
 ArrayRef Recs, IntrinsicKind K) {
   const TargetInfo &TI = Context.getTargetInfo();
-  bool HasRV64 = TI.hasFeature("64bit");
+  static const std::pair FeatureCheckList[] = {
+  {"64bit", RVV_REQ_RV64},
+  {"xsfvcp", RVV_REQ_Xsfvcp}};
+
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : Recs) {
+// Check requirements.
+if (llvm::any_of(FeatureCheckList, [&](const auto &Item) {
+  return (Record.RequiredExtensions & Item.second) == Item.second &&
+ !TI.hasFeature(Item.first);
+}))
+  continue;
+
 // Create Intrinsics for each type and LMUL.
 BasicType BaseType = BasicType::Unknown;
 ArrayRef BasicProtoSeq =
@@ -251,11 +261,6 @@
   if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
 continue;
 
-  // Check requirement.
-  if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) &&
-  !HasRV64)
-continue;
-
   // Expanded with different LMUL.
   for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
 if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3


Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -202,10 +202,20 @@
 void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
 ArrayRef Recs, IntrinsicKind K) {
   const TargetInfo &TI = Context.getTargetInfo();
-  bool HasRV64 = TI.hasFeature("64bit");
+  static const std::pair FeatureCheckList[] = {
+  {"64bit", RVV_REQ_RV64},
+  {"xsfvcp", RVV_REQ_Xsfvcp}};
+
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : Recs) {
+// Check requirements.
+if (llvm::any_of(FeatureCheckList, [&](const auto &Item) {
+  return (Record.RequiredExtensions & Item.second) == Item.second &&
+ !TI.hasFeature(Item.first);
+}))
+  continue;
+
 // Create Intrinsics for each type and LMUL.
 BasicType BaseType = BasicType::Unknown;
 ArrayRef BasicProtoSeq =
@@ -251,11 +261,6 @@
   if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
 continue;
 
-  // Check requirement.
-  if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) &&
-  !HasRV64)
-continue;
-
   // Expanded with different LMUL.
   for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
 if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3
___
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[PATCH] D157474: [RISCV] Add missing Xsfvcp extension check in clang sema

2023-08-09 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 548509.
4vtomat added a comment.

Add test cases.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/rvv-required-features-invalid.c
  clang/test/Sema/rvv-required-features.c


Index: clang/test/Sema/rvv-required-features.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp 
%s -fsyntax-only -verify
+
+// expected-no-diagnostics
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t 
vl) {
+  return __riscv_vloxei64(base, bindex, vl);
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, 
size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl);
+}
+
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl);
+}
Index: clang/test/Sema/rvv-required-features-invalid.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features-invalid.c
@@ -0,0 +1,17 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v %s -fsyntax-only -verify
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t 
vl) {
+  return __riscv_vloxei64(base, bindex, vl); // expected-error {{call to 
undeclared function '__riscv_vloxei64'}} expected-error {{returning 'int' from 
a function with incompatible result type 'vint8m1_t'}}
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, 
size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl); // expected-error {{call to 
undeclared function '__riscv_vsoxei64'}}
+}
+
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { // expected-note 
{{'test_sf_vc_x_se_u64m1' declared here}}
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); // expected-error {{call to 
undeclared function '__riscv_sf_vc_x_se_u64m1'}} expected-note {{did you mean 
'test_sf_vc_x_se_u64m1'?}}
+}
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -202,10 +202,20 @@
 void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
 ArrayRef Recs, IntrinsicKind K) {
   const TargetInfo &TI = Context.getTargetInfo();
-  bool HasRV64 = TI.hasFeature("64bit");
+  static const std::pair FeatureCheckList[] = {
+  {"64bit", RVV_REQ_RV64},
+  {"xsfvcp", RVV_REQ_Xsfvcp}};
+
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : Recs) {
+// Check requirements.
+if (llvm::any_of(FeatureCheckList, [&](const auto &Item) {
+  return (Record.RequiredExtensions & Item.second) == Item.second &&
+ !TI.hasFeature(Item.first);
+}))
+  continue;
+
 // Create Intrinsics for each type and LMUL.
 BasicType BaseType = BasicType::Unknown;
 ArrayRef BasicProtoSeq =
@@ -251,11 +261,6 @@
   if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
 continue;
 
-  // Check requirement.
-  if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) &&
-  !HasRV64)
-continue;
-
   // Expanded with different LMUL.
   for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
 if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3


Index: clang/test/Sema/rvv-required-features.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp %s -fsyntax-only -verify
+
+// expected-no-diagnostics
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
+  return __riscv_vloxei64(base, bindex, vl);
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl);
+}
+
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl);
+}
Index: clang/test/Sema/rvv-required-features-invalid.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features-invalid.c
@@ -0,0 +1,17 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v %s -fsyntax-only -verify
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
+  return __riscv_vlo

[PATCH] D157474: [RISCV] Add missing Xsfvcp extension check in clang sema

2023-08-09 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 548843.
4vtomat added a comment.

Rename the function in the test case.


Repository:
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Files:
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/Sema/rvv-required-features-invalid.c
  clang/test/Sema/rvv-required-features.c


Index: clang/test/Sema/rvv-required-features.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp 
%s -fsyntax-only -verify
+
+// expected-no-diagnostics
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t 
vl) {
+  return __riscv_vloxei64(base, bindex, vl);
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, 
size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl);
+}
+
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl);
+}
Index: clang/test/Sema/rvv-required-features-invalid.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features-invalid.c
@@ -0,0 +1,17 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v %s -fsyntax-only -verify
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t 
vl) {
+  return __riscv_vloxei64(base, bindex, vl); // expected-error {{call to 
undeclared function '__riscv_vloxei64'}} expected-error {{returning 'int' from 
a function with incompatible result type 'vint8m1_t'}}
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, 
size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl); // expected-error {{call to 
undeclared function '__riscv_vsoxei64'}}
+}
+
+void test_xsfvcp_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); // expected-error {{call to 
undeclared function '__riscv_sf_vc_x_se_u64m1'}}
+}
Index: clang/lib/Sema/SemaRISCVVectorLookup.cpp
===
--- clang/lib/Sema/SemaRISCVVectorLookup.cpp
+++ clang/lib/Sema/SemaRISCVVectorLookup.cpp
@@ -202,10 +202,20 @@
 void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
 ArrayRef Recs, IntrinsicKind K) {
   const TargetInfo &TI = Context.getTargetInfo();
-  bool HasRV64 = TI.hasFeature("64bit");
+  static const std::pair FeatureCheckList[] = {
+  {"64bit", RVV_REQ_RV64},
+  {"xsfvcp", RVV_REQ_Xsfvcp}};
+
   // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
   // in RISCVVEmitter.cpp.
   for (auto &Record : Recs) {
+// Check requirements.
+if (llvm::any_of(FeatureCheckList, [&](const auto &Item) {
+  return (Record.RequiredExtensions & Item.second) == Item.second &&
+ !TI.hasFeature(Item.first);
+}))
+  continue;
+
 // Create Intrinsics for each type and LMUL.
 BasicType BaseType = BasicType::Unknown;
 ArrayRef BasicProtoSeq =
@@ -251,11 +261,6 @@
   if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
 continue;
 
-  // Check requirement.
-  if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) &&
-  !HasRV64)
-continue;
-
   // Expanded with different LMUL.
   for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
 if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3


Index: clang/test/Sema/rvv-required-features.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features.c
@@ -0,0 +1,19 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp %s -fsyntax-only -verify
+
+// expected-no-diagnostics
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
+  return __riscv_vloxei64(base, bindex, vl);
+}
+
+void test_vsoxei64_v_i8m1(int8_t *base, vuint64m8_t bindex, vint8m1_t value, size_t vl) {
+  __riscv_vsoxei64(base, bindex, value, vl);
+}
+
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) {
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl);
+}
Index: clang/test/Sema/rvv-required-features-invalid.c
===
--- /dev/null
+++ clang/test/Sema/rvv-required-features-invalid.c
@@ -0,0 +1,17 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv32 -target-feature +v %s -fsyntax-only -verify
+
+#include 
+#include 
+
+vint8m1_t test_vloxei64_v_i8m1(const int8_t *base, vuint64m8_t bindex, size_t vl) {
+  return __riscv_vloxei64(base, bindex, vl); // expected-error {{call to undeclared function '__riscv_vloxei

[PATCH] D157474: [RISCV] Add missing Xsfvcp extension check in clang sema

2023-08-09 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat marked an inline comment as done.
4vtomat added inline comments.



Comment at: clang/test/Sema/rvv-required-features-invalid.c:16
+void test_sf_vc_x_se_u64m1(uint64_t rs1, size_t vl) { // expected-note 
{{'test_sf_vc_x_se_u64m1' declared here}}
+  __riscv_sf_vc_x_se_u64m1(1, 1, 1, rs1, vl); // expected-error {{call to 
undeclared function '__riscv_sf_vc_x_se_u64m1'}} expected-note {{did you mean 
'test_sf_vc_x_se_u64m1'?}}
+}

craig.topper wrote:
> This doesn't mention the xsfvcp extension. So it doesn't look like the 
> diagnostic in the code is being hit.
I guess it's just because `__riscv_sf_vc_x_se_u64m1` is too similar to 
`test_sf_vc_x_se_u64m1`, I just changed the name of the function, and the 
diagnostic just disappeared.


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[PATCH] D157580: [RISCV][NFC] Use named arguments in newly added changes

2023-08-09 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat accepted this revision.
4vtomat added a comment.

LGTM, thanks~


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[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-07-03 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 536947.
4vtomat marked 27 inline comments as done.
4vtomat added a comment.
Herald added a subscriber: wangpc.

Sorry for late update.
Resolved MaskRay's comments, thanks for detailed review!


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Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-extensions.c
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -198,6 +198,29 @@
 #endif
 }
 
+void llvm::riscvExtensionsHelp() {
+  errs() << "All available -march extensions for RISC-V\n\n";
+  errs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+errs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  errs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions)
+ExtMap[E.Name] = { E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+errs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  errs() << "\nUse -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -22,6 +22,8 @@
   unsigned MinorVersion;
 };
 
+void riscvExtensionsHelp();
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
Index: clang/tools/driver/cc1_main.cpp
===
--- clang/tools/driver/cc1_main.cpp
+++ clang/tools/driver/cc1_main.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TimeProfiler.h"
@@ -182,6 +183,14 @@
   return 0;
 }
 
+/// Print supported extensions of the RISCV target.
+static int print_supported_extensions() {
+  llvm::riscvExtensionsHelp();
+
+  return 0;
+}
+
+
 int cc1_main(ArrayRef Argv, const char *Argv0, void *MainAddr) {
   ensureSufficientStack();
 
@@ -221,6 +230,10 @@
   if (Clang->getFrontendOpts().PrintSupportedCPUs)
 return PrintSupportedCPUs(Clang->getTargetOpts().Triple);
 
+  // --print-supported-extensions takes priority over the actual compilation.
+  if (Clang->getFrontendOpts().PrintSupportedExtensions)
+return print_supported_extensions();
+
   // Infer the builtin include path if unspecified.
   if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
   Clang->getHeaderSearchOpts().ResourceDir.empty())
Index: clang/test/Driver/print-supported-extensions.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-extensions.c
@@ -0,0 +1,122 @@
+/// Test that --print-supported-extensions lists supported extensions.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang --target=riscv64 --print-supported-extensions 2>&1 | \
+// RUN:   FileCheck --implicit-check-not=warning --strict-whitespace --match-full-lines %s
+
+// CHECK:Target: riscv64
+// CHECK:All available -march extensions for RISC-V
+// CHECK:	NameVersion
+// CHECK-NEXT:	i   2.1
+// CHECK-NEXT:	e   2.0
+// CHECK-NEXT:	m   2.0
+// CHECK-NEXT:	a   2.1
+// CHECK-NEXT:	f   2.2
+// CHECK-NEXT:	d   2.2
+// CHECK-NEXT:	c   2.0
+// CHECK-NEXT:	v   1.0
+// CHECK-NEXT:	h   1.0
+// CHECK-NEXT:	zicbom  1.0
+// CHECK-NEXT:	zicbop  1.0
+// CHECK-NEXT:	zicboz  1.0
+// CHECK-NEXT:	zicntr  1.0
+// CHECK-NEXT:	zicsr   2.0
+// CHECK-NEXT:	zifencei2.0
+// CHECK-NEXT:	zihintpause 2.0
+// CHECK-NEXT:	zihpm   1.0
+// CHECK-NEXT:	zmmul   1.0
+// CHECK-NEXT:	zawrs   1.0
+// CHECK-NEXT:	zfh 1.0
+// CHECK-NEXT:	zfhmin  1.0
+// CHECK-NEXT:	zfinx   1

[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-07-03 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added inline comments.



Comment at: clang/test/Driver/print-supported-extensions.c:6
+// RUN: %clang --target=riscv64 --print-supported-extensions 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-RISCV
+

MaskRay wrote:
> MaskRay wrote:
> > Use `--implicit-check-not=warning:` instead of `// CHECK-NOT: warning: 
> > argument unused during compilation`.
> > 
> > We additionally check that there is no warning and the warning doesn't come 
> > after the output from `--print-supported-extensions`.
> For a file with just one prefix, conventionally we just use the default 
> `CHECK` and omit `--check-prefix`.
> 
> Have you ever checked that the test detects issues? `CHECK` below are ignored 
> with `--check-prefix=CHECK-RISCV`.
Oh, I missed it, CHECK-NEXT are all ignored...
thanks!!


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[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-07-03 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat marked an inline comment as done.
4vtomat added inline comments.



Comment at: clang/test/Driver/print-supported-extensions.c:3
+
+// REQUIRES: riscv-registered-target
+

MaskRay wrote:
> If you remove `all` and `RISCV` from `LLVM_TARGETS_TO_BUILD`, you can test 
> whether this feature works without lib/Target/RISCV support. I suspect it 
> works, so you may need another build for verification.
No it cause an error if I use the command with the target without riscv such 
as: 
```
bin/clang --target=aarch64 --print-supported-extensions
or
bin/clang --target=x86 --print-supported-extensions
```



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[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

2023-07-06 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, ormris, vkmr, 
frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, steven_wu, 
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simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
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Herald added a project: All.
4vtomat requested review of this revision.
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Herald added projects: clang, LLVM.

This is the vector calling convention based on
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389,
the idea is to split between "scalar" callee-saved registers
and "vector" callee-saved registers. "scalar" ones remain the
original strategy, however, "vector" ones are handled together
with RVV objects.

The stack layout would be:

  |--| <-- FP
  | callee-allocated save|
  | area for register varargs|
  |--|
  | callee-saved registers   | <-- scalar callee-saved
  |(scalar)  |
  |--|
  | RVV alignment padding|
  |--|
  | callee-saved registers   | <-- vector callee-saved
  |(vector)  |
  |--|
  | RVV objects  |
  |--|
  | padding before RVV   |
  |--|
  | scalar local variables   |
  |--| <-- BP
  | variable size objects|
  |--| <-- SP

Note: This patch doesn't contain "tuple" type, e.g. vint32m1x2.

  It will be handled in future patch once the PR389 is ready.


Repository:
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https://reviews.llvm.org/D154576

Files:
  clang/include/clang/Basic/Attr.td
  clang/include/clang/Basic/AttrDocs.td
  clang/include/clang/Basic/Specifiers.h
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/Type.cpp
  clang/lib/AST/TypePrinter.cpp
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/Basic/Targets/RISCV.h
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/lib/Sema/SemaType.cpp
  clang/test/CodeGen/RISCV/riscv-vector-cc-attr.c
  llvm/include/llvm/AsmParser/LLToken.h
  llvm/include/llvm/IR/CallingConv.h
  llvm/lib/AsmParser/LLLexer.cpp
  llvm/lib/AsmParser/LLParser.cpp
  llvm/lib/IR/AsmWriter.cpp
  llvm/lib/Target/RISCV/RISCVCallingConv.td
  llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
  llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll

Index: llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/callee-saved-regs.ll
@@ -0,0 +1,222 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+m -mattr=+v -O2 < %s \
+; RUN:| FileCheck --check-prefix=SPILL-O2 %s
+
+define  @test_vector_std( %va) nounwind {
+; SPILL-O2-LABEL: test_vector_std:
+; SPILL-O2:   # %bb.0: # %entry
+; SPILL-O2-NEXT:addi sp, sp, -16
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 1
+; SPILL-O2-NEXT:sub sp, sp, a0
+; SPILL-O2-NEXT:addi a0, sp, 16
+; SPILL-O2-NEXT:vs1r.v v8, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:#APP
+; SPILL-O2-NEXT:#NO_APP
+; SPILL-O2-NEXT:vl1r.v v8, (a0) # Unknown-size Folded Reload
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 1
+; SPILL-O2-NEXT:add sp, sp, a0
+; SPILL-O2-NEXT:addi sp, sp, 16
+; SPILL-O2-NEXT:ret
+entry:
+  call void asm sideeffect "",
+  "~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
+
+  ret  %va
+}
+
+define riscv_vector_cc  @test_vector_callee( %va) nounwind {
+; SPILL-O2-LABEL: test_vector_callee:
+; SPILL-O2:   # %bb.0: # %entry
+; SPILL-O2-NEXT:addi sp, sp, -16
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:slli a0, a0, 4
+; SPILL-O2-NEXT:sub sp, sp, a0
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 14
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v1, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 13
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v2, (a0) # Unknown-size Folded Spill
+; SPILL-O2-NEXT:csrr a0, vlenb
+; SPILL-O2-NEXT:li a1, 12
+; SPILL-O2-NEXT:mul a0, a0, a1
+; SPILL-O2-NEXT:add a0, sp, a0
+; SPILL-O2-NEXT:addi a0, a0, 16
+; SPILL-O2-NEXT:vs1r.v v3, (a0) # Un

[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

2023-07-06 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

In D154576#4476291 , @craig.topper 
wrote:

> Does this only change the calling convention when 
> `__attribute__((riscv_vector_cc))` is used? The attribute should be mentioned 
> in the patch description.

Yes it only changes when __attribute__((riscv_vector_cc)) is used, thanks for 
reminding, I will mention in the description.


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[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-07-11 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat marked an inline comment as done.
4vtomat added a comment.

@MaskRay if you are available, please help me to check the revision, thanks!!


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-07-11 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 539402.
4vtomat marked 12 inline comments as done.
4vtomat added a comment.

Resolved Craig's and Michael's comments.


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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Sema/SemaChecking.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intr

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-07-12 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat marked 2 inline comments as done.
4vtomat added inline comments.



Comment at: clang/include/clang/Basic/riscv_vector.td:2378
+
+multiclass RVVOutBuiltinSetP {

craig.topper wrote:
> What does `P` in this name mean? Is this because they use OP_P as their 
> opcode? If so I don't think that should be part of how we name intrinsics.
Sure, I will rename by appending Zvk suffix for clarifying it's meaning~



Comment at: clang/include/clang/Basic/riscv_vector.td:2381
+  if HasVV then {
+defvar suffix = !if(!or(HasVS, !eq(NAME, "vsm4r")), "vv", "v");
+// We don't need suffix in Zvkb extension since it's consider as normal

michaelmaitland wrote:
> Why do we check `HasVS` when assigning suffix `vv`? I would have expected we 
> use `HasVV`. In addition, why do we need to check `!eq(NAME, "vsm4r")` 
> instead of setting the `HasVV` for that instruction?
We check `HasVS` when assigning suffix `vv` because when the instruction has 
both `VV` and `VS` version, it uses double `v` as suffix, but if it just has 
`VS` version, it will use single `v` as suffix, that's why we check if it also 
has `VS` version in `HasVV` statement.
As per spec, the instruction name is vsm4r.v(single v), so it's an exception 
for `HasVV` case.



Comment at: clang/include/clang/Basic/riscv_vector.td:2400
+// mnemonics into its intrinsic function name.
+defvar suffix = !if(!eq(NAME, "vgmul"), "vv", "vs");
+defvar name = NAME # !if(!or(IsZvkb, !or(!eq(NAME, "vaesz"),

michaelmaitland wrote:
> Why not set `HasVS=1` and `HasVV=0` for `vaesz` instead of checking 
> `!if(!eq(NAME, "vgmul"),...`?
> 
> Also, do you mean to be discussing `vaesz` in the comment but use `vgmul` 
> below?
The reason we set these condition to check `vaesz` and `vgmul` is because they 
are exceptions.
They don't need suffix in their overloaded name since they only have one 
version.
`HasVS=1` and `HasVV=0` is not enough to determine this situation.



Comment at: clang/include/clang/Basic/riscv_vector.td:2423
+  defm vandn   : RVVIntBinBuiltinSet;
+  defm vbrev   : RVVOutBuiltinSetP<1, 0, 1, "csil", 1>;
+  defm vbrev8  : RVVOutBuiltinSetP<1, 0, 1, "csil", 1>;

craig.topper wrote:
> I think I'd prefer to see the Zvbb instructions use their own class and not 
> try to make `RVVOutBuiltinSetP` handle them and instructions that set HasVS.
It's a good idea, it will be much clearer and reduce the code size, thanks!



Comment at: clang/include/clang/Basic/riscv_vector.td:2449
+  let UnMaskedPolicyScheme = HasPassthruOperand in
+  defm vaeskf1 : RVVOutOp1BuiltinSet<"vaeskf1", "i", [["vi", "Uv", "UvUvUe"]]>;
+  defm vaeskf2 : RVVOutOp1BuiltinSetP<0>;

craig.topper wrote:
> I think the `Ue` needs a `K` since its required to be a constant? Also need 
> to update SemaChecking to verify the valid range.
> 
> I'm not sure whether we should use `Ue` or 'z' for constants.
I'm not sure what's the difference between `e` and `z`, but seems both of them 
works fine.
However K is needed.


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[PATCH] D158255: [RISCV][NFC] Update compile options for some vector crypto C intrinsics

2023-08-29 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 554591.
4vtomat added a comment.

Update Craig's comment.


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Files:
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c


Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %s
 
 #include 
 
Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %s
 
 #include 
 
Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %s
 
 #include 
 
Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %s
 
 #include 
 
Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %s
 
 #include 
 
Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
==

[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-08-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

In D146054#4596571 , @MaskRay wrote:

> In D146054#4587210 , @4vtomat wrote:
>
>> In D146054#4586067 , @MaskRay 
>> wrote:
>>
>>> I think the best place to test `RISCVISAInfo.cpp` is 
>>> `llvm/unittests/Support/RISCVISAInfoTest.cpp`.
>>>
>>> `clang/test/Driver/print-supported-extensions.c` can test just a few lines 
>>> (there will be some overlap with the testing in 
>>> `llvm/unittests/Support/RISCVISAInfoTest.cpp`), so that changes to RISC-V 
>>> extensions will generally not require updates to 
>>> `clang/test/Driver/print-supported-extensions.c`
>>
>> The goal of this patch is to list the supported extensions and their 
>> versions by providing an option, so I guess 
>> `clang/test/Driver/print-supported-extensions.c` aims differently with 
>> `llvm/unittests/Support/RISCVISAInfoTest.cpp` which is testing the 
>> functionalities in `RISCVISAInfoTest.cpp`.
>> `clang/test/Driver/print-supported-extensions.c` only tracks the extensions 
>> added and the their version changes and `riscvExtensionsHelp` in 
>> `llvm/lib/Support/RISCVISAInfo.cpp` doesn't have any input or output as well 
>> as any side effect, it only reads `SupportedExtensions` and 
>> `SupportedExperimentalExtensions` and dump the information.
>> So I think `clang/test/Driver/print-supported-extensions.c` is enough for 
>> this patch?
>
> My comment is about: the test is placed at the wrong layer. See 
> https://maskray.me/blog/2021-08-08-toolchain-testing#the-test-checks-at-the-wrong-layer
>
> I don't want that RISC-V development in LLVM causes repeated changes to 
> `clang/test/Driver`.

Got it, thanks!


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[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-08-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 554609.
4vtomat added a comment.

Resolved MaskRay's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp

Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -604,3 +604,140 @@
   EXPECT_EQ(ExtsRV64IDZce.count("zcmp"), 1U);
   EXPECT_EQ(ExtsRV64IDZce.count("zcmt"), 1U);
 }
+
+TEST(RiscvExtensionsHelp, CheckExtensions) {
+  std::string ExpectedOutput =
+R"(All available -march extensions for RISC-V
+
+	NameVersion
+	i   2.1
+	e   2.0
+	m   2.0
+	a   2.1
+	f   2.2
+	d   2.2
+	c   2.0
+	v   1.0
+	h   1.0
+	zicbom  1.0
+	zicbop  1.0
+	zicboz  1.0
+	zicntr  1.0
+	zicsr   2.0
+	zifencei2.0
+	zihintpause 2.0
+	zihpm   1.0
+	zmmul   1.0
+	zawrs   1.0
+	zfh 1.0
+	zfhmin  1.0
+	zfinx   1.0
+	zdinx   1.0
+	zca 1.0
+	zcb 1.0
+	zcd 1.0
+	zce 1.0
+	zcf 1.0
+	zcmp1.0
+	zcmt1.0
+	zba 1.0
+	zbb 1.0
+	zbc 1.0
+	zbkb1.0
+	zbkc1.0
+	zbkx1.0
+	zbs 1.0
+	zk  1.0
+	zkn 1.0
+	zknd1.0
+	zkne1.0
+	zknh1.0
+	zkr 1.0
+	zks 1.0
+	zksed   1.0
+	zksh1.0
+	zkt 1.0
+	zve32f  1.0
+	zve32x  1.0
+	zve64d  1.0
+	zve64f  1.0
+	zve64x  1.0
+	zvfh1.0
+	zvl1024b1.0
+	zvl128b 1.0
+	zvl16384b   1.0
+	zvl2048b1.0
+	zvl256b 1.0
+	zvl32768b   1.0
+	zvl32b  1.0
+	zvl4096b1.0
+	zvl512b 1.0
+	zvl64b  1.0
+	zvl65536b   1.0
+	zvl8192b1.0
+	zhinx   1.0
+	zhinxmin1.0
+	svinval 1.0
+	svnapot 1.0
+	svpbmt  1.0
+	xcvalu  1.0
+	xcvbi   1.0
+	xcvbitmanip 1.0
+	xcvmac  1.0
+	xcvsimd 1.0
+	xsfcie  1.0
+	xsfvcp  1.0
+	xtheadba1.0
+	xtheadbb1.0
+	xtheadbs1.0
+	xtheadcmo   1.0
+	xtheadcondmov   1.0
+	xtheadfmemidx   1.0
+	xtheadmac   1.0
+	xtheadmemidx1.0
+	xtheadmempair   1.0
+	xtheadsync  1.0
+	xtheadvdot  1.0
+	xventanacondops 1.0
+
+Experimental extensions
+	zicond  1.0
+	zihintntl   0.2
+	zacas   1.0
+	zfa 0.2
+	zfbfmin 0.8
+	ztso0.1
+	zvbb1.0
+	zvbc1.0
+	zvfbfmin0.8
+	zvfbfwma0.8
+	zvkg1.0
+	zvkn1.0
+	zvknc   1.0
+	zvkned  1.0
+	zvkng   1.0
+	zvknha  1.0
+	zvknhb  1.0
+	zvks1.0
+	zvksc   1.0
+	zvksed  1.0
+	zvksg   1.0
+	zvksh   1.0
+	zvkt1.0
+	smaia   1.0
+	ssaia   1.0
+
+Use -march to specify the target's extension.
+For example, clang -march=rv32i_v1p0)";
+
+  outs().flush();
+  testing::internal::CaptureStdout();
+
+  llvm::riscvExtensionsHelp();
+  outs().flush();
+
+  std::string CapturedOutput = testing::internal::GetCapturedStdout();
+  EXPECT_TRUE([](std::string &Captured, std::string &Expected) {
+return Captured.find(Expected) != std::string::npos;
+  }(CapturedOutput, ExpectedOutput));
+}
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -208,6 +208,29 @@
 #endif
 }
 
+void llvm::riscvExtensionsHelp() {
+  outs() << "All available -march extensions for RISC-V\n\n";
+  outs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = {E.Version.Major, E.Versi

[PATCH] D158255: [RISCV][NFC] Update compile options for some vector crypto C intrinsics

2023-08-30 Thread Brandon Wu via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGbb47721fb743: [RISCV][NFC] Update compile options for some 
vector crypto C intrinsics (authored by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158255/new/

https://reviews.llvm.org/D158255

Files:
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c


Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vctz.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %s
 
 #include 
 
Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vcpopv.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %s
 
 #include 
 
Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vclz.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %s
 
 #include 
 
Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vctz.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %s
 
 #include 
 
Index: 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
===
--- 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
+++ 
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vcpopv.c
@@ -1,6 +1,6 @@
 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -disable-O0-optnone 
-emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature 
+experimental-zvbb -disable-O0-optnone -emit-llvm %s -o - | opt -S 
-passes=mem2reg | FileCheck %

[PATCH] D158257: [RISCV] Add feature checks for vector crypto C intrinsics

2023-08-30 Thread Brandon Wu via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8609819eb1c3: [RISCV] Add feature checks for vector crypto C 
intrinsics (authored by 4vtomat).

Changed prior to commit:
  https://reviews.llvm.org/D158257?vs=551419&id=554896#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158257/new/

https://reviews.llvm.org/D158257

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf1-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vaeskf2-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm3c-out-of-range.c
  clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vsm4k-out-of-range.c
  clang/test/Sema/zvk-invalid-features.c
  clang/test/Sema/zvk-invalid-vlen.c
  clang/test/Sema/zvk-invalid.c
  clang/utils/TableGen/RISCVVEmitter.cpp

Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -655,6 +655,14 @@
   .Case("RV64", RVV_REQ_RV64)
   .Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
   .Case("Xsfvcp", RVV_REQ_Xsfvcp)
+  .Case("Zvbb", RVV_REQ_Zvbb)
+  .Case("Zvbc", RVV_REQ_Zvbc)
+  .Case("Zvkb", RVV_REQ_Zvkb)
+  .Case("Zvkg", RVV_REQ_Zvkg)
+  .Case("Zvkned", RVV_REQ_Zvkned)
+  .Case("Zvknha", RVV_REQ_Zvknha)
+  .Case("Zvksed", RVV_REQ_Zvksed)
+  .Case("Zvksh", RVV_REQ_Zvksh)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
   SR.RequiredExtensions |= RequireExt;
Index: clang/test/Sema/zvk-invalid-vlen.c
===
--- clang/test/Sema/zvk-invalid-vlen.c
+++ clang/test/Sema/zvk-invalid-vlen.c
@@ -1,5 +1,6 @@
 // REQUIRES: riscv-registered-target
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -fsyntax-only -verify
+// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvkned \
+// RUN:   -target-feature +experimental-zvksh %s -fsyntax-only -verify
 
 #include 
 
Index: clang/test/Sema/zvk-invalid-features.c
===
--- /dev/null
+++ clang/test/Sema/zvk-invalid-features.c
@@ -0,0 +1,48 @@
+// REQUIRES: riscv-registered-target
+// RUN: %clang_cc1 -triple riscv64 %s -fsyntax-only -verify
+
+void test_zvk_features() {
+  // zvbb
+  __riscv_vbrev(); // expected-error {{call to undeclared function '__riscv_vbrev'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vclz(); // expected-error {{call to undeclared function '__riscv_vclz'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vctz(); // expected-error {{call to undeclared function '__riscv_vctz'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vcpopv(); // expected-error {{call to undeclared function '__riscv_vcpopv'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vwsll(); // expected-error {{call to undeclared function '__riscv_vwsll'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvbc
+  __riscv_vclmul(); // expected-error {{call to undeclared function '__riscv_vclmul'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vclmulh(); // expected-error {{call to undeclared function '__riscv_vclmulh'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkb
+  __riscv_vandn(); // expected-error {{call to undeclared function '__riscv_vandn'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vbrev8(); // expected-error {{call to undeclared function '__riscv_vbrev8'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vrev8(); // expected-error {{call to undeclared function '__riscv_vrev8'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vrol(); // expected-error {{call to undeclared function '__riscv_vrol'; ISO C99 and later do not support implicit function declarations}}
+  __riscv_vror(); // expected-error {{call to undeclared function '__riscv_vror'; ISO C99 and later do not support implicit function declarations}}
+
+  // zvkg
+  __riscv_vghsh(); // expected-error {{call to undeclared function '__riscv_vghsh'; ISO C99 and later do not

[PATCH] D146054: [RISCV] Add --print-supported-extensions support

2023-08-31 Thread Brandon Wu via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG4b40ced4e5ba: [RISCV] Add --print-supported-extensions 
support (authored by 4vtomat).

Changed prior to commit:
  https://reviews.llvm.org/D146054?vs=554609&id=554921#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146054/new/

https://reviews.llvm.org/D146054

Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp

Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -626,3 +626,143 @@
   EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension(""), "");
   EXPECT_EQ(RISCVISAInfo::getTargetFeatureForExtension("zbbzihintntl"), "");
 }
+
+TEST(RiscvExtensionsHelp, CheckExtensions) {
+  std::string ExpectedOutput =
+R"(All available -march extensions for RISC-V
+
+	NameVersion
+	i   2.1
+	e   2.0
+	m   2.0
+	a   2.1
+	f   2.2
+	d   2.2
+	c   2.0
+	v   1.0
+	h   1.0
+	zicbom  1.0
+	zicbop  1.0
+	zicboz  1.0
+	zicntr  1.0
+	zicsr   2.0
+	zifencei2.0
+	zihintntl   1.0
+	zihintpause 2.0
+	zihpm   1.0
+	zmmul   1.0
+	zawrs   1.0
+	zfh 1.0
+	zfhmin  1.0
+	zfinx   1.0
+	zdinx   1.0
+	zca 1.0
+	zcb 1.0
+	zcd 1.0
+	zce 1.0
+	zcf 1.0
+	zcmp1.0
+	zcmt1.0
+	zba 1.0
+	zbb 1.0
+	zbc 1.0
+	zbkb1.0
+	zbkc1.0
+	zbkx1.0
+	zbs 1.0
+	zk  1.0
+	zkn 1.0
+	zknd1.0
+	zkne1.0
+	zknh1.0
+	zkr 1.0
+	zks 1.0
+	zksed   1.0
+	zksh1.0
+	zkt 1.0
+	zve32f  1.0
+	zve32x  1.0
+	zve64d  1.0
+	zve64f  1.0
+	zve64x  1.0
+	zvfh1.0
+	zvfhmin 1.0
+	zvl1024b1.0
+	zvl128b 1.0
+	zvl16384b   1.0
+	zvl2048b1.0
+	zvl256b 1.0
+	zvl32768b   1.0
+	zvl32b  1.0
+	zvl4096b1.0
+	zvl512b 1.0
+	zvl64b  1.0
+	zvl65536b   1.0
+	zvl8192b1.0
+	zhinx   1.0
+	zhinxmin1.0
+	svinval 1.0
+	svnapot 1.0
+	svpbmt  1.0
+	xcvalu  1.0
+	xcvbi   1.0
+	xcvbitmanip 1.0
+	xcvmac  1.0
+	xcvsimd 1.0
+	xsfcie  1.0
+	xsfvcp  1.0
+	xtheadba1.0
+	xtheadbb1.0
+	xtheadbs1.0
+	xtheadcmo   1.0
+	xtheadcondmov   1.0
+	xtheadfmemidx   1.0
+	xtheadmac   1.0
+	xtheadmemidx1.0
+	xtheadmempair   1.0
+	xtheadsync  1.0
+	xtheadvdot  1.0
+	xventanacondops 1.0
+
+Experimental extensions
+	zicfilp 0.2
+	zicond  1.0
+	zacas   1.0
+	zfa 0.2
+	zfbfmin 0.8
+	ztso0.1
+	zvbb1.0
+	zvbc1.0
+	zvfbfmin0.8
+	zvfbfwma0.8
+	zvkb1.0
+	zvkg1.0
+	zvkn1.0
+	zvknc   1.0
+	zvkned  1.0
+	zvkng   1.0
+	zvknha  1.0
+	zvknhb  1.0
+	zvks1.0
+	zvksc   1.0
+	zvksed  1.0
+	zvksg   1.0
+	zvksh   1.0
+	zvkt1.0
+	smaia   1.0
+	ssaia   1.0
+
+Use -march to specify the target's extension.
+For example, clang -march=rv32i_v1p0)";
+
+  outs().flush();
+  testing::internal::CaptureStdout();
+
+  llvm::riscvExtensionsHelp();
+  outs().flush();
+
+  std::string CapturedOutput = testing::internal::GetCapturedStdout();
+  EXPECT_TRUE([](std::string &Captured, std::string &Expected) {
+return Captured.find(Expected) != std::string::npos;
+  }(CapturedOutput, ExpectedOutput));
+}
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISC

[PATCH] D158050: [RISCV] RISCV vector calling convention (2/2)

2023-09-01 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 555304.
4vtomat added a comment.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

Finish handling vector arguments in backend.


Repository:
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Files:
  clang/include/clang/AST/Type.h
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenera

[PATCH] D158050: [RISCV] RISCV vector calling convention (2/2)

2023-09-01 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

`RVVArgDispatcher` is the class used to compute and maximize the register usage 
by using the vector argument information placed in `std::vector`, 
it's both used by `frontend` and `backend`.
Currently I'm not sure where is the better file to place this class, so I just 
place it in `RISCVTargetParser.h`.


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[PATCH] D158050: [RISCV] RISCV vector calling convention (2/2)

2023-09-01 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 555307.
4vtomat edited the summary of this revision.
4vtomat added a comment.

Update commit message.


Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/AST/Type.h
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsac.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vnmsub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaaddu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vand.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasub.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vasubu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vdivu.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfdiv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmax.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmin.c
  
clang/test/CodeGen/RI

[PATCH] D138803: [RISCV] Support vector crypto extension C intrinsics

2022-11-28 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
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Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Repository:
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https://reviews.llvm.org/D138803

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesdf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesdm.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesef.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaeskf1.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaeskf2.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesz.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vandn.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vbrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vclmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vclmulh.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vghmac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrol.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vror.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2ch.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2cl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2ms.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm3c.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm3me.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm4k.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm4r.c

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[PATCH] D138805: [RISCV] Support vector crypto extension C intrinsics

2022-11-28 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Repository:
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Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesdf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesdm.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesef.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaeskf1.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaeskf2.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesz.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vandn.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vbrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vclmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vclmulh.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vghmac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrol.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vror.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2ch.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2cl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2ms.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm3c.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm3me.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm4k.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm4r.c

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[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2022-11-28 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, jdoerfert, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
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MaskRay.
Herald added projects: clang, LLVM.

Repository:
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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/rv64zvkb.s
  llvm/test/MC/RISCV/rvv/rv64zvkg.s
  llvm/test/MC/RISCV/rvv/rv64zvknf.s
  llvm/test/MC/RISCV/rvv/rv64zvknha.s
  llvm/test/MC/RISCV/rvv/rv64zvknhb.s
  llvm/test/MC/RISCV/rvv/rv64zvkns.s
  llvm/test/MC/RISCV/rvv/rv64zvksed.s
  llvm/test/MC/RISCV/rvv/rv64zvksh.s

Index: llvm/test/MC/RISCV/rvv/rv64zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x57,0xb5,0x93,0xd6]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 57 b5 93 d6   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x57,0x35,0x94,0xda]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 57 35 94 da   
Index: llvm/test/MC/RISCV/rvv/rv64zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x57,0xb5,0x93,0xea]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 57 b5 93 ea   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x57,0x35,0x90,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 57 35 90 ee   
Index: llvm/test/MC/RISCV/rvv/rv64zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns.s
@@ -0,0 +1,87 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvkns %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvkns %s \
+# RUN:| llvm-objdump -d --mattr=+zvkns  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvkns %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vaesdf.vv v10, v9
+# CHECK-INST: vaesdf.vv v10, v9
+# CHECK-ENCODING: [0x57,0x05,0x90,0xee]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 05 90 ee   
+
+vaesdf.vs v10, v9
+# CHECK-INST: vaesdf.vs v10, v9
+# CHECK-ENCODING: [0x57,0x65,0x90,0x66]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 65 90 66   
+
+vaesef.vv v10, v9
+# CHECK-INST: vaesef.vv v10, v9
+# CHECK-ENCODING: [0x57,0x05,0x90,0xf6]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 57 05 90 f6   
+   
+vaesef.vs v10, v9
+# CHECK-INST: vaesef.vs v10, v9
+# CHECK-ENCODING: [0x57,0x65,0x90,0

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2022-11-28 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: sunshaoce, VincentWu, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Depends on D138807 , D138809 



Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138810

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesdf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesdm.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesef.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaeskf1.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaeskf2.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesz.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vandn.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vbrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vclmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vclmulh.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vghmac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrol.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vror.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2ch.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2cl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2ms.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm3c.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm3me.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm4k.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm4r.c

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[PATCH] D138807: [RISCV] Support vector crypto extension ISA string and assembly

2022-11-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 479142.
4vtomat added a comment.

Fixed the comment from Craig Topper and Philip Reames


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138807/new/

https://reviews.llvm.org/D138807

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/rv64zvkb.s
  llvm/test/MC/RISCV/rvv/rv64zvkg.s
  llvm/test/MC/RISCV/rvv/rv64zvknha.s
  llvm/test/MC/RISCV/rvv/rv64zvknhb.s
  llvm/test/MC/RISCV/rvv/rv64zvkns.s
  llvm/test/MC/RISCV/rvv/rv64zvksed.s
  llvm/test/MC/RISCV/rvv/rv64zvksh.s

Index: llvm/test/MC/RISCV/rvv/rv64zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh'
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/rv64zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvksed.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed'
+# CHECK-UNKNOWN: 77 25 98 a2   
Index: llvm/test/MC/RISCV/rvv/rv64zvkns.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/rv64zvkns.s
@@ -0,0 +1,75 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvkns %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvkns %s \
+# RUN:| llvm-objdump -d --mattr=+experimental-zvkns  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvkns %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vaesdf.vv v10, v9
+# CHECK-INST: vaesdf.vv v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x90,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 a5 90 a2   
+
+vaesdf.vs v10, v9
+# CHECK-INST: vaesdf.vs v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x90,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 a5 90 a6   
+
+vaesef.vv v10, v9
+# CHECK-INST: vaesef.vv v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x91,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkns'
+# CHECK-UNKNOWN: 77 a5 91 a2   
+   
+vaesef.vs v10, v9
+# CHECK-INST: vaesef.vs v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x91,0xa6]
+# CHECK-ERROR: instruction req

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2022-11-30 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 479144.
4vtomat added a comment.

Fixed the comment from Craig Topper and Philip Reames


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138810/new/

https://reviews.llvm.org/D138810

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesdf.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesdm.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesef.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesem.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaeskf1.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaeskf2.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vaesz.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vandn.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vbrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vclmul.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vclmulh.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vghmac.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrev8.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vrol.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vror.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2ch.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2cl.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsha2ms.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm3c.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm3me.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm4k.c
  clang/test/CodeGen/RISCV/rvv-intrinsics/vsm4r.c

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[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

2023-03-14 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D146054

Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-marchs.c
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -17,6 +17,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -139,6 +140,34 @@
 {"ztso", RISCVExtensionVersion{0, 1}},
 };
 
+void RISCVMarchHelp() {
+  auto Cmp = [](const RISCVSupportedExtension &a,
+const RISCVSupportedExtension &b) {
+   StringRef aRef{a.Name}, bRef{b.Name};
+   return std::tie(aRef, a.Version.Major, a.Version.Minor) <
+  std::tie(bRef, b.Version.Major, b.Version.Minor); };
+
+  errs() << "All available -march extensions for RISC-V\n\n";
+  errs() << '\t' << left_justify("Name", 20) << "Version\n";
+  std::set TempSet(Cmp);
+  for (auto E : SupportedExtensions)
+TempSet.insert(E);
+  for (auto E : TempSet)
+errs() << format("\t%-20s%d.%d\n", E.Name, E.Version.Major, E.Version.Minor);
+
+  errs() << "\nExperimental extensions\n";
+  TempSet.clear();
+  for (auto E : SupportedExperimentalExtensions)
+TempSet.insert(E);
+  for (auto E : TempSet)
+errs() << format("\t%-20s%d.%d\n",
+ E.Name, E.Version.Major, E.Version.Minor);
+  errs() << '\n';
+
+  errs() << "Use -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: clang/test/Driver/print-supported-marchs.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-marchs.c
@@ -0,0 +1,98 @@
+// Test that --print-supported-marchs lists supported Marchs.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang --target=riscv64 --print-supported-marchs 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-RISCV
+
+// Test -march=help alias.
+// RUN: %clang --target=riscv64 -march=help 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-RISCV
+
+// CHECK-NOT: warning: argument unused during compilation
+// CHECK-RISCV: Target: riscv64
+// CHECK-RISCV: All available -march extensions for RISC-V
+// CHECK-RISCV: 	NameVersion
+// CHECK-RISCV: 	a   2.0
+// CHECK-RISCV: 	c   2.0
+// CHECK-RISCV: 	d   2.0
+// CHECK-RISCV: 	e   1.9
+// CHECK-RISCV: 	f   2.0
+// CHECK-RISCV: 	h   1.0
+// CHECK-RISCV: 	i   2.0
+// CHECK-RISCV: 	m   2.0
+// CHECK-RISCV: 	svinval 1.0
+// CHECK-RISCV: 	svnapot 1.0
+// CHECK-RISCV: 	svpbmt  1.0
+// CHECK-RISCV: 	v   1.0
+// CHECK-RISCV: 	xtheadba1.0
+// CHECK-RISCV: 	xtheadbb1.0
+// CHECK-RISCV: 	xtheadbs1.0
+// CHECK-RISCV: 	xtheadcmo   1.0
+// CHECK-RISCV: 	xtheadcondmov   1.0
+// CHECK-RISCV: 	xtheadfmemidx   1.0
+// CHECK-RISCV: 	xtheadmac   1.0
+// CHECK-RISCV: 	xtheadmemidx1.0
+// CHECK-RISCV: 	xtheadmempair   1.0
+// CHECK-RISCV: 	xtheadsync  1.0
+// CHECK-RISCV: 	xtheadvdot  1.0
+// CHECK-RISCV: 	xventanacondops 1.0
+// CHECK-RISCV: 	zawrs   1.0
+// CHECK-RISCV: 	zba 1.0
+// CHECK-RISCV: 	zbb 1.0
+// CHECK-RISCV: 	zbc 1.0
+// CHECK-RISCV: 	zbkb1.0
+// CHECK-RISCV: 	zbkc1.0
+// CHECK-RISCV: 	zbkx1.0
+// CHECK-RISCV: 	zbs 1.0
+// CHECK-RISCV: 	zdinx   1.0
+// CHECK-RISCV: 	zfh 1.0
+// CHECK-RISCV: 	zfhmin  1.0
+// CHECK-RISCV: 	zfinx   1.0
+// CHECK-RISCV: 	zhinx   1.0
+// CHECK-RISCV: 	zhinxmin1.0
+// CHECK-RISCV: 	zicbom  1.0
+// CHECK-RISCV: 	zicbop  1.0
+// CHECK-RISCV: 	zicboz  1.0
+// CHECK-RISCV: 	zicsr   2.0
+// CHECK-RISCV: 	zifencei2.0
+// CHECK-RISCV: 	zihintpause 2.0
+// CHECK-RISCV: 	zk  1.0
+// CHECK-RISCV: 	zkn 1.0
+// CH

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

2023-03-14 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 505112.
4vtomat added a comment.

Resolved Craig's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141672/new/

https://reviews.llvm.org/D141672

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvkned-invalid.s
  llvm/test/MC/RISCV/rvv/zvkned.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvknh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvknh.s
@@ -0,0 +1,34 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+expe

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

2023-03-17 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 506062.
4vtomat added a comment.

Resolved Craig and Kito's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146054/new/

https://reviews.llvm.org/D146054

Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-marchs.c
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -139,6 +139,33 @@
 {"ztso", RISCVExtensionVersion{0, 1}},
 };
 
+namespace llvm {
+void RISCVMarchHelp() {
+  errs() << "All available -march extensions for RISC-V\n\n";
+  errs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = { E.Name, E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+errs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  errs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions)
+ExtMap[E.Name] = { E.Name, E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+errs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  errs() << '\n';
+
+  errs() << "Use -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -23,6 +23,8 @@
   unsigned MinorVersion;
 };
 
+void RISCVMarchHelp();
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
Index: clang/tools/driver/cc1_main.cpp
===
--- clang/tools/driver/cc1_main.cpp
+++ clang/tools/driver/cc1_main.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TimeProfiler.h"
@@ -182,6 +183,27 @@
   return 0;
 }
 
+/// Print supported marchs of the given target.
+static int PrintSupportedMarchs(std::string TargetStr) {
+  std::string Error;
+  const llvm::Target *TheTarget =
+  llvm::TargetRegistry::lookupTarget(TargetStr, Error);
+  if (!TheTarget) {
+llvm::errs() << Error;
+return 1;
+  }
+
+  if (TargetStr.find("riscv") == std::string::npos) {
+llvm::errs() << "The -march=help only supports for RISCV target.\n";
+return 1;
+  }
+
+  llvm::RISCVMarchHelp();
+
+  return 0;
+}
+
+
 int cc1_main(ArrayRef Argv, const char *Argv0, void *MainAddr) {
   ensureSufficientStack();
 
@@ -223,6 +245,10 @@
   if (Clang->getFrontendOpts().PrintSupportedCPUs)
 return PrintSupportedCPUs(Clang->getTargetOpts().Triple);
 
+  // --print-supported-marchs takes priority over the actual compilation.
+  if (Clang->getFrontendOpts().PrintSupportedMarchs)
+return PrintSupportedMarchs(Clang->getTargetOpts().Triple);
+
   // Infer the builtin include path if unspecified.
   if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
   Clang->getHeaderSearchOpts().ResourceDir.empty())
Index: clang/test/Driver/print-supported-marchs.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-marchs.c
@@ -0,0 +1,98 @@
+// Test that --print-supported-marchs lists supported Marchs.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang --target=riscv64 --print-supported-marchs 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-RISCV
+
+// Test -march=help alias.
+// RUN: %clang --target=riscv64 -march=help 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-RISCV
+
+// CHECK-NOT: warning: argument unused during compilation
+// CHECK-RISCV: Target: riscv64
+// CHECK-RISCV: All available -march extensions for RISC-V
+// CHECK-RISCV: 	NameVersion
+// CHECK-RISCV: 	i   2.0
+// CHECK-RISCV: 	e   1.9
+// CHECK-RISCV: 	m   2.0
+// CHECK-RISCV: 	a   2.0
+// CHECK-RISCV: 	f   2.0
+// CHECK-RISCV: 	d   2.0
+// CHECK-RISCV: 	c   2.0
+// CHECK-RISCV: 	v   1.0
+// CHECK-RISCV: 	h   1.0
+// CHECK-RISCV: 	svinval

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

2023-03-21 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 506894.
4vtomat added a comment.

Resolved Craig's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141672/new/

https://reviews.llvm.org/D141672

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvkned-invalid.s
  llvm/test/MC/RISCV/rvv/zvkned.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvknh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvknh.s
@@ -0,0 +1,34 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+exper

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

2023-03-25 Thread Brandon Wu via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG9795aa042a84: [RISCV] Support vector crypto extension ISA 
string and assembly (authored by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141672/new/

https://reviews.llvm.org/D141672

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvkned-invalid.s
  llvm/test/MC/RISCV/rvv/zvkned.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvknh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvknh.s
@@ -0,0 +1,34 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

2023-03-26 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 508461.
4vtomat added a comment.

Resolved MaskRay and Craig's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146054/new/

https://reviews.llvm.org/D146054

Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-marchs.c
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -139,6 +139,29 @@
 {"ztso", RISCVExtensionVersion{0, 1}},
 };
 
+void llvm::riscvMarchHelp() {
+  errs() << "All available -march extensions for RISC-V\n\n";
+  errs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = { E.Name, E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+errs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  errs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions)
+ExtMap[E.Name] = { E.Name, E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+errs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  errs() << "\nUse -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -23,6 +23,8 @@
   unsigned MinorVersion;
 };
 
+void riscvMarchHelp();
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
Index: clang/tools/driver/cc1_main.cpp
===
--- clang/tools/driver/cc1_main.cpp
+++ clang/tools/driver/cc1_main.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TimeProfiler.h"
@@ -182,6 +183,22 @@
   return 0;
 }
 
+/// Print supported marchs of the given target.
+static int PrintSupportedMarchs(std::string TargetStr) {
+  std::string Error;
+  const llvm::Target *TheTarget =
+  llvm::TargetRegistry::lookupTarget(TargetStr, Error);
+  if (!TheTarget) {
+llvm::errs() << Error;
+return 1;
+  }
+
+  llvm::riscvMarchHelp();
+
+  return 0;
+}
+
+
 int cc1_main(ArrayRef Argv, const char *Argv0, void *MainAddr) {
   ensureSufficientStack();
 
@@ -223,6 +240,10 @@
   if (Clang->getFrontendOpts().PrintSupportedCPUs)
 return PrintSupportedCPUs(Clang->getTargetOpts().Triple);
 
+  // --print-supported-marchs takes priority over the actual compilation.
+  if (Clang->getFrontendOpts().PrintSupportedMarchs)
+return PrintSupportedMarchs(Clang->getTargetOpts().Triple);
+
   // Infer the builtin include path if unspecified.
   if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
   Clang->getHeaderSearchOpts().ResourceDir.empty())
Index: clang/test/Driver/print-supported-marchs.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-marchs.c
@@ -0,0 +1,98 @@
+// Test that --print-supported-marchs lists supported Marchs.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang --target=riscv64 --print-supported-marchs 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-RISCV
+
+// Test -march=help alias.
+// RUN: %clang --target=riscv64 -march=help 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-RISCV
+
+// CHECK-NOT: warning: argument unused during compilation
+// CHECK-RISCV: Target: riscv64
+// CHECK-NEXT: All available -march extensions for RISC-V
+// CHECK-NEXT: 	NameVersion
+// CHECK-NEXT: 	i   2.0
+// CHECK-NEXT: 	e   1.9
+// CHECK-NEXT: 	m   2.0
+// CHECK-NEXT: 	a   2.0
+// CHECK-NEXT: 	f   2.0
+// CHECK-NEXT: 	d   2.0
+// CHECK-NEXT: 	c   2.0
+// CHECK-NEXT: 	v   1.0
+// CHECK-NEXT: 	h   1.0
+// CHECK-NEXT: 	svinval 1.0
+// CHECK-NEXT: 	svnapot 1.0
+// CHECK-NEXT: 	svpbmt  1.0
+// CHECK-NEXT: 	zicbom  1.0
+// CHECK-NEXT: 	zicbop  1.0
+// CHECK-NEXT: 	zicboz

[PATCH] D146054: [RISCV] Add -print-supported-marchs and -march=help support

2023-03-26 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 508475.
4vtomat added a comment.

Resolved Craig's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146054/new/

https://reviews.llvm.org/D146054

Files:
  clang/include/clang/Driver/Options.td
  clang/include/clang/Frontend/FrontendOptions.h
  clang/lib/Driver/Driver.cpp
  clang/test/Driver/print-supported-marchs.c
  clang/tools/driver/cc1_main.cpp
  llvm/include/llvm/Support/RISCVISAInfo.h
  llvm/lib/Support/RISCVISAInfo.cpp

Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -139,6 +139,29 @@
 {"ztso", RISCVExtensionVersion{0, 1}},
 };
 
+void llvm::riscvMarchHelp() {
+  errs() << "All available -march extensions for RISC-V\n\n";
+  errs() << '\t' << left_justify("Name", 20) << "Version\n";
+
+  RISCVISAInfo::OrderedExtensionMap ExtMap;
+  for (const auto &E : SupportedExtensions)
+ExtMap[E.Name] = { E.Name, E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+errs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  errs() << "\nExperimental extensions\n";
+  ExtMap.clear();
+  for (const auto &E : SupportedExperimentalExtensions)
+ExtMap[E.Name] = { E.Name, E.Version.Major, E.Version.Minor };
+  for (const auto &E : ExtMap)
+errs() << format("\t%-20s%d.%d\n", E.first.c_str(), E.second.MajorVersion,
+ E.second.MinorVersion);
+
+  errs() << "\nUse -march to specify the target's extension.\n"
+"For example, clang -march=rv32i_v1p0\n";
+}
+
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
Index: llvm/include/llvm/Support/RISCVISAInfo.h
===
--- llvm/include/llvm/Support/RISCVISAInfo.h
+++ llvm/include/llvm/Support/RISCVISAInfo.h
@@ -23,6 +23,8 @@
   unsigned MinorVersion;
 };
 
+void riscvMarchHelp();
+
 class RISCVISAInfo {
 public:
   RISCVISAInfo(const RISCVISAInfo &) = delete;
Index: clang/tools/driver/cc1_main.cpp
===
--- clang/tools/driver/cc1_main.cpp
+++ clang/tools/driver/cc1_main.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/ManagedStatic.h"
 #include "llvm/Support/Path.h"
 #include "llvm/Support/Process.h"
+#include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Support/TimeProfiler.h"
@@ -182,6 +183,14 @@
   return 0;
 }
 
+/// Print supported extensions of the given target.
+static int PrintSupportedExtensions(std::string TargetStr) {
+  llvm::riscvMarchHelp();
+
+  return 0;
+}
+
+
 int cc1_main(ArrayRef Argv, const char *Argv0, void *MainAddr) {
   ensureSufficientStack();
 
@@ -223,6 +232,10 @@
   if (Clang->getFrontendOpts().PrintSupportedCPUs)
 return PrintSupportedCPUs(Clang->getTargetOpts().Triple);
 
+  // --print-supported-extensions takes priority over the actual compilation.
+  if (Clang->getFrontendOpts().PrintSupportedExtensions)
+return PrintSupportedExtensions(Clang->getTargetOpts().Triple);
+
   // Infer the builtin include path if unspecified.
   if (Clang->getHeaderSearchOpts().UseBuiltinIncludes &&
   Clang->getHeaderSearchOpts().ResourceDir.empty())
Index: clang/test/Driver/print-supported-marchs.c
===
--- /dev/null
+++ clang/test/Driver/print-supported-marchs.c
@@ -0,0 +1,98 @@
+// Test that --print-supported-extensions lists supported extensions.
+
+// REQUIRES: riscv-registered-target
+
+// RUN: %clang --target=riscv64 --print-supported-extensions 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-RISCV
+
+// Test -march=help alias.
+// RUN: %clang --target=riscv64 -march=help 2>&1 | \
+// RUN:   FileCheck %s --check-prefix=CHECK-RISCV
+
+// CHECK-NOT: warning: argument unused during compilation
+// CHECK-RISCV: Target: riscv64
+// CHECK-NEXT: All available -march extensions for RISC-V
+// CHECK-NEXT: 	NameVersion
+// CHECK-NEXT: 	i   2.0
+// CHECK-NEXT: 	e   1.9
+// CHECK-NEXT: 	m   2.0
+// CHECK-NEXT: 	a   2.0
+// CHECK-NEXT: 	f   2.0
+// CHECK-NEXT: 	d   2.0
+// CHECK-NEXT: 	c   2.0
+// CHECK-NEXT: 	v   1.0
+// CHECK-NEXT: 	h   1.0
+// CHECK-NEXT: 	svinval 1.0
+// CHECK-NEXT: 	svnapot 1.0
+// CHECK-NEXT: 	svpbmt  1.0
+// CHECK-NEXT: 	zicbom  1.0
+// CHECK-NEXT: 	zicbop  1.0
+// CHECK-NEXT: 	zicboz  1.0
+// CHECK-NEXT: 	zicsr   2.0
+// CHECK-NEXT: 	zifencei2.0
+// CHECK-NEXT: 	zihintpause 2.0
+// CHECK-NEXT: 	zmmul

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-03-27 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 508539.
4vtomat added a comment.
Herald added subscribers: jobnoorman, luke.

Updated to spec version 20230206.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138810/new/

https://reviews.llvm.org/D138810

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3me.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4k.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaeskf2.

[PATCH] D141672: [RISCV] Support vector crypto extension ISA string and assembly

2023-03-09 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 504034.
4vtomat added a comment.

Resolved Craig's comments and rename *zvkns* files to *zvkned*.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141672/new/

https://reviews.llvm.org/D141672

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s
  llvm/test/MC/RISCV/rvv/zvkned-invalid.s
  llvm/test/MC/RISCV/rvv/zvkned.s
  llvm/test/MC/RISCV/rvv/zvknh.s
  llvm/test/MC/RISCV/rvv/zvksed-invalid.s
  llvm/test/MC/RISCV/rvv/zvksed.s
  llvm/test/MC/RISCV/rvv/zvksh.s

Index: llvm/test/MC/RISCV/rvv/zvksh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksh.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksh  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksh %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm3c.vi v10, v9, 7
+# CHECK-INST: vsm3c.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0xae]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 ae   
+
+vsm3me.vv v10, v9, v8
+# CHECK-INST: vsm3me.vv v10, v9, v8
+# CHECK-ENCODING: [0x77,0x25,0x94,0x82]
+# CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 94 82   
Index: llvm/test/MC/RISCV/rvv/zvksed.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvksed  - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvksed %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsm4k.vi v10, v9, 7
+# CHECK-INST: vsm4k.vi v10, v9, 7
+# CHECK-ENCODING: [0x77,0xa5,0x93,0x86]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 a5 93 86   
+
+vsm4r.vv v10, v9
+# CHECK-INST: vsm4r.vv v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a2   
+
+vsm4r.vs v10, v9
+# CHECK-INST: vsm4r.vs v10, v9
+# CHECK-ENCODING: [0x77,0x25,0x98,0xa6]
+# CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions.){{$}}
+# CHECK-UNKNOWN: 77 25 98 a6   
Index: llvm/test/MC/RISCV/rvv/zvksed-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvksed-invalid.s
@@ -0,0 +1,5 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+zve32x --mattr=+experimental-zvksed -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+vsm4k.vi v10, v9, 8
+# CHECK-ERROR: immediate must be an integer in the range [0, 7]
Index: llvm/test/MC/RISCV/rvv/zvknh.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvknh.s
@@ -0,0 +1,34 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvknha %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zve64x --mattr=+experimental-zvknhb %s \
+# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filet

[PATCH] D153836: [RISCV] Bump vector crypto to v1.0.0-rc1

2023-06-27 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
jdoerfert, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, hiraditya, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, eopXD, MaskRay.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153836

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -111,50 +111,50 @@
 .attribute arch, "rv32izbc1p0"
 # CHECK: attribute  5, "rv32i2p1_zbc1p0"
 
-.attribute arch, "rv32i_zve64x_zvbb0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvbb1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvbc0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvbc1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvkg0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvkg1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve64x_zvkn0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvkn1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvknc0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvknc1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvkng0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvkng1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvknha0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvknha1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve64x_zvknhb0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvknhb1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvkned0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvkned1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve64x_zvks0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvks1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvksc0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvksc1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvksg0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvksg1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p

[PATCH] D153836: [RISCV] Bump vector crypto to v1.0.0-rc1

2023-06-28 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

In D153836#4452236 , @asb wrote:

> Agreed that looking at 
> https://github.com/riscv/riscv-crypto/compare/v20230531...v20230620 there are 
> no changes that need to be reflected on the LLVM side beyond the version bump 
> here. LGTM

Thanks for reviewing!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153836/new/

https://reviews.llvm.org/D153836

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[PATCH] D153836: [RISCV] Bump vector crypto to v1.0.0-rc1

2023-06-28 Thread Brandon Wu via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG02f94a655fb6: [RISCV] Bump vector crypto to v1.0.0-rc1 
(authored by 4vtomat).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153836/new/

https://reviews.llvm.org/D153836

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s

Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -111,50 +111,50 @@
 .attribute arch, "rv32izbc1p0"
 # CHECK: attribute  5, "rv32i2p1_zbc1p0"
 
-.attribute arch, "rv32i_zve64x_zvbb0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvbb1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvbc0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbc0p9_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvbc1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvkg0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvkg1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve64x_zvkn0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvkn1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvknc0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvkn0p9_zvknc0p9_zvkned0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvknc1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvkng0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvkn0p9_zvkned0p9_zvkng0p9_zvknha0p9_zvknhb0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvkng1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvknha0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvknha1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve64x_zvknhb0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha0p9_zvknhb0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvknhb1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvkned0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvkned1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0"
 
-.attribute arch, "rv32i_zve64x_zvks0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvks1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvksc0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zvbc0p9_zve32x1p0_zve64x1p0_zvks0p9_zvksc0p9_zvksed0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvksc1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zvbc1p0_zve32x1p0_zve64x1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve64x_zvksg0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb0p9_zve32x1p0_zve64x1p0_zvkg0p9_zvks0p9_zvksed0p9_zvksg0p9_zvksh0p9_zvkt0p9_zvl32b1p0_zvl64b1p0"
+.attribute arch, "rv32i_zve64x_zvksg1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zve64x1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0"
 
-.attribute arch, "rv32i_zve32x_zvksed0p9"
-# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed0p9_zvl32b1p0"
+.attribute arch, "rv32i_zve32x_zvksed1p0"
+# CHECK: attribute  5, "rv32i2p1_zicsr2p0_zve32x1p0_zv

[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

2023-06-29 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 535696.
4vtomat added a comment.
Herald added a subscriber: wangpc.

Ready for review


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138810/new/

https://reviews.llvm.org/D138810

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3c.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm3me.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4k.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vwsll.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf1.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaeskf2.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vandn.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vbrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclmulh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vclz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vcpopv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vctz.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vghsh.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vgmul.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrev8.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vrol.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vror.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ch.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2cl.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsha2ms.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm3c.c
  
clang/test/C

[PATCH] D154050: [Clang][RISCV] Fix RISC-V vector / SiFive intrinsic inclusion in SemaLookup

2023-06-29 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat accepted this revision.
4vtomat added a comment.

LGTM, thanks~


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D154050/new/

https://reviews.llvm.org/D154050

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[PATCH] D147935: [RISCV] Add SiFive extension support

2023-04-10 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, 
zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, 
rbar, asb, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Add SiFive extension support
Depends on D147934 


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147935

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("FullMultiply", RVV_REQ_FullMultiply)
+  .Case("Xsfvcp", RVV_REQ_xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
   SR.RequiredExtensions |= RequireExt;
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -462,8 +462,9 @@
   RVV_REQ_None = 0,
   RVV_REQ_RV64 = 1 << 0,
   RVV_REQ_FullMultiply = 1 << 1,
+  RVV_REQ_xsfvcp = 1 << 2,
 
-  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_FullMultiply)
+  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_xsfvcp)
 };
 
 // Raw RVV intrinsic info, used to expand later.


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("FullMultiply", RVV_REQ_FullMultiply)
+  .Case("Xsfvcp", RVV_REQ_xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
   SR.RequiredExtensions |= RequireExt;
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -462,8 +462,9 @@
   RVV_REQ_None = 0,
   RVV_REQ_RV64 = 1 << 0,
   RVV_REQ_FullMultiply = 1 << 1,
+  RVV_REQ_xsfvcp = 1 << 2,
 
-  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_FullMultiply)
+  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_xsfvcp)
 };
 
 // Raw RVV intrinsic info, used to expand later.
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[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

2023-04-11 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
jdoerfert, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb, hiraditya, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

This patch implements 1.0-RC3:
https://github.com/riscv/riscv-aia/releases/download/1.0-RC3/riscv-interrupts-1.0-RC3.pdf


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148066

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/hypervisor-csr-names.s
  llvm/test/MC/RISCV/machine-csr-names.s
  llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
  llvm/test/MC/RISCV/rv32-machine-csr-names.s
  llvm/test/MC/RISCV/rv32-only-csr-names.s
  llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
  llvm/test/MC/RISCV/rvi-aliases-valid.s
  llvm/test/MC/RISCV/supervisor-csr-names.s

Index: llvm/test/MC/RISCV/supervisor-csr-names.s
===
--- llvm/test/MC/RISCV/supervisor-csr-names.s
+++ llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -319,3 +319,63 @@
 csrrs t1, sstateen3, zero
 # uimm12
 csrrs t2, 0x10F, zero
+
+#
+# Advanced Interrupt Architecture (Smaia and Ssaia)
+#
+
+# siselect
+# name
+# CHECK-INST: csrrs t1, siselect, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x15]
+# CHECK-INST-ALIAS: csrr t1, siselect
+# uimm12
+# CHECK-INST: csrrs t2, siselect, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x15]
+# CHECK-INST-ALIAS: csrr t2, siselect
+# name
+csrrs t1, siselect, zero
+# uimm12
+csrrs t2, 0x150, zero
+
+# sireg
+# name
+# CHECK-INST: csrrs t1, sireg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x15]
+# CHECK-INST-ALIAS: csrr t1, sireg
+# uimm12
+# CHECK-INST: csrrs t2, sireg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x15]
+# CHECK-INST-ALIAS: csrr t2, sireg
+# name
+csrrs t1, sireg, zero
+# uimm12
+csrrs t2, 0x151, zero
+
+# stopei
+# name
+# CHECK-INST: csrrs t1, stopei, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x15]
+# CHECK-INST-ALIAS: csrr t1, stopei
+# uimm12
+# CHECK-INST: csrrs t2, stopei, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x15]
+# CHECK-INST-ALIAS: csrr t2, stopei
+# name
+csrrs t1, stopei, zero
+# uimm12
+csrrs t2, 0x15C, zero
+
+# stopi
+# name
+# CHECK-INST: csrrs t1, stopi, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xdb]
+# CHECK-INST-ALIAS: csrr t1, stopi
+# uimm12
+# CHECK-INST: csrrs t2, stopi, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xdb]
+# CHECK-INST-ALIAS: csrr t2, stopi
+# name
+csrrs t1, stopi, zero
+# uimm12
+csrrs t2, 0xDB0, zero
Index: llvm/test/MC/RISCV/rvi-aliases-valid.s
===
--- llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -207,8 +207,8 @@
 # CHECK-S-OBJ: rdtime s9
 rdtime x25
 
-# CHECK-S-OBJ-NOALIAS: csrrs  s0, 336, zero
-# CHECK-S-OBJ: csrr s0, 336
+# CHECK-S-OBJ-NOALIAS: csrrs s0, siselect, zero
+# CHECK-S-OBJ: csrr s0, siselect
 csrr x8, 0x150
 # CHECK-S-OBJ-NOALIAS: csrrw zero, sscratch, s1
 # CHECK-S-OBJ: csrw sscratch, s1
@@ -220,8 +220,8 @@
 # CHECK-S-OBJ: csrc 4095, s7
 csrc 0xfff, x23
 
-# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 15
-# CHECK-S-OBJ: csrwi 336, 15
+# CHECK-S-OBJ-NOALIAS: csrrwi zero, siselect, 15
+# CHECK-S-OBJ: csrwi siselect, 15
 csrwi 0x150, 0xf
 # CHECK-S-OBJ-NOALIAS: csrrsi zero, 4095, 16
 # CHECK-S-OBJ: csrsi 4095, 16
@@ -230,18 +230,18 @@
 # CHECK-S-OBJ: csrci sscratch, 17
 csrci 0x140, 0x11
 
-# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 7
-# CHECK-S-OBJ: csrwi 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrwi zero, siselect, 7
+# CHECK-S-OBJ: csrwi siselect, 7
 csrw 0x150, 7
-# CHECK-S-OBJ-NOALIAS: csrrsi zero, 336, 7
-# CHECK-S-OBJ: csrsi 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrsi zero, siselect, 7
+# CHECK-S-OBJ: csrsi siselect, 7
 csrs 0x150, 7
-# CHECK-S-OBJ-NOALIAS: csrrci zero, 336, 7
-# CHECK-S-OBJ: csrci 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrci zero, siselect, 7
+# CHECK-S-OBJ: csrci siselect, 7
 csrc 0x150, 7
 
-# CHECK-S-OBJ-NOALIAS: csrrwi t0, 336, 15
-# CHECK-S-OBJ: csrrwi t0, 336, 15
+# CHECK-S-OBJ-NOALIAS: csrrwi t0, siselect, 15
+# CHECK-S-OBJ: csrrwi t0, siselect, 15
 csrrw t0, 0x150, 0xf
 # CHECK-S-OBJ-NOALIAS: csrrsi t0, 4095, 16
 # CHECK-S-OBJ: csrrsi t0, 4095, 16
Index: llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
===
--- llv

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

2023-04-11 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 512655.
4vtomat added a comment.

Resolved Kito's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148066/new/

https://reviews.llvm.org/D148066

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/hypervisor-csr-names.s
  llvm/test/MC/RISCV/machine-csr-names.s
  llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
  llvm/test/MC/RISCV/rv32-machine-csr-names.s
  llvm/test/MC/RISCV/rv32-only-csr-names.s
  llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
  llvm/test/MC/RISCV/rvi-aliases-valid.s
  llvm/test/MC/RISCV/supervisor-csr-names.s

Index: llvm/test/MC/RISCV/supervisor-csr-names.s
===
--- llvm/test/MC/RISCV/supervisor-csr-names.s
+++ llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -319,3 +319,63 @@
 csrrs t1, sstateen3, zero
 # uimm12
 csrrs t2, 0x10F, zero
+
+#
+# Advanced Interrupt Architecture (Smaia and Ssaia)
+#
+
+# siselect
+# name
+# CHECK-INST: csrrs t1, siselect, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0x15]
+# CHECK-INST-ALIAS: csrr t1, siselect
+# uimm12
+# CHECK-INST: csrrs t2, siselect, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x15]
+# CHECK-INST-ALIAS: csrr t2, siselect
+# name
+csrrs t1, siselect, zero
+# uimm12
+csrrs t2, 0x150, zero
+
+# sireg
+# name
+# CHECK-INST: csrrs t1, sireg, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x10,0x15]
+# CHECK-INST-ALIAS: csrr t1, sireg
+# uimm12
+# CHECK-INST: csrrs t2, sireg, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x15]
+# CHECK-INST-ALIAS: csrr t2, sireg
+# name
+csrrs t1, sireg, zero
+# uimm12
+csrrs t2, 0x151, zero
+
+# stopei
+# name
+# CHECK-INST: csrrs t1, stopei, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x15]
+# CHECK-INST-ALIAS: csrr t1, stopei
+# uimm12
+# CHECK-INST: csrrs t2, stopei, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x15]
+# CHECK-INST-ALIAS: csrr t2, stopei
+# name
+csrrs t1, stopei, zero
+# uimm12
+csrrs t2, 0x15C, zero
+
+# stopi
+# name
+# CHECK-INST: csrrs t1, stopi, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x00,0xdb]
+# CHECK-INST-ALIAS: csrr t1, stopi
+# uimm12
+# CHECK-INST: csrrs t2, stopi, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0x00,0xdb]
+# CHECK-INST-ALIAS: csrr t2, stopi
+# name
+csrrs t1, stopi, zero
+# uimm12
+csrrs t2, 0xDB0, zero
Index: llvm/test/MC/RISCV/rvi-aliases-valid.s
===
--- llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -207,8 +207,8 @@
 # CHECK-S-OBJ: rdtime s9
 rdtime x25
 
-# CHECK-S-OBJ-NOALIAS: csrrs  s0, 336, zero
-# CHECK-S-OBJ: csrr s0, 336
+# CHECK-S-OBJ-NOALIAS: csrrs s0, siselect, zero
+# CHECK-S-OBJ: csrr s0, siselect
 csrr x8, 0x150
 # CHECK-S-OBJ-NOALIAS: csrrw zero, sscratch, s1
 # CHECK-S-OBJ: csrw sscratch, s1
@@ -220,8 +220,8 @@
 # CHECK-S-OBJ: csrc 4095, s7
 csrc 0xfff, x23
 
-# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 15
-# CHECK-S-OBJ: csrwi 336, 15
+# CHECK-S-OBJ-NOALIAS: csrrwi zero, siselect, 15
+# CHECK-S-OBJ: csrwi siselect, 15
 csrwi 0x150, 0xf
 # CHECK-S-OBJ-NOALIAS: csrrsi zero, 4095, 16
 # CHECK-S-OBJ: csrsi 4095, 16
@@ -230,18 +230,18 @@
 # CHECK-S-OBJ: csrci sscratch, 17
 csrci 0x140, 0x11
 
-# CHECK-S-OBJ-NOALIAS: csrrwi zero, 336, 7
-# CHECK-S-OBJ: csrwi 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrwi zero, siselect, 7
+# CHECK-S-OBJ: csrwi siselect, 7
 csrw 0x150, 7
-# CHECK-S-OBJ-NOALIAS: csrrsi zero, 336, 7
-# CHECK-S-OBJ: csrsi 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrsi zero, siselect, 7
+# CHECK-S-OBJ: csrsi siselect, 7
 csrs 0x150, 7
-# CHECK-S-OBJ-NOALIAS: csrrci zero, 336, 7
-# CHECK-S-OBJ: csrci 336, 7
+# CHECK-S-OBJ-NOALIAS: csrrci zero, siselect, 7
+# CHECK-S-OBJ: csrci siselect, 7
 csrc 0x150, 7
 
-# CHECK-S-OBJ-NOALIAS: csrrwi t0, 336, 15
-# CHECK-S-OBJ: csrrwi t0, 336, 15
+# CHECK-S-OBJ-NOALIAS: csrrwi t0, siselect, 15
+# CHECK-S-OBJ: csrrwi t0, siselect, 15
 csrrw t0, 0x150, 0xf
 # CHECK-S-OBJ-NOALIAS: csrrsi t0, 4095, 16
 # CHECK-S-OBJ: csrrsi t0, 4095, 16
Index: llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
===
--- llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
+++ llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
@@ -21,3 +21,35 @@
 csrrs t1, stimecmph, zero
 # uimm12
 csrrs t2, 0x15D, zero
+
+#
+# Advanced Interrupt Architecture (Smaia and Ssaia)
+#
+
+# sieh
+# name
+# CHECK-INST: csrrs t1, sieh, zero
+# CHECK-ENC: encoding: [0x73,0x23,0x40,0x11]
+# CHECK-INST-ALIAS: csrr t1, sieh
+# uimm12
+# CHECK-INST: csrrs t2, sieh, zero
+# CHECK-EN

[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

2023-04-13 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: luke, frasercrmck, luismarques, apazos, 
sameer.abuasal, s.egerton, Jim, jocewei, PkmX, the_o, brucehoult, 
MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, MaskRay.
Herald added a project: clang.

Depends on D147934  and D147935 



Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D148223

Files:
  clang/include/clang/Basic/riscv_vector.td
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c

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[PATCH] D147935: [RISCV] Add SiFive extension support

2023-04-13 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat added a comment.

In D147935#4259687 , @craig.topper 
wrote:

> Is there a different patch with the .td for these intrinsics?

Yes, it's in this patch: D148223 




Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:465
   RVV_REQ_FullMultiply = 1 << 1,
+  RVV_REQ_xsfvcp = 1 << 2,
 

asb wrote:
> Nit: It would better match the surrounding capitalisation to call this 
> RVV_REQ_Xsfvcp
Got it! Thanks!


Repository:
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https://reviews.llvm.org/D147935

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[PATCH] D147935: [RISCV] Add SiFive extension support

2023-04-13 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 513223.
4vtomat added a comment.

Resolved Alex's comment.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147935/new/

https://reviews.llvm.org/D147935

Files:
  clang/include/clang/Support/RISCVVIntrinsicUtils.h
  clang/utils/TableGen/RISCVVEmitter.cpp


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("FullMultiply", RVV_REQ_FullMultiply)
+  .Case("Xsfvcp", RVV_REQ_Xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
   SR.RequiredExtensions |= RequireExt;
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -462,8 +462,9 @@
   RVV_REQ_None = 0,
   RVV_REQ_RV64 = 1 << 0,
   RVV_REQ_FullMultiply = 1 << 1,
+  RVV_REQ_Xsfvcp = 1 << 2,
 
-  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_FullMultiply)
+  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp)
 };
 
 // Raw RVV intrinsic info, used to expand later.


Index: clang/utils/TableGen/RISCVVEmitter.cpp
===
--- clang/utils/TableGen/RISCVVEmitter.cpp
+++ clang/utils/TableGen/RISCVVEmitter.cpp
@@ -633,6 +633,7 @@
   RVVRequire RequireExt = StringSwitch(RequiredFeature)
   .Case("RV64", RVV_REQ_RV64)
   .Case("FullMultiply", RVV_REQ_FullMultiply)
+  .Case("Xsfvcp", RVV_REQ_Xsfvcp)
   .Default(RVV_REQ_None);
   assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?");
   SR.RequiredExtensions |= RequireExt;
Index: clang/include/clang/Support/RISCVVIntrinsicUtils.h
===
--- clang/include/clang/Support/RISCVVIntrinsicUtils.h
+++ clang/include/clang/Support/RISCVVIntrinsicUtils.h
@@ -462,8 +462,9 @@
   RVV_REQ_None = 0,
   RVV_REQ_RV64 = 1 << 0,
   RVV_REQ_FullMultiply = 1 << 1,
+  RVV_REQ_Xsfvcp = 1 << 2,
 
-  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_FullMultiply)
+  LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Xsfvcp)
 };
 
 // Raw RVV intrinsic info, used to expand later.
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[PATCH] D148223: [SiFive] Support C intrinsics for xsfvcp extension.

2023-04-14 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat updated this revision to Diff 513464.
4vtomat added a comment.
Herald added a subscriber: arphaman.

Resolved Craig's comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D148223/new/

https://reviews.llvm.org/D148223

Files:
  clang/include/clang/Basic/riscv_vector.td
  clang/lib/Sema/SemaChecking.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c

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[PATCH] D148308: [RISCV] Split out SiFive VCIX C intrinsics from riscv_vector.td

2023-04-14 Thread Brandon Wu via Phabricator via cfe-commits

4vtomat created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, 
jocewei, PkmX, arphaman, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, 
simoncook, johnrusso, rbar, asb, arichardson.
Herald added a project: All.
4vtomat requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

Since we don't always need the vendor extension to be in riscv_vector.td,
so it's better to make it be in separated header.

Depends on D148223 


Repository:
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https://reviews.llvm.org/D148308

Files:
  clang/include/clang/Basic/BuiltinsRISCVVector.def
  clang/include/clang/Basic/CMakeLists.txt
  clang/include/clang/Basic/riscv_sifive_vcix.td
  clang/include/clang/Basic/riscv_vector.td
  clang/include/clang/Basic/riscv_vector_common.td
  clang/include/clang/Sema/RISCVIntrinsicManager.h
  clang/include/clang/Sema/Sema.h
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/Headers/CMakeLists.txt
  clang/lib/Headers/sifive_vector.h
  clang/lib/Parse/ParsePragma.cpp
  clang/lib/Sema/SemaLookup.cpp
  clang/lib/Sema/SemaRISCVVectorLookup.cpp
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c
  
clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c
  clang/test/Sema/riscv-bad-intrinsic-pragma.c
  clang/utils/TableGen/TableGen.cpp
  llvm/docs/CommandGuide/tblgen.rst

Index: llvm/docs/CommandGuide/tblgen.rst
===
--- llvm/docs/CommandGuide/tblgen.rst
+++ llvm/docs/CommandGuide/tblgen.rst
@@ -348,6 +348,14 @@
 
   Generate ``riscv_vector_builtin_cg.inc`` for Clang.
 
+.. option:: -gen-riscv-sifive-vcix-builtins
+
+  Generate ``riscv_sifive_vcix_builtins.inc`` for Clang.
+
+.. option:: -gen-riscv-sifive-vcix-builtin-codegen
+
+  Generate ``riscv_sifive_vcix_builtin_cg.inc`` for Clang.
+
 .. option:: -gen-attr-docs
 
   Generate attribute documentation.
Index: clang/utils/TableGen/TableGen.cpp
===
--- clang/utils/TableGen/TableGen.cpp
+++ clang/utils/TableGen/TableGen.cpp
@@ -91,6 +91,9 @@
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
   GenRISCVVectorBuiltinSema,
+  GenRISCVSiFiveVCIXBuiltins,
+  GenRISCVSiFiveVCIXBuiltinCG,
+  GenRISCVSiFiveVCIXBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
@@ -251,6 +254,12 @@
"Generate riscv_vector_builtin_cg.inc for clang"),
 clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
"Generate riscv_vector_builtin_sema.inc for clang"),
+clEnumValN(GenRISCVSiFiveVCIXBuiltins, "gen-riscv-sifive-vcix-builtins",
+   "Generate riscv_sifive_vcix_builtins.inc for clang"),
+clEnumValN(GenRISCVSiFiveVCIXBuiltinCG, "gen-riscv-sifive-vcix-builtin-codegen",
+   "Generate riscv_sifive_vcix_builtin_cg.inc for clang"),
+clEnumValN(GenRISCVSiFiveVCIXBuiltinSema, "gen-riscv-sifive-vcix-builtin-sema",
+   "Generate riscv_sifive_vcix_builtin_sema.inc for clang"),
 clEnumValN(GenAttrDocs, "gen-attr-docs",
"Generate attribute documentation"),
 clEnumValN(GenDiagDocs, "gen-diag-docs",
@@ -472,6 +481,15 @@
   case GenRISCVVectorBuiltinSema:
 EmitRVVBuiltinSema(Records, OS);
 break;
+  case GenRISCVSiFiveVCIXBuiltins:
+EmitRVVBuiltins(Records, OS);
+break;
+  case GenRISCVSiFiveVCIXBuiltinCG:
+EmitRVVBuiltinCG(Records, OS);
+break;
+  case GenRISCVSiFiveVCIXBuiltinSema:
+EmitRVVBuiltinSema(Records, OS);
+break;
   case GenAttrDocs:
 EmitClangAttrDocs(Records, OS);
 break;
Index: clang/test/Sema/riscv-bad-intrinsic-pragma.c
===
--- clang/test/Sema/riscv-bad-intrinsic-pragma.c
+++ clang/test/Sema/riscv-bad-intrinsic-pragma.c
@@ -2,7 +2,7 @@
 // RUN:2>&1 | FileCheck %s
 
 #pragma clang riscv intrinsic 
-// CHECK:  warning: unexpected argument '' to '#pragma riscv'; expected 'vector' [-Wignored-pragmas]
+// CHECK:  wa

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