[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-17 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added a comment.

In D153008#4430491 , @MaskRay wrote:

> In D153008#4428694 , @abel-bernabeu 
> wrote:
>
>> In D153008#4428568 , @MaskRay 
>> wrote:
>>
>>> This new update still applies many unneeded `getParser().Lex();` and adds a 
>>> test at a wrong layer 
>>> 
>>>  (clang/test/CodeGen):
>>
>> Would you rather have:
>>
>> - LLVM IR as input
>> - assembly as output
>> - the test placed under llvm/test/CodeGen/RISCV/
>>
>> ?
>>
>> That would make the test more verbose, but it would reduce the testing 
>> scope. Please confirm your preference.
>
> I created D153204  as an alternative. 
> Thanks for reporting the issue!

Thanks for reviewing. Added my comments on your patch proposal.


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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-18 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532488.
abel-bernabeu added a comment.

Updated commit message:

- fixed a typo
- added a co-author


Repository:
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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/CodeGen/RISCV/inline-asm-gcc-comments.ll

Index: llvm/test/CodeGen/RISCV/inline-asm-gcc-comments.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/inline-asm-gcc-comments.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IF %s
+
+define i64 @f() #0 {
+; RV32IF-LABEL:   f:
+; RV32IF: li a0, 0 # this is fine # this is also fine # and last but not least
+;
+; RV64IF-LABEL:   f:
+; RV64IF: li a0, 0 # this is fine # this is also fine # and last but not least
+  %1 = alloca i64, align 8
+  %2 = call i64 asm "li /* this is fine */ $0 , /* this is also fine */ 0 /* and last but not least */\0A", "=r"()
+  store i64 %2, ptr %1, align 8
+  %3 = load i64, ptr %1, align 8
+  ret i64 %3
+}
\ No newline at end of file
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2410,12 +2410,12 @@
   Error(getLoc(), "continuous register list must start from 's0' or 'x8'");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex(); // eat reg
+getParser().Lex(); // eat reg
   }
 
   // parse case like -s1
   if (getLexer().is(AsmToken::Minus)) {
-getLexer().Lex();
+getParser().Lex();
 StringRef EndName = getLexer().getTok().getIdentifier();
 // FIXME: the register mapping and checks of EABI is wrong
 RegEnd = matchRegisterNameHelper(IsEABI, EndName);
@@ -2428,7 +2428,7 @@
   "'x8-x9' pair");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (!IsEABI) {
@@ -2442,7 +2442,7 @@
   }
 
   // parse ', x18' for extra part
-  getLexer().Lex();
+  getParser().Lex();
   if (getLexer().isNot(AsmToken::Identifier)) {
 Error(getLoc(), "invalid register");
 return MatchOperand_ParseFail;
@@ -2453,11 +2453,11 @@
 "must start from 'x18'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse '-x20' for extra part
   if (getLexer().is(AsmToken

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-18 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532489.
abel-bernabeu added a comment.

Fixed a typo on commit message


Repository:
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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/CodeGen/RISCV/inline-asm-gcc-comments.ll

Index: llvm/test/CodeGen/RISCV/inline-asm-gcc-comments.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/inline-asm-gcc-comments.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IF %s
+
+define i64 @f() #0 {
+; RV32IF-LABEL:   f:
+; RV32IF: li a0, 0 # this is fine # this is also fine # and last but not least
+;
+; RV64IF-LABEL:   f:
+; RV64IF: li a0, 0 # this is fine # this is also fine # and last but not least
+  %1 = alloca i64, align 8
+  %2 = call i64 asm "li /* this is fine */ $0 , /* this is also fine */ 0 /* and last but not least */\0A", "=r"()
+  store i64 %2, ptr %1, align 8
+  %3 = load i64, ptr %1, align 8
+  ret i64 %3
+}
\ No newline at end of file
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2410,12 +2410,12 @@
   Error(getLoc(), "continuous register list must start from 's0' or 'x8'");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex(); // eat reg
+getParser().Lex(); // eat reg
   }
 
   // parse case like -s1
   if (getLexer().is(AsmToken::Minus)) {
-getLexer().Lex();
+getParser().Lex();
 StringRef EndName = getLexer().getTok().getIdentifier();
 // FIXME: the register mapping and checks of EABI is wrong
 RegEnd = matchRegisterNameHelper(IsEABI, EndName);
@@ -2428,7 +2428,7 @@
   "'x8-x9' pair");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (!IsEABI) {
@@ -2442,7 +2442,7 @@
   }
 
   // parse ', x18' for extra part
-  getLexer().Lex();
+  getParser().Lex();
   if (getLexer().isNot(AsmToken::Identifier)) {
 Error(getLoc(), "invalid register");
 return MatchOperand_ParseFail;
@@ -2453,11 +2453,11 @@
 "must start from 'x18'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse '-x20' for extra part
   if (getLexer().is(AsmToken::Minus)) {
-getLexer

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-19 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532686.
abel-bernabeu added a comment.

Rebased on top of the latest changes in RISCVAsmParser.cpp

Moved the testing to llc-mc test cases under lvm/test/MC/RISCV/

Covered with tests for every single case where the parser consumes a
token and a potential comment needs to be handled. Having manually
verified that the testing coverage is complete.

Reworked the code using getLexer().peekTokens for ignoring comments.

If a comment is not handled proper, now is a bug, because the feature
is complete and the testing has full coverage.


Repository:
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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/comments-zdinx.ll
  llvm/test/MC/RISCV/comments.ll

Index: llvm/test/MC/RISCV/comments.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments.ll
@@ -0,0 +1,70 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments \
+# RUN:--mattr=+v,+experimental-zfa,+experimental-zcmp,+experimental-ztso %s \
+# RUN:| FileCheck %s
+
+/*c0*/ li /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: li  a0, 0   # c0# c1# c2# c3
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ ( /*c4*/ a1 /*c5*/ ) /*c6*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ nan /*c4*/
+# CHECK: fli.s   ft0, nan#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ 1.0 /*c4*/
+# CHECK: fli.s   ft0, 1.0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ auipc /*c1*/ a0 /*c2*/ , /*c3*/ %pcrel_hi /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK:  auipc   a0, %pcrel_hi(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ + /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi0:#c0 #c1 #c2 #c3 #c4 #c5 #c6
+# CHECK: auipc   s0, %pcrel_hi(symbol+10)
+# CHECK: addis0, s0, %pcrel_lo(.Lpcrel_hi0)
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ - /*c5*/ 10
+# CHECK: .Lpcrel_hi1:#c0 #c1 #c2 #c3 #c4 #c5
+# CHECK: auipc   s0, %pcrel_hi(symbol-10)
+# CHECK: addis0, s0, %pcrel_lo(.Lpcrel_hi1)
+
+/*c0*/ vsetivli /*c1*/ a2 /*c2*/ , /*c3*/ 31 /*c4*/ , /*c5*/ e32 /*c6*/ , /*c7*/ m1 /*c8*/ , /*c9*/ ta /*c10*/ , /*c11*/ ma /*c12*/
+# CHECK: vsetivlia2, 31, e32, m1, ta, ma #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12
+
+/*c0*/ vadd.vv /*c1*/ v1 /*c2*/ , /*c3*/ v2 /*c4*/ , /*c5*/ v3 /*c6*/ , /*c7*/ v0.t /*c8*/
+# CHECK: vadd.vv v1, v2, v3, v0.t#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8
+
+/*c0*/ cm.push /*c1*/ { /*c2*/ ra /*c3*/ , /*c4*/ s0 /*c5*/ - /*c6*/ s1 /*c7*/ } /*c8*/ , /*c9*/ - /*c10*/ 32 /*c11*/
+# CHECK: cm.push {ra, s0-s1}, -32#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11
+
+/*c0*/ cm.popret /*c0*/ { /*c1*/ x1 /*c2*/ , /*c3*/ x8 /*c4*/ - /*c5*/ x9 /*c6*/ , /*c7*/ x18 /*c8*/ - /*c9*/ x20 /*c10*/ } /*c11*/ , /*c12*/ 64 /*c13*/
+# CHECK: cm.popret   {ra, s0-s4}, 64 #c0 #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12#c13
+
+/*c0*/ fence /*c1*/ 0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: fence   0, 0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence /*c1*/ iorw /*c2*/ , /*c3*/ iorw /*c4*/
+# CHECK: fence   #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence.tso /*c1*/
+# CHECK: fence.tso   #c0 #c1
+
+/*c0*/ fence.i /*c1*/
+# CHECK: fence.i #c0 #c1
+
+/*c0*/ nop /*c1*/
+# CHECK: nop #c0 #c1
+
+/*c0*/ .option /*c1*/ arch /*c2*/ , /*c3*/ rv64gc /*c4*/
+# CHECK: #c0 #c1 #c2 #c3 #c4
+# CHECK-NEXT: .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0
+
+/*c0*/ .attribute /*c1*/ priv_spec /*c2*/ , /*c3*/ 2 /*c4*/
+# CHECK: .attribute  8, 2
+# CHECK-NEXT: #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ .attribute /*c1*/ arch /*c2*/ , /*c3*/ "rv32i_zvfbfmin0p6" /*c4*/
+# CHECK: .attribute  5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
+# CHECK-NEXT: #c0 #c1 #c2 #c3 #c4
\ No newline at end of file
Index: llvm/test/MC/RISCV/comments-zdinx.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments-zdinx.ll
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments --mattr=+zdinx  %s | FileCheck %s
+
+/*c0*/ fmadd.d /*c1*/ x10 /*c2*/ , /*c3*/ x12 /*c4*/ , /*c5*/ x14 /*c6*/ , /*c7*/ x16 /*c8*/ , /*c9*/ dyn /*c10*/
+// CHECK: fmadd.d a0, a2, a4, a6

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-19 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added inline comments.



Comment at: llvm/test/MC/RISCV/comments.ll:25
+# CHECK: .Lpcrel_hi0:#c0 #c1 #c2 #c3 #c4 #c5 #c6
+# CHECK: auipc   s0, %pcrel_hi(symbol+10)
+# CHECK: addis0, s0, %pcrel_lo(.Lpcrel_hi0)

This should be CHECK-NEXT rather than CHECK. Will update again tonight.


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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-19 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532753.
abel-bernabeu added a comment.

Added --match-fulllines to FileCheck for making the check stricter.


Repository:
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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/comments-zdinx.ll
  llvm/test/MC/RISCV/comments.ll

Index: llvm/test/MC/RISCV/comments.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments.ll
@@ -0,0 +1,68 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments \
+# RUN:--mattr=+v,+experimental-zfa,+experimental-zcmp,+experimental-ztso %s \
+# RUN:| FileCheck %s  --match-full-lines
+
+/*c0*/ li /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: li	a0, 0	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ ( /*c4*/ a1 /*c5*/ ) /*c6*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ nan /*c4*/
+# CHECK: fli.s	ft0, nan	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ 1.0 /*c4*/
+# CHECK: fli.s	ft0, 1.0	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ auipc /*c1*/ a0 /*c2*/ , /*c3*/ %pcrel_hi /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK:  auipc   a0, %pcrel_hi(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ + /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi0:#c0 #c1 #c2 #c3 #c4 #c5 #c6
+# CHECK-NEXT: auipc   s0, %pcrel_hi(symbol+10)
+# CHECK-NEXT: addis0, s0, %pcrel_lo(.Lpcrel_hi0)
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ - /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi1:#c0 #c1 #c2 #c3 #c4 #c5	#c6
+# CHECK-NEXT: auipc   s0, %pcrel_hi(symbol-10)
+# CHECK-NEXT: addis0, s0, %pcrel_lo(.Lpcrel_hi1)
+
+/*c0*/ vsetivli /*c1*/ a2 /*c2*/ , /*c3*/ 31 /*c4*/ , /*c5*/ e32 /*c6*/ , /*c7*/ m1 /*c8*/ , /*c9*/ ta /*c10*/ , /*c11*/ ma /*c12*/
+# CHECK: vsetivlia2, 31, e32, m1, ta, ma #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12
+
+/*c0*/ vadd.vv /*c1*/ v1 /*c2*/ , /*c3*/ v2 /*c4*/ , /*c5*/ v3 /*c6*/ , /*c7*/ v0.t /*c8*/
+# CHECK: vadd.vv v1, v2, v3, v0.t#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8
+
+/*c0*/ cm.push /*c1*/ { /*c2*/ ra /*c3*/ , /*c4*/ s0 /*c5*/ - /*c6*/ s1 /*c7*/ } /*c8*/ , /*c9*/ - /*c10*/ 32 /*c11*/
+# CHECK: cm.push {ra, s0-s1}, -32#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11
+
+/*c0*/ cm.popret /*c0*/ { /*c1*/ x1 /*c2*/ , /*c3*/ x8 /*c4*/ - /*c5*/ x9 /*c6*/ , /*c7*/ x18 /*c8*/ - /*c9*/ x20 /*c10*/ } /*c11*/ , /*c12*/ 64 /*c13*/
+# CHECK: cm.popret   {ra, s0-s4}, 64 #c0 #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12#c13
+
+/*c0*/ fence /*c1*/ 0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: fence   0, 0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence /*c1*/ iorw /*c2*/ , /*c3*/ iorw /*c4*/
+# CHECK: fence   #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence.tso /*c1*/
+# CHECK: fence.tso   #c0 #c1
+
+/*c0*/ fence.i /*c1*/
+# CHECK: fence.i #c0 #c1
+
+/*c0*/ nop /*c1*/
+# CHECK: nop	#c0	#c1
+
+/*c0*/ .option /*c1*/ arch /*c2*/ , /*c3*/ rv64gc /*c4*/
+
+# CHECK: .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0
+
+/*c0*/ .attribute /*c1*/ priv_spec /*c2*/ , /*c3*/ 2 /*c4*/
+# CHECK: .attribute  8, 2
+
+/*c0*/ .attribute /*c1*/ arch /*c2*/ , /*c3*/ "rv32i_zvfbfmin0p6" /*c4*/
+# CHECK: .attribute  5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
Index: llvm/test/MC/RISCV/comments-zdinx.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments-zdinx.ll
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments --mattr=+zdinx  %s | FileCheck %s --match-full-lines
+
+/*c0*/ fmadd.d /*c1*/ x10 /*c2*/ , /*c3*/ x12 /*c4*/ , /*c5*/ x14 /*c6*/ , /*c7*/ x16 /*c8*/ , /*c9*/ dyn /*c10*/
+// CHECK: fmadd.d a0, a2, a4, a6  #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -107,6 +107,8 @@
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
 
+  AsmToken peekNextNext();
+
   bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
  SMLoc &EndLoc) override;
   OperandMat

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-19 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532754.
abel-bernabeu added a comment.

Removed a gratuitous blank line


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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/comments-zdinx.ll
  llvm/test/MC/RISCV/comments.ll

Index: llvm/test/MC/RISCV/comments.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments.ll
@@ -0,0 +1,67 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments \
+# RUN:--mattr=+v,+experimental-zfa,+experimental-zcmp,+experimental-ztso %s \
+# RUN:| FileCheck %s  --match-full-lines
+
+/*c0*/ li /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: li	a0, 0	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ ( /*c4*/ a1 /*c5*/ ) /*c6*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ nan /*c4*/
+# CHECK: fli.s	ft0, nan	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ 1.0 /*c4*/
+# CHECK: fli.s	ft0, 1.0	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ auipc /*c1*/ a0 /*c2*/ , /*c3*/ %pcrel_hi /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK:  auipc   a0, %pcrel_hi(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ + /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi0:#c0 #c1 #c2 #c3 #c4 #c5 #c6
+# CHECK-NEXT: auipc   s0, %pcrel_hi(symbol+10)
+# CHECK-NEXT: addis0, s0, %pcrel_lo(.Lpcrel_hi0)
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ - /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi1:#c0 #c1 #c2 #c3 #c4 #c5	#c6
+# CHECK-NEXT: auipc   s0, %pcrel_hi(symbol-10)
+# CHECK-NEXT: addis0, s0, %pcrel_lo(.Lpcrel_hi1)
+
+/*c0*/ vsetivli /*c1*/ a2 /*c2*/ , /*c3*/ 31 /*c4*/ , /*c5*/ e32 /*c6*/ , /*c7*/ m1 /*c8*/ , /*c9*/ ta /*c10*/ , /*c11*/ ma /*c12*/
+# CHECK: vsetivlia2, 31, e32, m1, ta, ma #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12
+
+/*c0*/ vadd.vv /*c1*/ v1 /*c2*/ , /*c3*/ v2 /*c4*/ , /*c5*/ v3 /*c6*/ , /*c7*/ v0.t /*c8*/
+# CHECK: vadd.vv v1, v2, v3, v0.t#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8
+
+/*c0*/ cm.push /*c1*/ { /*c2*/ ra /*c3*/ , /*c4*/ s0 /*c5*/ - /*c6*/ s1 /*c7*/ } /*c8*/ , /*c9*/ - /*c10*/ 32 /*c11*/
+# CHECK: cm.push {ra, s0-s1}, -32#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11
+
+/*c0*/ cm.popret /*c0*/ { /*c1*/ x1 /*c2*/ , /*c3*/ x8 /*c4*/ - /*c5*/ x9 /*c6*/ , /*c7*/ x18 /*c8*/ - /*c9*/ x20 /*c10*/ } /*c11*/ , /*c12*/ 64 /*c13*/
+# CHECK: cm.popret   {ra, s0-s4}, 64 #c0 #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12#c13
+
+/*c0*/ fence /*c1*/ 0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: fence   0, 0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence /*c1*/ iorw /*c2*/ , /*c3*/ iorw /*c4*/
+# CHECK: fence   #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence.tso /*c1*/
+# CHECK: fence.tso   #c0 #c1
+
+/*c0*/ fence.i /*c1*/
+# CHECK: fence.i #c0 #c1
+
+/*c0*/ nop /*c1*/
+# CHECK: nop	#c0	#c1
+
+/*c0*/ .option /*c1*/ arch /*c2*/ , /*c3*/ rv64gc /*c4*/
+# CHECK: .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0
+
+/*c0*/ .attribute /*c1*/ priv_spec /*c2*/ , /*c3*/ 2 /*c4*/
+# CHECK: .attribute  8, 2
+
+/*c0*/ .attribute /*c1*/ arch /*c2*/ , /*c3*/ "rv32i_zvfbfmin0p6" /*c4*/
+# CHECK: .attribute  5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
Index: llvm/test/MC/RISCV/comments-zdinx.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments-zdinx.ll
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments --mattr=+zdinx  %s | FileCheck %s --match-full-lines
+
+/*c0*/ fmadd.d /*c1*/ x10 /*c2*/ , /*c3*/ x12 /*c4*/ , /*c5*/ x14 /*c6*/ , /*c7*/ x16 /*c8*/ , /*c9*/ dyn /*c10*/
+// CHECK: fmadd.d a0, a2, a4, a6  #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -107,6 +107,8 @@
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
 
+  AsmToken peekNextNext();
+
   bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
  SMLoc &EndLoc) override;
   OperandMatchResultTy tryParseRegister(MCRegister

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-19 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu accepted this revision.
abel-bernabeu added a comment.

Am happy with the current patch version


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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-19 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532758.
abel-bernabeu added a comment.

On the zdinx test, changed a FileCheck comment that was written starting with 
"//" rather than "#".

Changed for "#" just for consistency with the rest of tests.


Repository:
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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/comments-zdinx.ll
  llvm/test/MC/RISCV/comments.ll

Index: llvm/test/MC/RISCV/comments.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments.ll
@@ -0,0 +1,67 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments \
+# RUN:--mattr=+v,+experimental-zfa,+experimental-zcmp,+experimental-ztso %s \
+# RUN:| FileCheck %s  --match-full-lines
+
+/*c0*/ li /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: li	a0, 0	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ ( /*c4*/ a1 /*c5*/ ) /*c6*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ nan /*c4*/
+# CHECK: fli.s	ft0, nan	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ 1.0 /*c4*/
+# CHECK: fli.s	ft0, 1.0	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ auipc /*c1*/ a0 /*c2*/ , /*c3*/ %pcrel_hi /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK:  auipc   a0, %pcrel_hi(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ + /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi0:#c0 #c1 #c2 #c3 #c4 #c5 #c6
+# CHECK-NEXT: auipc   s0, %pcrel_hi(symbol+10)
+# CHECK-NEXT: addis0, s0, %pcrel_lo(.Lpcrel_hi0)
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ - /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi1:#c0 #c1 #c2 #c3 #c4 #c5	#c6
+# CHECK-NEXT: auipc   s0, %pcrel_hi(symbol-10)
+# CHECK-NEXT: addis0, s0, %pcrel_lo(.Lpcrel_hi1)
+
+/*c0*/ vsetivli /*c1*/ a2 /*c2*/ , /*c3*/ 31 /*c4*/ , /*c5*/ e32 /*c6*/ , /*c7*/ m1 /*c8*/ , /*c9*/ ta /*c10*/ , /*c11*/ ma /*c12*/
+# CHECK: vsetivlia2, 31, e32, m1, ta, ma #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12
+
+/*c0*/ vadd.vv /*c1*/ v1 /*c2*/ , /*c3*/ v2 /*c4*/ , /*c5*/ v3 /*c6*/ , /*c7*/ v0.t /*c8*/
+# CHECK: vadd.vv v1, v2, v3, v0.t#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8
+
+/*c0*/ cm.push /*c1*/ { /*c2*/ ra /*c3*/ , /*c4*/ s0 /*c5*/ - /*c6*/ s1 /*c7*/ } /*c8*/ , /*c9*/ - /*c10*/ 32 /*c11*/
+# CHECK: cm.push {ra, s0-s1}, -32#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11
+
+/*c0*/ cm.popret /*c0*/ { /*c1*/ x1 /*c2*/ , /*c3*/ x8 /*c4*/ - /*c5*/ x9 /*c6*/ , /*c7*/ x18 /*c8*/ - /*c9*/ x20 /*c10*/ } /*c11*/ , /*c12*/ 64 /*c13*/
+# CHECK: cm.popret   {ra, s0-s4}, 64 #c0 #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12#c13
+
+/*c0*/ fence /*c1*/ 0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: fence   0, 0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence /*c1*/ iorw /*c2*/ , /*c3*/ iorw /*c4*/
+# CHECK: fence   #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence.tso /*c1*/
+# CHECK: fence.tso   #c0 #c1
+
+/*c0*/ fence.i /*c1*/
+# CHECK: fence.i #c0 #c1
+
+/*c0*/ nop /*c1*/
+# CHECK: nop	#c0	#c1
+
+/*c0*/ .option /*c1*/ arch /*c2*/ , /*c3*/ rv64gc /*c4*/
+# CHECK: .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0
+
+/*c0*/ .attribute /*c1*/ priv_spec /*c2*/ , /*c3*/ 2 /*c4*/
+# CHECK: .attribute  8, 2
+
+/*c0*/ .attribute /*c1*/ arch /*c2*/ , /*c3*/ "rv32i_zvfbfmin0p6" /*c4*/
+# CHECK: .attribute  5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
Index: llvm/test/MC/RISCV/comments-zdinx.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments-zdinx.ll
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments --mattr=+zdinx  %s | FileCheck %s --match-full-lines
+
+/*c0*/ fmadd.d /*c1*/ x10 /*c2*/ , /*c3*/ x12 /*c4*/ , /*c5*/ x14 /*c6*/ , /*c7*/ x16 /*c8*/ , /*c9*/ dyn /*c10*/
+# CHECK: fmadd.d a0, a2, a4, a6  #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -107,6 +107,8 @@
uint64_t &ErrorInfo,
bool MatchingInlineAsm) override;
 
+  AsmToken peekNextNext();
+
   bool parseRegister(MCRe

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-19 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added a comment.

@jrtc27:

The tests:

- are under llvm/test/MC/RISCV
- use llvm-mc as assembler (rather than C!)
- are as simple as they can be
- cover every line touched by this patch.

Would you unblock this now? Thanks for your feedback so far.

@MaskRay:

Let me know if you miss any testing or places where comments are still not 
possible. Am pretty sure I am covering every case.

You have been added as coauthor here (with the standard "Co-Authored-By: " tag 
on the commit message) and you can close https://reviews.llvm.org/D153204 in 
return :)


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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-20 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532837.
abel-bernabeu added a comment.

I just this flashback...

For code coverage of one of the Lex() calls in ParseInstruction we needed one 
case
where an instruction has no operands.

We had, not one, but three. Am keeping just the "nop" case, which is the 
simplest
and most known instruction and moving it to the top of the test suite, so the 
tests
are listed in increasing complexity (from the simplest to reach test points to
the most sophisticated and least frequently used parser features).


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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/comments-zdinx.ll
  llvm/test/MC/RISCV/comments.ll

Index: llvm/test/MC/RISCV/comments.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments.ll
@@ -0,0 +1,61 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments \
+# RUN:--mattr=+v,+experimental-zfa,+experimental-zcmp,+experimental-ztso %s \
+# RUN:| FileCheck %s  --match-full-lines
+
+/*c0*/ nop /*c1*/
+# CHECK: nop	#c0	#c1
+
+/*c0*/ li /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: li	a0, 0	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ ( /*c4*/ a1 /*c5*/ ) /*c6*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ nan /*c4*/
+# CHECK: fli.s	ft0, nan	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ 1.0 /*c4*/
+# CHECK: fli.s	ft0, 1.0	#c0	#c1	#c2	#c3	#c4
+
+/*c0*/ auipc /*c1*/ a0 /*c2*/ , /*c3*/ %pcrel_hi /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK:  auipc   a0, %pcrel_hi(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ + /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi0:#c0 #c1 #c2 #c3 #c4 #c5 #c6
+# CHECK-NEXT: auipc   s0, %pcrel_hi(symbol+10)
+# CHECK-NEXT: addis0, s0, %pcrel_lo(.Lpcrel_hi0)
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ - /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi1:#c0 #c1 #c2 #c3 #c4 #c5	#c6
+# CHECK-NEXT: auipc   s0, %pcrel_hi(symbol-10)
+# CHECK-NEXT: addis0, s0, %pcrel_lo(.Lpcrel_hi1)
+
+/*c0*/ vsetivli /*c1*/ a2 /*c2*/ , /*c3*/ 31 /*c4*/ , /*c5*/ e32 /*c6*/ , /*c7*/ m1 /*c8*/ , /*c9*/ ta /*c10*/ , /*c11*/ ma /*c12*/
+# CHECK: vsetivlia2, 31, e32, m1, ta, ma #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12
+
+/*c0*/ vadd.vv /*c1*/ v1 /*c2*/ , /*c3*/ v2 /*c4*/ , /*c5*/ v3 /*c6*/ , /*c7*/ v0.t /*c8*/
+# CHECK: vadd.vv v1, v2, v3, v0.t#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8
+
+/*c0*/ cm.push /*c1*/ { /*c2*/ ra /*c3*/ , /*c4*/ s0 /*c5*/ - /*c6*/ s1 /*c7*/ } /*c8*/ , /*c9*/ - /*c10*/ 32 /*c11*/
+# CHECK: cm.push {ra, s0-s1}, -32#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11
+
+/*c0*/ cm.popret /*c0*/ { /*c1*/ x1 /*c2*/ , /*c3*/ x8 /*c4*/ - /*c5*/ x9 /*c6*/ , /*c7*/ x18 /*c8*/ - /*c9*/ x20 /*c10*/ } /*c11*/ , /*c12*/ 64 /*c13*/
+# CHECK: cm.popret   {ra, s0-s4}, 64 #c0 #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12#c13
+
+/*c0*/ fence /*c1*/ 0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: fence   0, 0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence /*c1*/ iorw /*c2*/ , /*c3*/ iorw /*c4*/
+# CHECK: fence   #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ .option /*c1*/ arch /*c2*/ , /*c3*/ rv64gc /*c4*/
+# CHECK: .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0
+
+/*c0*/ .attribute /*c1*/ priv_spec /*c2*/ , /*c3*/ 2 /*c4*/
+# CHECK: .attribute  8, 2
+
+/*c0*/ .attribute /*c1*/ arch /*c2*/ , /*c3*/ "rv32i_zvfbfmin0p6" /*c4*/
+# CHECK: .attribute  5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
Index: llvm/test/MC/RISCV/comments-zdinx.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments-zdinx.ll
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments --mattr=+zdinx  %s | FileCheck %s --match-full-lines
+
+/*c0*/ fmadd.d /*c1*/ x10 /*c2*/ , /*c3*/ x12 /*c4*/ , /*c5*/ x14 /*c6*/ , /*c7*/ x16 /*c8*/ , /*c9*/ dyn /*c10*/
+# CHECK: fmadd.d a0, a2, a4, a6  #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -107,6 +107,8 @@

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-21 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 533191.
abel-bernabeu added a comment.

Addressed some review comments:

- Doxygen-style comments are not common, so using triple-slash instead.
- Using a regular C array on a place where the usage of SmallVector is not 
justified.
- Proper capitalization of a variable
- Usage of "&&" rather than "and", to blend better with the existing code style.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

https://reviews.llvm.org/D153008

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/comments-zdinx.ll
  llvm/test/MC/RISCV/comments.ll

Index: llvm/test/MC/RISCV/comments.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments.ll
@@ -0,0 +1,70 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments \
+# RUN:--mattr=+v,+experimental-zfa,+experimental-zcmp,+experimental-ztso %s \
+# RUN:| FileCheck %s
+
+/*c0*/ li /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: li  a0, 0   # c0# c1# c2# c3
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ ( /*c4*/ a1 /*c5*/ ) /*c6*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ nan /*c4*/
+# CHECK: fli.s   ft0, nan#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ 1.0 /*c4*/
+# CHECK: fli.s   ft0, 1.0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ auipc /*c1*/ a0 /*c2*/ , /*c3*/ %pcrel_hi /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK:  auipc   a0, %pcrel_hi(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ + /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi0:#c0 #c1 #c2 #c3 #c4 #c5 #c6
+# CHECK: auipc   s0, %pcrel_hi(symbol+10)
+# CHECK: addis0, s0, %pcrel_lo(.Lpcrel_hi0)
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ - /*c5*/ 10
+# CHECK: .Lpcrel_hi1:#c0 #c1 #c2 #c3 #c4 #c5
+# CHECK: auipc   s0, %pcrel_hi(symbol-10)
+# CHECK: addis0, s0, %pcrel_lo(.Lpcrel_hi1)
+
+/*c0*/ vsetivli /*c1*/ a2 /*c2*/ , /*c3*/ 31 /*c4*/ , /*c5*/ e32 /*c6*/ , /*c7*/ m1 /*c8*/ , /*c9*/ ta /*c10*/ , /*c11*/ ma /*c12*/
+# CHECK: vsetivlia2, 31, e32, m1, ta, ma #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12
+
+/*c0*/ vadd.vv /*c1*/ v1 /*c2*/ , /*c3*/ v2 /*c4*/ , /*c5*/ v3 /*c6*/ , /*c7*/ v0.t /*c8*/
+# CHECK: vadd.vv v1, v2, v3, v0.t#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8
+
+/*c0*/ cm.push /*c1*/ { /*c2*/ ra /*c3*/ , /*c4*/ s0 /*c5*/ - /*c6*/ s1 /*c7*/ } /*c8*/ , /*c9*/ - /*c10*/ 32 /*c11*/
+# CHECK: cm.push {ra, s0-s1}, -32#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11
+
+/*c0*/ cm.popret /*c0*/ { /*c1*/ x1 /*c2*/ , /*c3*/ x8 /*c4*/ - /*c5*/ x9 /*c6*/ , /*c7*/ x18 /*c8*/ - /*c9*/ x20 /*c10*/ } /*c11*/ , /*c12*/ 64 /*c13*/
+# CHECK: cm.popret   {ra, s0-s4}, 64 #c0 #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12#c13
+
+/*c0*/ fence /*c1*/ 0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: fence   0, 0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence /*c1*/ iorw /*c2*/ , /*c3*/ iorw /*c4*/
+# CHECK: fence   #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence.tso /*c1*/
+# CHECK: fence.tso   #c0 #c1
+
+/*c0*/ fence.i /*c1*/
+# CHECK: fence.i #c0 #c1
+
+/*c0*/ nop /*c1*/
+# CHECK: nop #c0 #c1
+
+/*c0*/ .option /*c1*/ arch /*c2*/ , /*c3*/ rv64gc /*c4*/
+# CHECK: #c0 #c1 #c2 #c3 #c4
+# CHECK-NEXT: .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0
+
+/*c0*/ .attribute /*c1*/ priv_spec /*c2*/ , /*c3*/ 2 /*c4*/
+# CHECK: .attribute  8, 2
+# CHECK-NEXT: #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ .attribute /*c1*/ arch /*c2*/ , /*c3*/ "rv32i_zvfbfmin0p6" /*c4*/
+# CHECK: .attribute  5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
+# CHECK-NEXT: #c0 #c1 #c2 #c3 #c4
\ No newline at end of file
Index: llvm/test/MC/RISCV/comments-zdinx.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments-zdinx.ll
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments --mattr=+zdinx  %s | FileCheck %s
+
+/*c0*/ fmadd.d /*c1*/ x10 /*c2*/ , /*c3*/ x12 /*c4*/ , /*c5*/ x14 /*c6*/ , /*c7*/ x16 /*c8*/ , /*c9*/ dyn /*c10*/
+// CHECK: fmadd.d a0, a2, a4, a6  #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10
\ No newline at end of file
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
=

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-21 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 533193.
abel-bernabeu added a comment.

Reduced the commit message verbosity by one half, without losing anything.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

https://reviews.llvm.org/D153008

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/comments-zdinx.ll
  llvm/test/MC/RISCV/comments.ll

Index: llvm/test/MC/RISCV/comments.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments.ll
@@ -0,0 +1,70 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments \
+# RUN:--mattr=+v,+experimental-zfa,+experimental-zcmp,+experimental-ztso %s \
+# RUN:| FileCheck %s
+
+/*c0*/ li /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: li  a0, 0   # c0# c1# c2# c3
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ ( /*c4*/ a1 /*c5*/ ) /*c6*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ nan /*c4*/
+# CHECK: fli.s   ft0, nan#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ 1.0 /*c4*/
+# CHECK: fli.s   ft0, 1.0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ auipc /*c1*/ a0 /*c2*/ , /*c3*/ %pcrel_hi /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK:  auipc   a0, %pcrel_hi(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ + /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi0:#c0 #c1 #c2 #c3 #c4 #c5 #c6
+# CHECK: auipc   s0, %pcrel_hi(symbol+10)
+# CHECK: addis0, s0, %pcrel_lo(.Lpcrel_hi0)
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ - /*c5*/ 10
+# CHECK: .Lpcrel_hi1:#c0 #c1 #c2 #c3 #c4 #c5
+# CHECK: auipc   s0, %pcrel_hi(symbol-10)
+# CHECK: addis0, s0, %pcrel_lo(.Lpcrel_hi1)
+
+/*c0*/ vsetivli /*c1*/ a2 /*c2*/ , /*c3*/ 31 /*c4*/ , /*c5*/ e32 /*c6*/ , /*c7*/ m1 /*c8*/ , /*c9*/ ta /*c10*/ , /*c11*/ ma /*c12*/
+# CHECK: vsetivlia2, 31, e32, m1, ta, ma #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12
+
+/*c0*/ vadd.vv /*c1*/ v1 /*c2*/ , /*c3*/ v2 /*c4*/ , /*c5*/ v3 /*c6*/ , /*c7*/ v0.t /*c8*/
+# CHECK: vadd.vv v1, v2, v3, v0.t#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8
+
+/*c0*/ cm.push /*c1*/ { /*c2*/ ra /*c3*/ , /*c4*/ s0 /*c5*/ - /*c6*/ s1 /*c7*/ } /*c8*/ , /*c9*/ - /*c10*/ 32 /*c11*/
+# CHECK: cm.push {ra, s0-s1}, -32#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11
+
+/*c0*/ cm.popret /*c0*/ { /*c1*/ x1 /*c2*/ , /*c3*/ x8 /*c4*/ - /*c5*/ x9 /*c6*/ , /*c7*/ x18 /*c8*/ - /*c9*/ x20 /*c10*/ } /*c11*/ , /*c12*/ 64 /*c13*/
+# CHECK: cm.popret   {ra, s0-s4}, 64 #c0 #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12#c13
+
+/*c0*/ fence /*c1*/ 0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: fence   0, 0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence /*c1*/ iorw /*c2*/ , /*c3*/ iorw /*c4*/
+# CHECK: fence   #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence.tso /*c1*/
+# CHECK: fence.tso   #c0 #c1
+
+/*c0*/ fence.i /*c1*/
+# CHECK: fence.i #c0 #c1
+
+/*c0*/ nop /*c1*/
+# CHECK: nop #c0 #c1
+
+/*c0*/ .option /*c1*/ arch /*c2*/ , /*c3*/ rv64gc /*c4*/
+# CHECK: #c0 #c1 #c2 #c3 #c4
+# CHECK-NEXT: .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0
+
+/*c0*/ .attribute /*c1*/ priv_spec /*c2*/ , /*c3*/ 2 /*c4*/
+# CHECK: .attribute  8, 2
+# CHECK-NEXT: #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ .attribute /*c1*/ arch /*c2*/ , /*c3*/ "rv32i_zvfbfmin0p6" /*c4*/
+# CHECK: .attribute  5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
+# CHECK-NEXT: #c0 #c1 #c2 #c3 #c4
\ No newline at end of file
Index: llvm/test/MC/RISCV/comments-zdinx.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments-zdinx.ll
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments --mattr=+zdinx  %s | FileCheck %s
+
+/*c0*/ fmadd.d /*c1*/ x10 /*c2*/ , /*c3*/ x12 /*c4*/ , /*c5*/ x14 /*c6*/ , /*c7*/ x16 /*c8*/ , /*c9*/ dyn /*c10*/
+// CHECK: fmadd.d a0, a2, a4, a6  #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10
\ No newline at end of file
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -107,6 +107,8 @@
uint64_t &ErrorInfo

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-21 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 533194.
abel-bernabeu added a comment.

Even less verbosity...


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

https://reviews.llvm.org/D153008

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/comments-zdinx.ll
  llvm/test/MC/RISCV/comments.ll

Index: llvm/test/MC/RISCV/comments.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments.ll
@@ -0,0 +1,70 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments \
+# RUN:--mattr=+v,+experimental-zfa,+experimental-zcmp,+experimental-ztso %s \
+# RUN:| FileCheck %s
+
+/*c0*/ li /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: li  a0, 0   # c0# c1# c2# c3
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ 0 /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ lw /*c1*/ a0 /*c2*/ , /*c3*/ ( /*c4*/ a1 /*c5*/ ) /*c6*/
+# CHECK: lw  a0, 0(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ nan /*c4*/
+# CHECK: fli.s   ft0, nan#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fli.s /*c1*/ ft0 /*c2*/ , /*c3*/ 1.0 /*c4*/
+# CHECK: fli.s   ft0, 1.0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ auipc /*c1*/ a0 /*c2*/ , /*c3*/ %pcrel_hi /*c4*/ ( /*c5*/ a1 /*c6*/ ) /*c7*/
+# CHECK:  auipc   a0, %pcrel_hi(a1)   #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ + /*c5*/ 10 /*c6*/
+# CHECK: .Lpcrel_hi0:#c0 #c1 #c2 #c3 #c4 #c5 #c6
+# CHECK: auipc   s0, %pcrel_hi(symbol+10)
+# CHECK: addis0, s0, %pcrel_lo(.Lpcrel_hi0)
+
+/*c0*/ la /*c1*/ s0 /*c2*/ , /*c3*/ symbol /*c4*/ - /*c5*/ 10
+# CHECK: .Lpcrel_hi1:#c0 #c1 #c2 #c3 #c4 #c5
+# CHECK: auipc   s0, %pcrel_hi(symbol-10)
+# CHECK: addis0, s0, %pcrel_lo(.Lpcrel_hi1)
+
+/*c0*/ vsetivli /*c1*/ a2 /*c2*/ , /*c3*/ 31 /*c4*/ , /*c5*/ e32 /*c6*/ , /*c7*/ m1 /*c8*/ , /*c9*/ ta /*c10*/ , /*c11*/ ma /*c12*/
+# CHECK: vsetivlia2, 31, e32, m1, ta, ma #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12
+
+/*c0*/ vadd.vv /*c1*/ v1 /*c2*/ , /*c3*/ v2 /*c4*/ , /*c5*/ v3 /*c6*/ , /*c7*/ v0.t /*c8*/
+# CHECK: vadd.vv v1, v2, v3, v0.t#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8
+
+/*c0*/ cm.push /*c1*/ { /*c2*/ ra /*c3*/ , /*c4*/ s0 /*c5*/ - /*c6*/ s1 /*c7*/ } /*c8*/ , /*c9*/ - /*c10*/ 32 /*c11*/
+# CHECK: cm.push {ra, s0-s1}, -32#c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11
+
+/*c0*/ cm.popret /*c0*/ { /*c1*/ x1 /*c2*/ , /*c3*/ x8 /*c4*/ - /*c5*/ x9 /*c6*/ , /*c7*/ x18 /*c8*/ - /*c9*/ x20 /*c10*/ } /*c11*/ , /*c12*/ 64 /*c13*/
+# CHECK: cm.popret   {ra, s0-s4}, 64 #c0 #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10#c11#c12#c13
+
+/*c0*/ fence /*c1*/ 0 /*c2*/ , /*c3*/ 0 /*c4*/
+# CHECK: fence   0, 0#c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence /*c1*/ iorw /*c2*/ , /*c3*/ iorw /*c4*/
+# CHECK: fence   #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ fence.tso /*c1*/
+# CHECK: fence.tso   #c0 #c1
+
+/*c0*/ fence.i /*c1*/
+# CHECK: fence.i #c0 #c1
+
+/*c0*/ nop /*c1*/
+# CHECK: nop #c0 #c1
+
+/*c0*/ .option /*c1*/ arch /*c2*/ , /*c3*/ rv64gc /*c4*/
+# CHECK: #c0 #c1 #c2 #c3 #c4
+# CHECK-NEXT: .option arch, rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0
+
+/*c0*/ .attribute /*c1*/ priv_spec /*c2*/ , /*c3*/ 2 /*c4*/
+# CHECK: .attribute  8, 2
+# CHECK-NEXT: #c0 #c1 #c2 #c3 #c4
+
+/*c0*/ .attribute /*c1*/ arch /*c2*/ , /*c3*/ "rv32i_zvfbfmin0p6" /*c4*/
+# CHECK: .attribute  5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
+# CHECK-NEXT: #c0 #c1 #c2 #c3 #c4
\ No newline at end of file
Index: llvm/test/MC/RISCV/comments-zdinx.ll
===
--- /dev/null
+++ llvm/test/MC/RISCV/comments-zdinx.ll
@@ -0,0 +1,4 @@
+# RUN: llvm-mc -triple=riscv64 --preserve-comments --mattr=+zdinx  %s | FileCheck %s
+
+/*c0*/ fmadd.d /*c1*/ x10 /*c2*/ , /*c3*/ x12 /*c4*/ , /*c5*/ x14 /*c6*/ , /*c7*/ x16 /*c8*/ , /*c9*/ dyn /*c10*/
+// CHECK: fmadd.d a0, a2, a4, a6  #c0 #c1 #c2 #c3 #c4 #c5 #c6 #c7 #c8 #c9 #c10
\ No newline at end of file
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -107,6 +107,8 @@
uint64_t &ErrorInfo,
bool MatchingInlin

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-15 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
hiraditya, kristof.beyls, arichardson.
Herald added a project: All.
abel-bernabeu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, pcwang-thead, eopXD, 
MaskRay.
Herald added projects: clang, LLVM.

It had been reported by one of Esperanto's customers that slash-start
comments ("/*") within inline assembly were only allowed before the
first instruction operand or at the end of the lines. However, those
comments were not allowed when interleaved within the operands.

An example follows:

  unsigned long int dst;
  __asm__ __volatile__(
"li /* this is fine */ %[dst], /* this was NOT fine */ 0x1234\n"
"add zero, %[dst], %[dst]\n"
: [ dst ] "=r"(dst)
:
:);

A code review of the top level parser (AsmParser class) showed that
when comments are place before the instruction operand or at end of
a line, then they are gracefully handled irrespective of the backend.
When the comments are interleaved within the instruction operands it
is the backend's responsibility to handle the comments.

Explicitly handling the comments in the RISC-V backend is not a too
invasive patch and fixes the issue.

Thanks to David Spikett from Arm's community for pointing out where to
start looking within the LLVM code base.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153008

Files:
  clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp


Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2573,14 +2573,26 @@
   if (parseOperand(Operands, Name))
 return true;
 
+  // Silently ignore comments after the first operand for compatibility with 
gcc
+  while (getLexer().is(AsmToken::Comment))
+getLexer().Lex();
+
   // Parse until end of statement, consuming commas between operands
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma token
 getLexer().Lex();
 
+// Silently ignore comments before operand for compatibility with gcc
+while (getLexer().is(AsmToken::Comment))
+  getLexer().Lex();
+
 // Parse next operand
 if (parseOperand(Operands, Name))
   return true;
+
+// Silently ignore comments after operand for compatibility with gcc
+while (getLexer().is(AsmToken::Comment))
+  getLexer().Lex();
   }
 
   if (getParser().parseEOL("unexpected token")) {
Index: clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
===
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
@@ -0,0 +1,31 @@
+// RUN: %clang -fPIC --target=riscv64-unknown-elf -mabi=lp64f -O3 -o - -S %s | 
FileCheck %s
+
+unsigned long int f1() {
+  unsigned long int dst;
+  __asm__ __volatile__("li %[dst], 0x1234 /* this is fine */ \n"
+   "add zero, %[dst], %[dst]\n"
+   : [ dst ] "=r"(dst)
+   :
+   :);
+  return dst;
+}
+
+unsigned long int f2() {
+  unsigned long int dst;
+  __asm__ __volatile__("li /* this is fine */ %[dst], /* this should also be 
fine */ 0x1234\n"
+   "add zero, %[dst], %[dst]\n"
+   : [ dst ] "=r"(dst)
+   :
+   :);
+  return dst;
+}
+// CHECK: f1:
+// CHECK:  lui a0, 1
+// CHECK-NEXT: addiw   a0, a0, 564
+// CHECK-NEXT: add zero, a0, a0
+// CHECK:  ret
+// CHECK: f2:
+// CHECK:  lui a0, 1
+// CHECK-NEXT: addiw   a0, a0, 564
+// CHECK-NEXT: add zero, a0, a0
+// CHECK:  ret


Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -2573,14 +2573,26 @@
   if (parseOperand(Operands, Name))
 return true;
 
+  // Silently ignore comments after the first operand for compatibility with gcc
+  while (getLexer().is(AsmToken::Comment))
+getLexer().Lex();
+
   // Parse until end of statement, consuming commas between operands
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma token
 getLexer().Lex();
 
+// Silently ignore comments before operand for compatibility with gcc
+while (getLexer().is(AsmToken::Comment))
+  getLexer().Lex();
+
 // Parse next operand
 if (parseOperand(Operands, Name))
   return true;

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-15 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added a comment.

For the customer who reported the problem, the comments are in the input source 
(doing their job explaining what the operands are).

Now, if that comment is not seen when compiling with "-S" it is less of a 
problem that having the compilation not succeeding. I did not see an obvious 
way to pass those coments to the AsmParser instance.

My understanding is that the ParseInstruction interface needs to be extended 
for the comments to be collected and passed to the top level parser (similarly 
to what is done with the operands).


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

https://reviews.llvm.org/D153008

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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-15 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 531735.
abel-bernabeu added a comment.

  [RISCV] Allow slash-star comments in instruction operands
  
  It has been reported by one of Esperanto's customers that slash-start
  comments ("/*") within inline assembly were only allowed before the
  first instruction operand or at the end of the lines. Those comments
  were, however, not allowed when interleaved within the operands.
  
  An example follows:
  
  unsigned long int dst;
  __asm__ __volatile__(
"li /* this was fine */ %[dst], /* this was NOT fine */ 0x1234\n"
"add zero, %[dst], %[dst]\n"
: [ dst ] "=r"(dst)
:
:);
  
  A code review of the top level parser (AsmParser class) showed that
  when comments were placed before the instruction operand or at end of
  a line, then they were gracefully handled irrespective of the backend.
  When the comments were interleaved within the instruction operands it
  was the backend's responsibility to handle the comments.
  
  RISC-V's backend did not handle the comments in any way.
  
  Beyond the obvious solution of explicitly handling the comments within
  the RISC-V backend, another, easier to maintain solution was suggested
  by Sergei Barannikov in a Discourse discussion thread:
  
  
https://discourse.llvm.org/t/interleaving-several-c-style-comments-in-the-same-inline-assembly-line/71353/8
  
  In summary, all backends, including the RISC-V's, should switch
  from getLexer().Lex() to getParser().Lex() in their ParseInstruction
  implementation.
  
  The getLexer().Lex() approach relies on the user to explicitly handle
  the comments, whereas the suggested getParser().Lex() alternive already
  handles the comments in the same way as done for non-target-specific
  assembly directives.
  
  Here we just do the RISC-V work. Other backends should also do their own
  review.
  
  In addition to Sergei Barannikov, I would also we thank David Spikett
  from Arm's community for pointing out where to start looking within the
  LLVM code base, and also the patch reviewers.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

https://reviews.llvm.org/D153008

Files:
  clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2410,12 +2410,12 @@
   Error(getLoc(), "continuous register list must start from 's0' or 'x8'");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex(); // eat reg
+getParser().Lex(); // eat reg
   }
 
   // parse case like -s1
   if (getLex

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-15 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 531740.
abel-bernabeu added a comment.

[RISCV] Allow slash-star comments in instruction operands

It has been reported by one of Esperanto's customers that slash-start
comments ("/*") within inline assembly were only allowed before the
first instruction operand or at the end of the lines. Those comments
were, however, not allowed when interleaved within the operands.

An example follows:

  unsigned long int dst;
  __asm__ __volatile__(
"li /* this was fine */ %[dst], /* this was NOT fine */ 0x1234\n"
"add zero, %[dst], %[dst]\n"
: [ dst ] "=r"(dst)
:
:);

A code review of the top level parser (AsmParser class) showed that
when comments were placed before the instruction operand or at end of
a line, then they were gracefully handled irrespective of the backend.
When the comments were interleaved within the instruction operands it
was the backend's responsibility to handle the comments.

RISC-V's backend did not handle the comments in any way.

Beyond the obvious solution of explicitly handling the comments within
the RISC-V backend, another, easier to maintain solution was suggested
by Sergei Barannikov in a Discourse discussion thread:

https://discourse.llvm.org/t/interleaving-several-c-style-comments-in-the-same-inline-assembly-line/71353/8

In summary, all backends, including the RISC-V's, should switch
from getLexer().Lex() to getParser().Lex() in their ParseInstruction
implementation.

The getLexer().Lex() approach relies on the user to explicitly handle
the comments, whereas the suggested getParser().Lex() alternive already
handles the comments in the same way as done for non-target-specific
assembly directives.

Here we just do the RISC-V work. Other backends should also do their own
review.

In addition to Sergei Barannikov, I would also we thank David Spikett
from Arm's community for pointing out where to start looking within the
LLVM code base, and also the patch reviewers.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

https://reviews.llvm.org/D153008

Files:
  clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2410,12 +2410,12 @@
   Error(getLoc(), "continuous register list must start from 's0' or 'x8'");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex(); // eat reg
+getParser().Lex(); // eat reg
   }
 
   // parse case like -s1
   if (getLexer().is(AsmToken::Minus)) {
-getLexer().Lex();
+getParser().Lex();

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-15 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added a comment.

I was a bit reluctant to start a discussion on migrating getLexer().Lex() to 
getParser().Lex(), but I guess it makes sense to do it now rather than 
deferring.

It is cleaner now, I agree.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-15 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 531741.
abel-bernabeu added a comment.

  [RISCV] Allow slash-star comments in instruction operands
  
  It has been reported by one of Esperanto's customers that slash-start
  comments ("/*") within inline assembly were only allowed before the
  first instruction operand or at the end of the lines. Those comments
  were, however, not allowed when interleaved within the operands.
  
  An example follows:
  
  ```
  unsigned long int dst;
  __asm__ __volatile__(
"li /* this was fine */ %[dst], /* this was NOT fine */ 0x1234\n"
"add zero, %[dst], %[dst]\n"
: [ dst ] "=r"(dst)
:
:);
  ```
  
  A code review of the top level parser (AsmParser class) showed that
  when comments were placed before the instruction operand or at end of
  a line, then they were gracefully handled irrespective of the backend.
  When the comments were interleaved within the instruction operands it
  was the backend's responsibility to handle the comments.
  
  RISC-V's backend did not handle the comments in any way.
  
  Beyond the obvious solution of explicitly handling the comments within
  the RISC-V backend, another, easier to maintain solution was suggested
  by Sergei Barannikov in a Discourse discussion thread:
  
  
https://discourse.llvm.org/t/interleaving-several-c-style-comments-in-the-same-inline-assembly-line/71353/8
  
  In summary, all backends, including the RISC-V's, should switch
  from getLexer().Lex() to getParser().Lex() in their ParseInstruction
  implementation.
  
  The getLexer().Lex() approach relies on the user to explicitly handle
  the comments, whereas the suggested getParser().Lex() alternive already
  handles the comments in the same way as done for non-target-specific
  assembly directives.
  
  Here we just do the RISC-V work. Other backends should also do their own
  review.
  
  In addition to Sergei Barannikov, I would also like to thank David Spikett
  from Arm's community for pointing out where to start looking within the
  LLVM code base, and also the patch reviewers.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

https://reviews.llvm.org/D153008

Files:
  clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2410,12 +2410,12 @@
   Error(getLoc(), "continuous register list must start from 's0' or 'x8'");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex(); // eat reg
+getParser().Lex(); // eat reg
   }
 
   // parse case like

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-15 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 531746.
abel-bernabeu added a comment.

[RISCV] Allow slash-star comments in instruction operands

It has been reported by one of Esperanto's customers that slash-start
comments ("/*") within inline assembly were only allowed before the
first instruction operand or at the end of the lines. Those comments
were, however, not allowed when interleaved within the operands.

An example follows:

  unsigned long int dst;
  __asm__ __volatile__(
"li /* this was fine */ %[dst], /* this was NOT fine */ 0x1234\n"
"add zero, %[dst], %[dst]\n"
: [ dst ] "=r"(dst)
:
:);

A code review of the top level parser (AsmParser class) showed that
when comments were placed before the instruction operand or at end of
a line, then they were gracefully handled irrespective of the backend.
When the comments were interleaved within the instruction operands it
was the backend's responsibility to handle the comments.

RISC-V's backend did not handle the comments in any way.

Beyond the obvious solution of explicitly handling the comments within
the RISC-V backend, another, easier to maintain, was suggested by Sergei
Barannikov in a Discourse discussion thread:

https://discourse.llvm.org/t/interleaving-several-c-style-comments-in-the-same-inline-assembly-line/71353/8

In summary, all backends, including the RISC-V's, should switch
from getLexer().Lex() to getParser().Lex() in their ParseInstruction
implementation.

The getLexer().Lex() approach relies on the user to explicitly handle
the comments, whereas the suggested getParser().Lex() alternive already
handles the comments in the same way as done for non-target-specific
assembly directives.

Here we just do the RISC-V work. Other backends should also do their own
review.

In addition to Sergei Barannikov, I would also like to thank David Spikett
from Arm's community for pointing out where to start looking within the
LLVM code base, and also the patch reviewers.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

https://reviews.llvm.org/D153008

Files:
  clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2410,12 +2410,12 @@
   Error(getLoc(), "continuous register list must start from 's0' or 'x8'");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex(); // eat reg
+getParser().Lex(); // eat reg
   }
 
   // parse case like -s1
   if (getLexer().is(AsmToken::Minus)) {
-getLexer().Lex();
+getParser().Lex();
 St

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-15 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added a comment.

In D153008#4424821 , @jrtc27 wrote:

> Clang tests should not compile to asm. You want an IR test.

Jessica, are there any exceptions for tests is under CodeGen/RISCV intended to 
exercise the assembly parser?

I have just written a test that reproduces the way I manually test the feature.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D153008/new/

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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-15 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added a comment.

Thanks everyone, taking notes of all the comments for improving the test:

- Simplify the test (can be one instruction, no problem).
- Check at IR level
- Check for the comments to be placed in the output
- Do "arc diff" with one-line descriptions

Will update before tomorrow at mid-day (CET).


Repository:
  rG LLVM Github Monorepo

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[PATCH] D153150: [RISCV] Allow slash-star comments in instruction operands

2023-06-16 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu created this revision.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, 
shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, 
hiraditya, kristof.beyls, arichardson.
Herald added a project: All.
abel-bernabeu requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, wangpc, eopXD, MaskRay.
Herald added projects: clang, LLVM.

It has been reported by one of Esperanto's customers that slash-start
comments ("/*") within inline assembly were only allowed before the
first instruction operand or at the end of the lines. Those comments
were, however, not allowed when interleaved within the operands.

An example follows:

  unsigned long int dst;
  __asm__ __volatile__(
"li /* this was fine */ %[dst], /* this was NOT fine */ 0x1234\n"
"add zero, %[dst], %[dst]\n"
: [ dst ] "=r"(dst)
:
:);

A code review of the top level parser (AsmParser class) showed that
when comments were placed before the instruction operand or at end of
a line, then they were gracefully handled irrespective of the backend.
When the comments were interleaved within the instruction operands it
was the backend's responsibility to handle the comments.

RISC-V's backend did not handle the comments in any way.

Beyond the obvious solution of explicitly handling the comments within
the RISC-V backend, another, easier to maintain, was suggested by Sergei
Barannikov in a Discourse discussion thread:

https://discourse.llvm.org/t/interleaving-several-c-style-comments-in-the-same-inline-assembly-line/71353/8

In summary, all backends, including the RISC-V's, should switch
from getLexer().Lex() to getParser().Lex() in their ParseInstruction
implementation.

The getLexer().Lex() approach relies on the user to explicitly handle
the comments, whereas the suggested getParser().Lex() alternive already
handles the comments in the same way as done for non-target-specific
assembly directives.

Here we just do the RISC-V work. Other backends should also do their own
review.

In addition to Sergei Barannikov, I would also like to thank David Spikett
from Arm's community for pointing out where to start looking within the
LLVM code base, and also the patch reviewers.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153150

Files:
  clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return Matc

[PATCH] D153150: [RISCV] Allow slash-star comments in instruction operands

2023-06-16 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532182.
abel-bernabeu added a comment.

Simplified the test and checking for comments to be carried over to the 
assembly output


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153150/new/

https://reviews.llvm.org/D153150

Files:
  clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2410,12 +2410,12 @@
   Error(getLoc(), "continuous register list must start from 's0' or 'x8'");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex(); // eat reg
+getParser().Lex(); // eat reg
   }
 
   // parse case like -s1
   if (getLexer().is(AsmToken::Minus)) {
-getLexer().Lex();
+getParser().Lex();
 StringRef EndName = getLexer().getTok().getIdentifier();
 // FIXME: the register mapping and checks of EABI is wrong
 RegEnd = matchRegisterNameHelper(IsEABI, EndName);
@@ -2428,7 +2428,7 @@
   "'x8-x9' pair");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (!IsEABI) {
@@ -2442,7 +2442,7 @@
   }
 
   // parse ', x18' for extra part
-  getLexer().Lex();
+  getParser().Lex();
   if (getLexer().isNot(AsmToken::Identifier)) {
 Error(getLoc(), "invalid register");
 return MatchOperand_ParseFail;
@@ -2453,11 +2453,11 @@
 "must start from 'x18'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse '-x20' for extra part
   if (getLexer().is(AsmToken::Minus)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2467,7 +2467,7 @@
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex();
+getParser().Lex();
   }
   RegEnd = MatchRegisterName(EndName);
 }
@@ -2497,7 +2497,7 @@
 
 OperandMatchResultTy RISCVAsmParser::parseZcmpSpimm(OperandVector &Operands) {
   if (getLexer().is(AsmToken::Minus))
-getLexer().Lex();
+getParser().Lex();
 
   SMLoc S = getLoc();
   int64_t StackAdjustment = getLexer().getTok().getIntVal();
@@ -2508,7 +2508,7 @@
   if (!RISCVZC::getSpimm(RlistVal, Spimm, StackAdjustment, isRV64(), IsEABI))
 return MatchOperand_NoMatch;
   Operands.push_back(RISCVOperand::createSpimm(Spimm << 4, S));
-  getLexer().Le

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-16 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532185.
abel-bernabeu added a comment.

Simplified the test. Also I check that the comments are a carried over to the 
assembly output.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153008/new/

https://reviews.llvm.org/D153008

Files:
  clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2410,12 +2410,12 @@
   Error(getLoc(), "continuous register list must start from 's0' or 'x8'");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex(); // eat reg
+getParser().Lex(); // eat reg
   }
 
   // parse case like -s1
   if (getLexer().is(AsmToken::Minus)) {
-getLexer().Lex();
+getParser().Lex();
 StringRef EndName = getLexer().getTok().getIdentifier();
 // FIXME: the register mapping and checks of EABI is wrong
 RegEnd = matchRegisterNameHelper(IsEABI, EndName);
@@ -2428,7 +2428,7 @@
   "'x8-x9' pair");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (!IsEABI) {
@@ -2442,7 +2442,7 @@
   }
 
   // parse ', x18' for extra part
-  getLexer().Lex();
+  getParser().Lex();
   if (getLexer().isNot(AsmToken::Identifier)) {
 Error(getLoc(), "invalid register");
 return MatchOperand_ParseFail;
@@ -2453,11 +2453,11 @@
 "must start from 'x18'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse '-x20' for extra part
   if (getLexer().is(AsmToken::Minus)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2467,7 +2467,7 @@
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex();
+getParser().Lex();
   }
   RegEnd = MatchRegisterName(EndName);
 }
@@ -2497,7 +2497,7 @@
 
 OperandMatchResultTy RISCVAsmParser::parseZcmpSpimm(OperandVector &Operands) {
   if (getLexer().is(AsmToken::Minus))
-getLexer().Lex();
+getParser().Lex();
 
   SMLoc S = getLoc();
   int64_t StackAdjustment = getLexer().getTok().getIntVal();
@@ -2508,7 +2508,7 @@
   if (!RISCVZC::getSpimm(RlistVal, Spimm, StackAdjustment, isRV64(), IsEABI))
 return MatchOperand_NoMatch;
   Operands.push_back(RISCVOperand::createSpimm(Spimm << 4, S));
-  getLex

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-16 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added a comment.

In D153008#4425244 , @jrtc27 wrote:

> In D153008#4425238 , @abel-bernabeu 
> wrote:
>
>> In D153008#4424821 , @jrtc27 wrote:
>>
>>> Clang tests should not compile to asm. You want an IR test.
>>
>> Jessica, are there any exceptions for tests is under CodeGen/RISCV intended 
>> to exercise the assembly parser?
>>
>> I have just written a test that reproduces the way I manually test the 
>> feature.
>
> No. You can test the assembly parser just as easily from IR.
>
> I'll also note that your assembly isn't particularly minimal, which it should 
> be, unless the `add zero, %[dst], %[dst]` lines are doing something I'm not 
> aware of?

Jessica, the LLVM IR form contains the inline assembly still unparsed. Look, 
this is what I get:

  abel@Docker:~/work/llvm-project/build$ ./bin/clang -fPIC 
--target=riscv64-unknown-elf   -o - -S  -emit-llvm  
../clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c 
  ; ModuleID = '../clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c'
  source_filename = 
"../clang/test/CodeGen/RISCV/riscv-inline-asm-gcc-commenting.c"
  target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
  target triple = "riscv64-unknown-unknown-elf"
  
  ; Function Attrs: noinline nounwind optnone
  define i64 @f() #0 {
%1 = alloca i64, align 8
%2 = call i64 asm "li /* this is fine */ $0 , /* this is also fine */ 0 /* 
and last but not least */\0A", "=r"() #1, !srcloc !6
store i64 %2, ptr %1, align 8
%3 = load i64, ptr %1, align 8
ret i64 %3
  }
  
  attributes #0 = { noinline nounwind optnone "frame-pointer"="all" 
"no-trapping-math"="true" "stack-protector-buffer-size"="8" 
"target-cpu"="generic-rv64" 
"target-features"="+64bit,+a,+c,+m,+relax,-d,-e,-experimental-smaia,-experimental-ssaia,-experimental-zca,-experimental-zcb,-experimental-zcd,-experimental-zcf,-experimental-zcmp,-experimental-zcmt,-experimental-zfa,-experimental-zfbfmin,-experimental-zicond,-experimental-zihintntl,-experimental-ztso,-experimental-zvbb,-experimental-zvbc,-experimental-zvfbfmin,-experimental-zvfbfwma,-experimental-zvfh,-experimental-zvkg,-experimental-zvkn,-experimental-zvknc,-experimental-zvkned,-experimental-zvkng,-experimental-zvknha,-experimental-zvknhb,-experimental-zvks,-experimental-zvksc,-experimental-zvksed,-experimental-zvksg,-experimental-zvksh,-experimental-zvkt,-f,-h,-save-restore,-svinval,-svnapot,-svpbmt,-v,-xsfvcp,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zdinx,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zicbom,-zicbop,-zicboz,-zicntr,-zicsr,-zifencei,-zihintpause,-zihpm,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b"
 }
  attributes #1 = { nounwind memory(none) }
  
  !llvm.module.flags = !{!0, !1, !2, !3, !4}
  !llvm.ident = !{!5}
  
  !0 = !{i32 1, !"wchar_size", i32 4}
  !1 = !{i32 1, !"target-abi", !"lp64"}
  !2 = !{i32 8, !"PIC Level", i32 2}
  !3 = !{i32 7, !"frame-pointer", i32 2}
  !4 = !{i32 8, !"SmallDataLimit", i32 0}
  !5 = !{!"clang version 17.0.0 (g...@github.com:llvm/llvm-project.git 
61bab164d4c3b15ba13ddd53de7bdeb6b8c9de30)"}
  !6 = !{i64 139}

From the provided assembly template only the substituion of "%[dst]" for "$0" 
is observable on the LLVM IR.

Am I misinterpreting your suggestion? Thanks in advance for you clarification.


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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-16 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu marked an inline comment as done.
abel-bernabeu added a comment.

In D153008#4428568 , @MaskRay wrote:

> This new update still applies many unneeded `getParser().Lex();` and adds a 
> test at a wrong layer 
> 
>  (clang/test/CodeGen):

Your comment in here suggests a full review of the parser to make the code 
consistent with the principle that a token should be eaten in the same function 
that checks for a specific pattern.

https://discourse.llvm.org/t/interleaving-several-c-style-comments-in-the-same-inline-assembly-line/71353/10

I like the suggestion, just a couple of questions:

- is it something that you would like to try yourself?
- do you want me to create a refactoring ticket for myself? Not sure when will 
I be highly available for a major refactor, but I can try to assign time at 
work for the task.

Let me know your preference.


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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-16 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added a comment.

In D153008#4428568 , @MaskRay wrote:

> This new update still applies many unneeded `getParser().Lex();` and adds a 
> test at a wrong layer 
> 
>  (clang/test/CodeGen):

Would you rather have:

- LLVM IR as input
- assembly as output
- the test placed under llvm/test/CodeGen/RISCV/

?

That would make the test for verbose, but it would make the test simple. Please 
confirm your preference.


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[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-16 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu updated this revision to Diff 532268.
abel-bernabeu added a comment.

The test has been moved to llvm/test/CodeGen/RISCV

Also has been reworked for using LLVM IR as input, so clang is not needed in 
the loop.


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Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/CodeGen/RISCV/inline-asm-gcc-comments.ll

Index: llvm/test/CodeGen/RISCV/inline-asm-gcc-comments.ll
===
--- /dev/null
+++ llvm/test/CodeGen/RISCV/inline-asm-gcc-comments.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IF %s
+
+define i64 @f() #0 {
+; RV32IF-LABEL:   f:
+; RV32IF: li a0, 0 # this is fine # this is also fine # and last but not least
+;
+; RV64IF-LABEL:   f:
+; RV64IF: li a0, 0 # this is fine # this is also fine # and last but not least
+  %1 = alloca i64, align 8
+  %2 = call i64 asm "li /* this is fine */ $0 , /* this is also fine */ 0 /* and last but not least */\0A", "=r"()
+  store i64 %2, ptr %1, align 8
+  %3 = load i64, ptr %1, align 8
+  ret i64 %3
+}
\ No newline at end of file
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
   Operands.push_back(RISCVOperand::createToken("(", FirstS));
 SMLoc S = getLoc();
 SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-getLexer().Lex();
+getParser().Lex();
 Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
 return MatchOperand_Success;
   case AsmToken::Plus:
 Opcode = MCBinaryExpr::Add;
-getLexer().Lex();
+getParser().Lex();
 break;
   case AsmToken::Minus:
 Opcode = MCBinaryExpr::Sub;
-getLexer().Lex();
+getParser().Lex();
 break;
   }
 
@@ -2131,11 +2131,11 @@
   MaskAgnostic))
 return MatchOperand_NoMatch;
 
-  getLexer().Lex();
+  getParser().Lex();
 
   while (getLexer().is(AsmToken::Comma)) {
 // Consume comma.
-getLexer().Lex();
+getParser().Lex();
 
 if (getLexer().isNot(AsmToken::Identifier))
   break;
@@ -2146,7 +2146,7 @@
 MaskAgnostic))
   break;
 
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {
@@ -2186,7 +2186,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   return MatchOperand_Success;
 }
@@ -2202,7 +2202,7 @@
 return MatchOperand_NoMatch;
   SMLoc S = getLoc();
   SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-  getLexer().Lex();
+  getParser().Lex();
   Operands.push_back(RISCVOperand::createReg(
   RegNo, S, E, !getSTI().hasFeature(RISCV::FeatureStdExtF)));
   return MatchOperand_Success;
@@ -2391,11 +2391,11 @@
 Error(getLoc(), "register list must start from 'ra' or 'x1'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().Lex();
 
   // parse case like ,s0
   if (getLexer().is(AsmToken::Comma)) {
-getLexer().Lex();
+getParser().Lex();
 if (getLexer().isNot(AsmToken::Identifier)) {
   Error(getLoc(), "invalid register");
   return MatchOperand_ParseFail;
@@ -2410,12 +2410,12 @@
   Error(getLoc(), "continuous register list must start from 's0' or 'x8'");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex(); // eat reg
+getParser().Lex(); // eat reg
   }
 
   // parse case like -s1
   if (getLexer().is(AsmToken::Minus)) {
-getLexer().Lex();
+getParser().Lex();
 StringRef EndName = getLexer().getTok().getIdentifier();
 // FIXME: the register mapping and checks of EABI is wrong
 RegEnd = matchRegisterNameHelper(IsEABI, EndName);
@@ -2428,7 +2428,7 @@
   "'x8-x9' pair");
   return MatchOperand_ParseFail;
 }
-getLexer().Lex();
+getParser().Lex();
   }
 
   if (!IsEABI) {
@@ -2442,7 +2442,7 @@
   }
 
   // parse ', x18' for extra part
-  getLexer().Lex();
+  getParser().Lex();
   if (getLexer().isNot(AsmToken::Identifier)) {
 Error(getLoc(), "invalid register");
 return MatchOperand_ParseFail;
@@ -2453,11 +2453,11 @@
 "must start from 'x18'");
 return MatchOperand_ParseFail;
   }
-  getLexer().Lex();
+  getParser().

[PATCH] D153008: [RISCV] Allow slash-star comments in instruction operands

2023-06-16 Thread Abel Bernabeu via Phabricator via cfe-commits 
abel-bernabeu added a comment.

In D153008#4424821 , @jrtc27 wrote:

> Clang tests should not compile to asm. You want an IR test.

My bad. You suggested IR as input (rather than C) and makes total sense. The 
latest update captures that suggestion.


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