[Bug binutils/4781] binutils 2.17.50.0.7 and later eats up memory when calling gnujava wizards in OpenOffice
--- Additional Comments From jakub at redhat dot com 2007-07-23 13:39 --- If you get an 8 byte .eh_frame_hdr section in the linked libc.so, then I'd like an reproducer from you, because all my x86_64 glibcs are just fine when compiled with recent (e.g. 2.17.50.0.12) binutils. So, please pack up: elf/ld.so libc.map libc_pic.a libc_pic.os shlib.lds csu/abi-note.o elf/soinit.os elf/sofini.os elf/interp.os in your glibc build directory and your `gcc -print-file-name=libgcc.a` and attach it as a bzip2ed tarball here as attachment. Also mention the exact ld command line that was used to link your libc.so - rerun the gcc -shared -static-libgcc -o /libc.so command from your glibc build log with additional -v and past the collect2 command line here. Thanks. -- What|Removed |Added Status|NEW |WAITING http://sourceware.org/bugzilla/show_bug.cgi?id=4781 --- You are receiving this mail because: --- You are on the CC list for the bug, or are watching someone who is. ___ bug-binutils mailing list bug-binutils@gnu.org http://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug binutils/4834] New: Incorrect bytemode in x86 disassembler
Disassembler prints incorrect bytemode for SSE insns in Intel syntax. % objdump -v GNU objdump (GNU Binutils) 2.17.50.20070723 Copyright 2007 Free Software Foundation, Inc. This program is free software; you may redistribute it under the terms of the GNU General Public License version 3 or (at your option) any later version. This program has absolutely no warranty. % cat sse.s .byte 0xF2, 0x0F, 0x5E, 0x00 .byte 0xF3, 0x0F, 0x5E, 0x00 .byte 0xF2, 0x0F, 0x5F, 0x00 .byte 0xF3, 0x0F, 0x5F, 0x00 .byte 0xF2, 0x0F, 0x5D, 0x00 .byte 0xF3, 0x0F, 0x5D, 0x00 .byte 0xF3, 0x0F, 0x10, 0x00 .byte 0xF3, 0x0F, 0x11, 0x00 .byte 0xF2, 0x0F, 0x10, 0x00 .byte 0xF2, 0x0F, 0x11, 0x00 .byte 0xF2, 0x0F, 0x59, 0x00 .byte 0xF3, 0x0F, 0x59, 0x00 .byte 0xF3, 0x0F, 0x53, 0x00 .byte 0xF3, 0x0F, 0x52, 0x00 .byte 0xF2, 0x0F, 0x51, 0x00 .byte 0xF3, 0x0F, 0x51, 0x00 .byte 0xF2, 0x0F, 0x5C, 0x00 .byte 0xF3, 0x0F, 0x5C, 0x00 .byte 0xF3, 0x0F, 0x5A, 0x00 .byte 0xF2, 0x0F, 0x5A, 0x00 % as sse.s -o sse.o % objdump -dw -Mintel --section="LC_SEGMENT.__TEXT.__text" sse.o sse.o: file format mach-o-le Disassembly of section LC_SEGMENT.__TEXT.__text: : 0: f2 0f 5e 00 divsd xmm0,XMMWORD PTR [eax] 4: f3 0f 5e 00 divss xmm0,XMMWORD PTR [eax] 8: f2 0f 5f 00 maxsd xmm0,XMMWORD PTR [eax] c: f3 0f 5f 00 maxss xmm0,XMMWORD PTR [eax] 10: f2 0f 5d 00 minsd xmm0,XMMWORD PTR [eax] 14: f3 0f 5d 00 minss xmm0,XMMWORD PTR [eax] 18: f3 0f 10 00 movss xmm0,XMMWORD PTR [eax] 1c: f3 0f 11 00 movss XMMWORD PTR [eax],xmm0 20: f2 0f 10 00 movsd xmm0,XMMWORD PTR [eax] 24: f2 0f 11 00 movsd XMMWORD PTR [eax],xmm0 28: f2 0f 59 00 mulsd xmm0,XMMWORD PTR [eax] 2c: f3 0f 59 00 mulss xmm0,XMMWORD PTR [eax] 30: f3 0f 53 00 rcpss xmm0,XMMWORD PTR [eax] 34: f3 0f 52 00 rsqrtss xmm0,XMMWORD PTR [eax] 38: f2 0f 51 00 sqrtsd xmm0,XMMWORD PTR [eax] 3c: f3 0f 51 00 sqrtss xmm0,XMMWORD PTR [eax] 40: f2 0f 5c 00 subsd xmm0,XMMWORD PTR [eax] 44: f3 0f 5c 00 subss xmm0,XMMWORD PTR [eax] 48: f3 0f 5a 00 cvtss2sd xmm0,XMMWORD PTR [eax] 4c: f2 0f 5a 00 cvtsd2ss xmm0,XMMWORD PTR [eax] All above modes are XMMWORD, but that's wrong. Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 2A & 2B In the manuals, it's written as follows. Opcode Instruction F2 0F 5E /r DIVSD xmm1, xmm2/m64 F3 0F 5E /r DIVSS xmm1, xmm2/m32 F2 0F 5F /r MAXSD xmm1, xmm2/m64 F3 0F 5F /r MAXSS xmm1, xmm2/m32 F2 0F 5D /r MINSD xmm1, xmm2/m64 F3 0F 5D /r MINSS xmm1, xmm2/m32 F3 0F 10 /r MOVSS xmm1, xmm2/m32 F3 0F 11 /r MOVSS xmm2/m32, xmm F2 0F 10 /r MOVSD xmm1, xmm2/m64 F2 0F 11 /r MOVSD xmm2/m64, xmm1 F2 0F 59 /r MULSD xmm1, xmm2/m64 F3 0F 59 /r MULSS xmm1, xmm2/m32 F3 0F 53 /r RCPSS xmm1, xmm2/m32 F3 0F 52 /r RSQRTSS xmm1, xmm2/m32 F2 0F 51 /r SQRTSD xmm1, xmm2/m64 F3 0F 51 /r SQRTSS xmm1, xmm2/m32 F2 0F 5C /r SUBSD xmm1, xmm2/m64 F3 0F 5C /r SUBSS xmm1, xmm2/m32 F3 0F 5A /r CVTSS2SD xmm1, xmm2/m32 F2 0F 5A /r CVTSD2SS xmm1, xmm2/m64 -- Summary: Incorrect bytemode in x86 disassembler Product: binutils Version: 2.18 (HEAD) Status: NEW Severity: normal Priority: P2 Component: binutils AssignedTo: unassigned at sources dot redhat dot com ReportedBy: ht at inter7 dot jp CC: bug-binutils at gnu dot org GCC host triplet: i686-apple-darwin http://sourceware.org/bugzilla/show_bug.cgi?id=4834 --- You are receiving this mail because: --- You are on the CC list for the bug, or are watching someone who is. ___ bug-binutils mailing list bug-binutils@gnu.org http://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug binutils/4835] New: movd insn isn't changed to movq in x86-64 disassembler
With REX.W prefix, "movd" insn changes to "movq" in 64 bit mode, Intel syntax. But disassembler still prints movd and doesn't recognize REX.W prefix. % objdump -v GNU objdump (GNU Binutils) 2.17.50.20070723 Copyright 2007 Free Software Foundation, Inc. This program is free software; you may redistribute it under the terms of the GNU General Public License version 3 or (at your option) any later version. This program has absolutely no warranty. % cat movq.s .byte 0x48, 0x0F, 0x6E, 0x00 .byte 0x48, 0x0F, 0x7E, 0x00 .byte 0x48, 0x66, 0x0F, 0x6E, 0x00 .byte 0x48, 0x66, 0x0F, 0x7E, 0x00 % as movq.s -o movq.o % objdump -dw -Mintel,x86-64 --section="LC_SEGMENT.__TEXT.__text" movq.o movq.o: file format mach-o-le Disassembly of section LC_SEGMENT.__TEXT.__text: : 0: 48 0f 6e 00 movd mm0,QWORD PTR [rax] 4: 48 0f 7e 00 movd QWORD PTR [rax],mm0 8: 48 rex.W 9: 66 0f 6e 00 movd xmm0,DWORD PTR [rax] d: 48 rex.W e: 66 0f 7e 00 movd DWORD PTR [rax],xmm0 In Intel CPU manual, it's written: MOVD/MOVQ Opcode Instruction REX.W + 0F 6E /rMOVQ mm, r/m64 REX.W + 0F 7E /rMOVQ r/m64, mm REX.W + 66 0F 6E /r MOVQ xmm, r/m64 REX.W + 66 0F 7E /r MOVQ r/m64, xmm -- Summary: movd insn isn't changed to movq in x86-64 disassembler Product: binutils Version: 2.18 (HEAD) Status: NEW Severity: normal Priority: P2 Component: binutils AssignedTo: unassigned at sources dot redhat dot com ReportedBy: ht at inter7 dot jp CC: bug-binutils at gnu dot org GCC host triplet: i686-apple-darwin http://sourceware.org/bugzilla/show_bug.cgi?id=4835 --- You are receiving this mail because: --- You are on the CC list for the bug, or are watching someone who is. ___ bug-binutils mailing list bug-binutils@gnu.org http://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug binutils/4835] movd insn isn't changed to movq in x86-64 disassembler
--- Additional Comments From ht at inter7 dot jp 2007-07-24 04:35 --- Some more similar issue. REX.W is ignored. (some are incorrect bytemode) % cat rex.w.s .text .byte 0x48, 0xF2, 0x0F, 0x2A, 0x00 .byte 0x48, 0xF3, 0x0F, 0x2A, 0x00 .byte 0x48, 0xF2, 0x0F, 0x2D, 0x00 .byte 0x48, 0xF3, 0x0F, 0x2D, 0x00 .byte 0x48, 0xF2, 0x0F, 0x2C, 0x00 .byte 0x48, 0xF3, 0x0F, 0x2C, 0x00 % as rex.w.s -o rex.w.o % objdump -dw -Mintel,x86-64 --section="LC_SEGMENT.__TEXT.__text" rex.w.o rex.w.o: file format mach-o-le Disassembly of section LC_SEGMENT.__TEXT.__text: : 0: 48 rex.W 1: f2 0f 2a 00 cvtsi2sd xmm0,DWORD PTR [rax] 5: 48 rex.W 6: f3 0f 2a 00 cvtsi2ss xmm0,DWORD PTR [rax] a: 48 rex.W b: f2 0f 2d 00 cvtsd2si eax,XMMWORD PTR [rax] f: 48 rex.W 10: f3 0f 2d 00 cvtss2si eax,XMMWORD PTR [rax] 14: 48 rex.W 15: f2 0f 2c 00 cvttsd2si eax,XMMWORD PTR [rax] 19: 48 rex.W 1a: f3 0f 2c 00 cvttss2si eax,XMMWORD PTR [rax] Intel CPU manual writes: Opcode Instruction REX.W + F2 0F 2A /r CVTSI2SD xmm, r/m64 REX.W + F3 0F 2A /r CVTSI2SS xmm, r/m64 REX.W + F2 0F 2D /r CVTSD2SI r64, xmm/m64 REX.W + F3 0F 2D /r CVTSS2SI r64, xmm/m32 REX.W + F2 0F 2C /r CVTTSD2SI r64, xmm/m64 REX.W + F3 0F 2C /r CVTTSS2SI r64, xmm/m32 -- http://sourceware.org/bugzilla/show_bug.cgi?id=4835 --- You are receiving this mail because: --- You are on the CC list for the bug, or are watching someone who is. ___ bug-binutils mailing list bug-binutils@gnu.org http://lists.gnu.org/mailman/listinfo/bug-binutils
[Bug binutils/4834] Incorrect bytemode in x86 disassembler
--- Additional Comments From ht at inter7 dot jp 2007-07-24 04:37 --- Some more bytemode issues. % cat cvt.s .text .byte 0xF2, 0x0F, 0xC2, 0x00, 0x00 .byte 0xF3, 0x0F, 0xC2, 0x00, 0x00 .byte 0x66, 0x0F, 0x2A, 0x00 .byte 0x0F, 0x2D, 0x00 .byte 0xF2, 0x0F, 0x2D, 0x00 .byte 0x0F, 0x2C, 0x00 .byte 0xF2, 0x0F, 0x2C, 0x00 .byte 0xF3, 0x0F, 0x2C, 0x00 % as cvt.s -o cvt.o % objdump -dw -Mintel --section="LC_SEGMENT.__TEXT.__text" cvt.o cvt.o: file format mach-o-le Disassembly of section LC_SEGMENT.__TEXT.__text: : 0: f2 0f c2 00 00 cmpeqsd xmm0,XMMWORD PTR [eax] 5: f3 0f c2 00 00 cmpeqss xmm0,XMMWORD PTR [eax] a: 66 0f 2a 00 cvtpi2pd xmm0,XMMWORD PTR [eax] e: 0f 2d 00cvtps2pi mm0,XMMWORD PTR [eax] 11: f2 0f 2d 00 cvtsd2si eax,XMMWORD PTR [eax] 15: 0f 2c 00cvttps2pi mm0,XMMWORD PTR [eax] 18: f2 0f 2c 00 cvttsd2si eax,XMMWORD PTR [eax] 1c: f3 0f 2c 00 cvttss2si eax,XMMWORD PTR [eax] Intel manual says: Opcode Instruction F2 0F C2 /r ib CMPSD xmm1, xmm2/m64, imm8 F3 0F C2 /r ib CMPSS xmm1, xmm2/m32, imm8 66 0F 2A /r CVTPI2PD xmm, mm/m64 0F 2D /rCVTPS2PI mm, xmm/m64 F2 0F 2D /r CVTSD2SI r32, xmm/m64 0F 2C /rCVTTPS2PI mm, xmm/m64 F2 0F 2C /r CVTTSD2SI r32, xmm/m64 F3 0F 2C /r CVTTSS2SI r32, xmm/m32 -- http://sourceware.org/bugzilla/show_bug.cgi?id=4834 --- You are receiving this mail because: --- You are on the CC list for the bug, or are watching someone who is. ___ bug-binutils mailing list bug-binutils@gnu.org http://lists.gnu.org/mailman/listinfo/bug-binutils
