On Thu, Jul 9, 2015 at 8:46 AM, Rob Clark wrote:
> From: Rob Clark
>
> Some, but not all, state trackers will explicitly unref (and set to
> NULL) the previous *fence before calling pipe->flush(). So driver
> should use fence_ref() which will unref the old fence if not NULL.
Looks good. Thanks.
All three are
Acked-by:Chia-I Wu
On Thu, Feb 2, 2017 at 12:15 AM, Edward O'Callaghan
wrote:
> This is no longer actively maintained and is just
> accumulating bitrot.
>
> Signed-off-by: Edward O'Callaghan
> ---
> .../auxiliary/pipe-loader/pipe_loader_drm.c| 5 ---
> src/gallium/auxil
; This patch is to potentially remove ourself from the maintaince
>>>>>>>>> burden of the ilo driver that appears to now be essentially
>>>>>>>>> unmaintained?
>>>>>>>>>
>>>>>>>>> I am not sure of our policy
From: Chia-I Wu
Hi,
This series of patches implements the emulation SIMD16 sample_d with dual
SIMD8 sample_d. Before the changes, the compiler would fail to generate
SIMD16 code for fragment shaders that use textureGrad. And that hurts the
performance.
The first four patches prepare the
From: Chia-I Wu
SIMD8 sampler messages are allowed in SIMD16 mode, and they could not work
without BRW_COMPRESSION_2NDHALF. Later PRMs (gen5 and later) do not
explicitly state whether BRW_COMPRESSION_2NDHALF is allowed, but they do have
examples using send with SecHalf. It should be safe to
From: Chia-I Wu
When the instruction to send the sampler message is forced uncompressed or
sechalf, send SIMD8 one even in SIMD16 mode.
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa
From: Chia-I Wu
FS_OPCODE_OVERWRITE_DST is used to indicate that the destination register is
(completely) overwritten. No code is emitted, but the liveness analysis can
use it as a hint to add the destination register to DEF bitset. This is
needed because it is hard to figure out if some
From: Chia-I Wu
Copy sechalf to the new register, otherwise we would read wrong HW registers.
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
From: Chia-I Wu
Add fs_visitor::emit_texture, which is used to emit the texture instruction
after the message payload has been set up.
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_fs.h | 10 ++-
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 13 ++-
src/mesa/drivers
From: Chia-I Wu
Add fs_visitor::emit_dual_texture_gen7 that emulate SIMD16 sample_d with dual
SIMD8 sample_d on gen7+. Fix fs_generator::generate_tex to send SIMD8
messages when force_uncompressed or force_sechalf is set.
No piglit quick.tests regression on Ivy Bridge and Haswell.
With this
From: Chia-I Wu
Consider only the top-left and top-right pixels to approximate DDX in a 2x2
subspan, unless the application requests a more accurate approximation via
GL_FRAGMENT_SHADER_DERIVATIVE_HINT or this optimization is disabled from the
new driconf option disable_derivative_optimization
On Tue, Oct 1, 2013 at 12:16 PM, Kenneth Graunke wrote:
> On 09/30/2013 07:16 PM, Ian Romanick wrote:
>> On 09/11/2013 10:00 PM, Chia-I Wu wrote:
>>> From: Chia-I Wu
>>>
>>> Replicate the gradient of the top-left pixel to the other three pixels in
>>&g
ve posted my other series that emulates SIMD16 sample_d
with dual SIMD8 sample_d for review.
>
> On Wed, Oct 2, 2013 at 6:38 AM, Ian Romanick wrote:
>> On 09/30/2013 10:54 PM, Chia-I Wu wrote:
>>> From: Chia-I Wu
>>
>> I agree with both of Ken's comments. Wi
On Wed, Oct 9, 2013 at 3:35 AM, Eric Anholt wrote:
> Chia-I Wu writes:
>
>> From: Chia-I Wu
>>
>> FS_OPCODE_OVERWRITE_DST is used to indicate that the destination register is
>> (completely) overwritten. No code is emitted, but the liveness analysis can
From: Chia-I Wu
FS_OPCODE_OVERWRITE_DST is used to indicate that the destination register is
(completely) overwritten. No code is emitted, but the liveness analysis can
use it as a hint to add the destination register to DEF bitset. This is
needed because it is hard to figure out if some
From: Chia-I Wu
Add fs_visitor::emit_texture, which is used to emit the texture instruction
after the message payload has been set up.
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_fs.h | 10 +-
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 13 ++-
src/mesa/drivers
From: Chia-I Wu
Add fs_visitor::emit_dual_texture_gen7 that emulate SIMD16 sample_d with dual
SIMD8 sample_d on gen7+.
No piglit quick.tests regression on Ivy Bridge and Haswell.
Improved Xonotic with Ultra effects by 6.76479% +/- 0.619064% (at 95.0%
confidence) on Haswell.
Signed-off-by
On Sat, Oct 12, 2013 at 3:18 AM, Eric Anholt wrote:
> Chia-I Wu writes:
>
>> Hi Eric,
>> The frame rate of Unigine Tropics (with low shader quality) dropped
>> from 40.8 to 23.5 after this change.
>
> Thanks for the note. I see the regression as well, and I
On Wed, Oct 16, 2013 at 2:08 AM, Ian Romanick wrote:
> On 10/09/2013 12:06 AM, Chia-I Wu wrote:
>> From: Chia-I Wu
>>
>> FS_OPCODE_OVERWRITE_DST is used to indicate that the destination register is
>> (completely) overwritten. No code is emitted, but the liveness
From: Chia-I Wu
When two partial writes write the first and second halves of a variable
respectively before the variable is used, the variable can be added to the def
bitset.
v2: no change
v3: no longer rely on hints from by the visitor
Signed-off-by: Chia-I Wu
---
.../drivers/dri/i965
From: Chia-I Wu
Add fs_visitor::emit_texture, which is used to emit the texture instruction
after the message payload has been set up.
v2: rebased because of texture gather changes
v3: rebased because of texture-from-GRF changes
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_fs.h
From: Chia-I Wu
Add fs_visitor::emit_dual_texture_gen7 that emulate SIMD16 sample_d with dual
SIMD8 sample_d on gen7+.
No piglit quick.tests regression on Ivy Bridge and Haswell.
Improved Xonotic with Ultra effects by 6.0209% +/- 0.396586% (N=11) on
Haswell.
v2: no change
v3: reworked because
On Wed, Oct 16, 2013 at 6:26 AM, Eric Anholt wrote:
> Chia-I Wu writes:
>
>> From: Chia-I Wu
>>
>> FS_OPCODE_OVERWRITE_DST is used to indicate that the destination register is
>> (completely) overwritten. No code is emitted, but the liveness analysis can
Hi Eric,
On Sat, Oct 12, 2013 at 3:18 AM, Eric Anholt wrote:
> Chia-I Wu writes:
>
>> Hi Eric,
>> The frame rate of Unigine Tropics (with low shader quality) dropped
>> from 40.8 to 23.5 after this change.
>
> Thanks for the note. I see the regression as wel
On Thu, Oct 17, 2013 at 1:53 PM, Chia-I Wu wrote:
> Hi Eric,
>
> On Sat, Oct 12, 2013 at 3:18 AM, Eric Anholt wrote:
>> Chia-I Wu writes:
>>
>>> Hi Eric,
>>> The frame rate of Unigine Tropics (with low shader quality) dropped
>>> from 40.8 to 2
On Thu, Oct 17, 2013 at 3:29 PM, Chia-I Wu wrote:
> On Thu, Oct 17, 2013 at 1:53 PM, Chia-I Wu wrote:
>> Hi Eric,
>>
>> On Sat, Oct 12, 2013 at 3:18 AM, Eric Anholt wrote:
>>> Chia-I Wu writes:
>>>
>>>> Hi Eric,
>>>> The frame rate
On Thu, Oct 17, 2013 at 3:24 AM, Matt Turner wrote:
> On Mon, Oct 14, 2013 at 4:14 PM, Eric Anholt wrote:
>> Previously, the best thing we had was to schedule the things unblocked by
>> the current instruction, on the hope that it would be consuming two values
>> at the end of their live interval
On Tue, Oct 15, 2013 at 7:14 AM, Eric Anholt wrote:
> Previously, the best thing we had was to schedule the things unblocked by
> the current instruction, on the hope that it would be consuming two values
> at the end of their live intervals while only producing one new value.
> Sometimes that was
On Tue, Oct 22, 2013 at 3:05 AM, Eric Anholt wrote:
> Chia-I Wu writes:
>
>> On Thu, Oct 17, 2013 at 3:24 AM, Matt Turner wrote:
>>> On Mon, Oct 14, 2013 at 4:14 PM, Eric Anholt wrote:
>>>> Previously, the best thing we had was to schedule the things unblocke
Hi Emil,
On Fri, Jun 13, 2014 at 3:56 AM, Emil Velikov wrote:
> Hi all,
>
> These patches add support for building (grouping) the various targets per
> API, meaning that only one library will be created for e.g. vdpau
> (libvdpau_gallium) with individual ones (libvdpau_r600) being a hardlink
> t
On Wed, Jun 18, 2014 at 8:14 PM, Emil Velikov wrote:
> On 18 June 2014 08:21, Chia-I Wu wrote:
>> Hi Emil,
>>
>> On Fri, Jun 13, 2014 at 3:56 AM, Emil Velikov
>> wrote:
>>> Hi all,
>>>
>>> These patches add support for building (grouping)
Hi list,
This is my second try to add multithread support for the GLSL compiler.
Changes since v1 are
- glLinkProgram can now be threaded
- added ctx->Const.DeferCompileShader and ctx->Const.DeferLinkProgram to
allow drivers to control what get threaded
- minimal changes to i965 to enable D
This thread pool will be used by contexts to queue compilation tasks.
Signed-off-by: Chia-I Wu
---
src/glsl/glsl_parser_extras.cpp | 4 +++
src/glsl/threadpool.c | 72 +
src/glsl/threadpool.h | 9 ++
3 files changed, 85
Split do_vs_prog into
brw_vs_init_compile
brw_vs_do_compile
brw_vs_upload_compile
brw_vs_clear_complile
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_vec4.h | 6 ++
src/mesa/drivers/dri/i965/brw_vs.c | 117 ++-
src/mesa/drivers/dri/i965
It can be used to implement, for example, threaded glCompileShader and
glLinkProgram.
v2: allow tasks to "complete" other tasks
Signed-off-by: Chia-I Wu
---
src/glsl/Makefile.am | 12 +-
src/glsl/Makefile.sources | 3 +-
src/glsl/tests/threadpool_test
We want to add a static object to initialize locale_t in the following commit.
Signed-off-by: Chia-I Wu
---
src/glsl/Makefile.sources | 2 +-
src/glsl/strtod.c | 79 ---
src/glsl/strtod.cpp | 79
The compiler may be used by multiple contexts simultaneously and needs to be
thread-safe.
Signed-off-by: Chia-I Wu
---
src/glsl/strtod.cpp | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/src/glsl/strtod.cpp b/src/glsl/strtod.cpp
index 5d4346b
We are about to change mesa to spawn threads for deferred glCompileShader and
glLinkProgram, and we need to make sure those threads can send compiler
warnings/errors to the debug output safely.
Signed-off-by: Chia-I Wu
---
src/mesa/main/errors.c | 172
Split do_gs_prog into
brw_gs_init_compile
brw_gs_do_compile
brw_gs_upload_compile
brw_gs_clear_complile
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_vec4_gs.c | 153
1 file changed, 96 insertions(+), 57 deletions(-)
diff --git a/src/mesa
er into two parts: the first part links and error checks
while the second part optimizes and generates the machine code. With the
split, we can always defer the second part to the thread pool.
Signed-off-by: Chia-I Wu
---
src/mesa/main/context.c | 29 +++
src/mesa/main/context.
. brw_shader_program_precompile_key
is introduced and initialized in NofityLinkShader for we cannot inspect the
context during precompiling.
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_context.c | 4 +-
src/mesa/drivers/dri/i965/brw_fs.cpp | 33 --
src/mesa/drivers/dri
Setting it to a non-zero value N will cause shader compilation to be deferred
to a thread pool. When N is greater than 1, it indicates the maximum number
of threads in the pool. When N is 1, the number of threads is up to the
driver (two for i965).
Signed-off-by: Chia-I Wu
---
src/mesa
glsl_type has several static hash tables and a static ralloc context. They
need to be protected by a mutex as they are not thread-safe.
Signed-off-by: Chia-I Wu
---
src/glsl/glsl_types.cpp | 57 +++--
src/glsl/glsl_types.h | 15 +
2
Split do_wm_prog into
brw_wm_init_compile
brw_wm_do_compile
brw_wm_upload_compile
brw_wm_clear_complile
Add struct brw_wm_compile to be passed around them.
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_wm.c | 119 -
src/mesa/drivers/dri
There may be two contexts compiling shaders at the same time, and we want the
anonymous struct id to be globally unique.
Signed-off-by: Chia-I Wu
---
src/glsl/glsl_parser_extras.cpp | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/glsl/glsl_parser_extras.cpp b
On Wed, Jul 9, 2014 at 10:42 PM, Brian Paul wrote:
> On 07/09/2014 01:47 AM, Chia-I Wu wrote:
>>
>> It can be used to implement, for example, threaded glCompileShader and
>> glLinkProgram.
>>
>> v2: allow tasks to "complete" other tasks
>>
On Wed, Jul 9, 2014 at 10:42 PM, Brian Paul wrote:
> On 07/09/2014 01:47 AM, Chia-I Wu wrote:
>>
>> Add _mesa_enable_glsl_threadpool to enable the thread pool for a context,
>> and
>> add ctx->Const.DeferCompileShader and ctx->Const.DeferLinkProgram to
&
On Tue, May 7, 2013 at 4:24 AM, Eric Anholt wrote:
> Paul Berry writes:
>
>> Currently the i965 driver uses a single buffer object to hold both batch
>> buffer commands and dynamic state data structures (which are pointed to by
>> batch buffer commands). We use a "stack and heap model", where th
On Wed, Aug 14, 2013 at 1:04 AM, wrote:
> From: Roland Scheidegger
>
> untested.
Looks good to me.
> ---
> src/gallium/drivers/ilo/shader/toy_tgsi.c | 20
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/src/gallium/drivers/ilo/shader/toy_tgsi.c
> b/sr
On Thu, Aug 15, 2013 at 10:03 AM, Kenneth Graunke wrote:
> On 08/08/2013 03:13 PM, Chad Versace wrote:
> [snip]
>>
>> By the way, I talked to krh today, and he suggested that we delete egl_glx
>> rather than allow it to bitrot.
>
>
> I'm in favor, but I don't know who uses that.
>
> GLX on EGL wou
On Sat, Aug 10, 2013 at 2:56 AM, Marek Olšák wrote:
> Most importantly, this hides all LLVM symbols. They shouldn't clash
> with a different LLVM version used by apps (at least in theory).
>
> $ nm -g --defined-only radeonsi_dri.so
> 01148f30 D __driDriverExtensions
I am not familiar with issues r
On Thu, Aug 15, 2013 at 1:26 PM, Chia-I Wu wrote:
> On Sat, Aug 10, 2013 at 2:56 AM, Marek Olšák wrote:
>> Most importantly, this hides all LLVM symbols. They shouldn't clash
>> with a different LLVM version used by apps (at least in theory).
>>
>> $ nm -
LIBGL_SHOW_FPS=1 makes GLX print FPS every second while other values do
nothing. Extend it so that LIBGL_SHOW_FPS=N will print the FPS every N
seconds.
---
src/glx/dri2_glx.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
i
after the change. Thus textureGrad() is lowered unconditionally for now.
Due to this and that I haven't tried it on Haswell, this is still RFC.
No piglit regressions.
Signed-off-by: Chia-I Wu
---
.../dri/i965/brw_lower_texture_gradients.cpp | 54 ++
1 file change
ld allow things like anisotropic filtering to be honored.
> It would be worth doing an image quality comparison before and after the
> change.
Yeah, that is worth doing. I will do that.
>
> -- Chris
>
> On Thu, Sep 5, 2013 at 8:35 PM, Chia-I Wu wrote:
>> sample_d is slower
ng one instead of
> two sqrt (though if your hw has blazing fast sqrt it won't matter...).
Nice.
>
> Roland
>
>
> Am 05.09.2013 10:35, schrieb Chia-I Wu:
>> sample_d is slower than the lowered version on gen7. For gen7, this improves
>> Xono
On Thu, Sep 5, 2013 at 9:57 PM, Chia-I Wu wrote:
> On Thu, Sep 5, 2013 at 5:12 PM, Chris Forbes wrote:
>> A possible explanation for the perf change is that Xonotic uses
>> anisotropic filtering at this quality level. Lowering to txl defeats
>> it.
> I had a l
On Tue, Sep 10, 2013 at 3:48 AM, Ian Romanick wrote:
> On 09/05/2013 08:57 AM, Chia-I Wu wrote:
>> On Thu, Sep 5, 2013 at 5:12 PM, Chris Forbes wrote:
>>> A possible explanation for the perf change is that Xonotic uses
>>> anisotropic filtering at this quality lev
On Tue, Sep 10, 2013 at 4:01 AM, Ian Romanick wrote:
> On 09/06/2013 05:05 AM, Chia-I Wu wrote:
>> On Thu, Sep 5, 2013 at 9:57 PM, Chia-I Wu wrote:
>>> On Thu, Sep 5, 2013 at 5:12 PM, Chris Forbes wrote:
>>>> A possible explanation for the perf change is that
On Tue, Sep 10, 2013 at 4:05 AM, Ian Romanick wrote:
> On 09/05/2013 03:35 AM, Chia-I Wu wrote:
>> sample_d is slower than the lowered version on gen7. For gen7, this improves
>> Xonotic benchmark with Ultimate effects by as much as 25%:
>>
>> before the change:
On Thu, Sep 12, 2013 at 6:32 AM, Johannes Obermayr
wrote:
> ---
> src/gallium/drivers/ilo/Makefile.am | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/ilo/Makefile.am
> b/src/gallium/drivers/ilo/Makefile.am
> index 10b3da3..33f2045 100644
> --- a/src/g
From: Chia-I Wu
Replicate the gradient of the top-left pixel to the other three pixels in the
subspan, as how DDY is implemented. Before, different graidents were used for
pixels in the top row and pixels in the bottom row.
This change results in a less accurate approximation. However, it
On Tue, Sep 10, 2013 at 2:01 PM, Chia-I Wu wrote:
> On Tue, Sep 10, 2013 at 4:05 AM, Ian Romanick wrote:
>> On 09/05/2013 03:35 AM, Chia-I Wu wrote:
>>> sample_d is slower than the lowered version on gen7. For gen7, this
>>> improves
>>> Xonotic benchmark wi
On Tue, Sep 10, 2013 at 1:37 PM, Chia-I Wu wrote:
> On Tue, Sep 10, 2013 at 4:01 AM, Ian Romanick wrote:
>> On 09/06/2013 05:05 AM, Chia-I Wu wrote:
>>> On Thu, Sep 5, 2013 at 9:57 PM, Chia-I Wu wrote:
>>>> On Thu, Sep 5, 2013 at 5:12 PM, Chris Forbes wrote:
&g
On Thu, Sep 12, 2013 at 2:06 PM, Chris Forbes wrote:
> Can we make this approximation conditional on an image-quality control
> in driconf [or somewhere else]?
Sure. What would be the default behavior?
> On Thu, Sep 12, 2013 at 5:00 PM, Chia-I Wu wrote:
>> From: Chia-I Wu
>
n't found
> anything equivalent -- but I might just be being blind.
>
> CC'ing Ian -- any opinion? Is there any conformance issue here?
>
> -- Chris
>
> On Thu, Sep 12, 2013 at 8:41 PM, Chia-I Wu wrote:
>> On Thu, Sep 12, 2013 at 2:06 PM, Chris Forbes wrote:
&
Hi Brian,
On Fri, Sep 13, 2013 at 8:46 AM, Brian Paul wrote:
>
> I just pushed a gallium-bind-sampler-states branch to my git repo at
> git://people.freedesktop.org/~brianp/mesa
>
> It replaces the four
> pipe_context::bind_fragment/vertex/geometry/compute_sampler_states()
> functions with a sing
option, accurate_ddx, to true to
override. accurate_ddx is false by default.
>> On Thu, Sep 12, 2013 at 5:00 PM, Chia-I Wu wrote:
>>> From: Chia-I Wu
>>>
>>> Replicate the gradient of the top-left pixel to the other three pixels in
>>> the
>>> sub
From: Chia-I Wu
Consider only the top-left and top-right pixels to approximate DDX in a 2x2
subspan, unless the application or the user requests a more accurate
approximation. This results in a less accurate approximation. However, it
improves the performance of Xonotic with Ultra settings by
On Sun, Sep 15, 2013 at 12:24 AM, Brian Paul wrote:
> On 09/12/2013 09:06 PM, Chia-I Wu wrote:
>>
>> Hi Brian,
>>
>> On Fri, Sep 13, 2013 at 8:46 AM, Brian Paul wrote:
>>>
>>>
>>> I just pushed a gallium-bind-sampler-states branch to my git
On Sat, Sep 14, 2013 at 5:15 AM, Paul Berry wrote:
> On 12 September 2013 22:06, Chia-I Wu wrote:
>>
>> From: Chia-I Wu
>>
>> Consider only the top-left and top-right pixels to approximate DDX in a
>> 2x2
>> subspan, unless the application or the user re
On Mon, Sep 16, 2013 at 3:50 AM, Mark Mueller wrote:
>
>
>
> On Fri, Sep 13, 2013 at 2:15 PM, Paul Berry wrote:
>>
>> On 12 September 2013 22:06, Chia-I Wu wrote:
>>>
>>> From: Chia-I Wu
>>>
>>> Consider only the top-left and top-righ
On Mon, Sep 16, 2013 at 4:12 PM, Chia-I Wu wrote:
> On Mon, Sep 16, 2013 at 3:50 AM, Mark Mueller wrote:
>>
>>
>>
>> On Fri, Sep 13, 2013 at 2:15 PM, Paul Berry wrote:
>>>
>>> On 12 September 2013 22:06, Chia-I Wu wrote:
>>>>
>>&
On Tue, Sep 17, 2013 at 12:09 AM, Brian Paul wrote:
> On 09/15/2013 09:31 AM, Chia-I Wu wrote:
>>
>> On Sun, Sep 15, 2013 at 12:24 AM, Brian Paul wrote:
>>>
>>> On 09/12/2013 09:06 PM, Chia-I Wu wrote:
>>>>
>>>>
>>>> H
On Wed, Sep 18, 2013 at 6:27 AM, Mark Mueller wrote:
> On Mon, Sep 16, 2013 at 1:31 AM, Chia-I Wu wrote:
>>
>> On Mon, Sep 16, 2013 at 4:12 PM, Chia-I Wu wrote:
>> > On Mon, Sep 16, 2013 at 3:50 AM, Mark Mueller
>> > wrote:
>> >>
>> >>
Hi Paul,
On Mon, Sep 16, 2013 at 3:46 PM, Chia-I Wu wrote:
> On Sat, Sep 14, 2013 at 5:15 AM, Paul Berry wrote:
>> On 12 September 2013 22:06, Chia-I Wu wrote:
>>>
>>> From: Chia-I Wu
>>>
>>> Consider only the top-left and top-right pixels to app
On Fri, Sep 20, 2013 at 10:50 PM, Paul Berry wrote:
> On 17 September 2013 19:54, Chia-I Wu wrote:
>>
>> Hi Paul,
>>
>> On Mon, Sep 16, 2013 at 3:46 PM, Chia-I Wu wrote:
>> > On Sat, Sep 14, 2013 at 5:15 AM, Paul Berry
>> > wrote:
>&
On Mon, Sep 23, 2013 at 12:09 PM, Chia-I Wu wrote:
> On Fri, Sep 20, 2013 at 10:50 PM, Paul Berry wrote:
>> On 17 September 2013 19:54, Chia-I Wu wrote:
>>>
>>> Hi Paul,
>>>
>>> On Mon, Sep 16, 2013 at 3:46 PM, Chia-I Wu wrote:
>>> >
Wrong fields were used when dumping width and height.
---
src/mesa/drivers/dri/i965/brw_state_dump.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state_dump.c
b/src/mesa/drivers/dri/i965/brw_state_dump.c
index 9ea3fac..6fc8837 100644
The inverse repeat count should taks up bits 31:15 and is in U1.16. Demos
from mesa/demos seem to render correctly with this change, bu piglit
"linestipple" test still fails.
---
src/mesa/drivers/dri/i965/brw_misc_state.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
Unlike GEN6, the bits of entry count are distributed like this
width = (entry_count & 0x007f); /* bits [6:0] */
height = (entry_count & 0x001fff80) >> 7; /* bits [20:7] */
depth = (entry_count & 0x7fe0) >> 21; /* bits [30:21] */
The maximum entry count is still limited to 2
Hi list,
On Thu, Dec 13, 2012 at 6:41 AM, Chia-I Wu wrote:
> Hi list,
>
> I've been working on i965g, a new pipe driver for Intel GEN6 (and
> later), for a while now. I would like to know if there is any
> interest in it and if it can be merged upstream. The code is
> c
Hi Matt,
On Wed, Apr 17, 2013 at 12:58 AM, Matt Turner wrote:
> On Tue, Apr 16, 2013 at 9:45 AM, Chia-I Wu wrote:
> > If there is no objection, I'd like to merge it in a day or two.
>
> My only objection is over adding a driver that is explicitly a toy,
> the confusion i
Hi Ken,
On Wed, Apr 17, 2013 at 1:18 AM, Kenneth Graunke wrote:
> On 04/16/2013 09:58 AM, Matt Turner wrote:
>
>> On Tue, Apr 16, 2013 at 9:45 AM, Chia-I Wu wrote:
>>
>>> If there is no objection, I'd like to merge it in a day or two.
>>>
>>
>&
On Wed, Apr 17, 2013 at 5:25 AM, Dave Airlie wrote:
> >> Those are just ideas. I'm open to discussion.
> >
> > The driver is disabled by default and needs to be enabled via
> > --with-gallium-drivers=i965.
>
> I think a warning + maybe something like
> --with-gallium-drivers=i965g-unofficial mig
On Wed, Apr 17, 2013 at 8:09 AM, Marek Olšák wrote:
> On Tue, Apr 16, 2013 at 9:58 PM, Chia-I Wu wrote:
>>
>> On Wed, Apr 17, 2013 at 12:58 AM, Matt Turner wrote:
>>>
>>> I think everything Marek said was correct. If you could extend Gallium
>>>
On Wed, Apr 17, 2013 at 10:26 PM, Brian Paul wrote:
> On 04/17/2013 02:31 AM, Jose Fonseca wrote:
[snipped]
>>> How hard would it be to make GLSL IR an alternative IR for pipe
>>> drivers? On the driver side, it seems I only need to add
>>> PIPE_SHADER_IR_GLSL for the preferred IR and change the
Hi list,
Per the discussion, i965g is confusing and misleading. Instead of
preventing the confusions via
--with-gallium-drivers=i965g-unofficial or
--with-gallium-drivers=experimental-i965g,
which kind of makes i965g a second-class citizen, I think it is better
to rename it. Then whenever
On Thu, Apr 18, 2013 at 11:36 PM, Eric Anholt wrote:
> Chia-I Wu writes:
>
>> Hi list,
>>
>> Per the discussion, i965g is confusing and misleading. Instead of
>> preventing the confusions via
>>
>> --with-gallium-drivers=i965g-unofficial or
>
When the depth buffer is already cleared, skip GEN6_HIZ_OP_DEPTH_CLEAR. This
is made possible by tracking which slices have been cleared in
"struct intel_mipmap_level". The hiz_cleared flag is unset when the depth
buffer is rendered to or when a HiZ resolve is needed.
For Unigine Tropics, the FP
On Thu, Jan 2, 2014 at 10:39 PM, Steven Newbury wrote:
> Forgot to add signed-off-by...
>
> In trying to get gallium-nine working with the ilo Gallium driver I
> noticed there's no ilo pipe-loader driver being built.
>
> This patch simply puts in place the missing pieces.
>
> The driver descriptor
opics, the FPS improvement is 1.32134% +/- 0.161878% (n=13).
v2:
- unset hiz_cleared automatically in intel_miptree_slice_set_needs_hiz_resolve
- set/unset hiz_cleared with intel_renderbuffer_att_set_needs_depth_resolve
Signed-off-by: Chia-I Wu
---
src/mesa/drivers/dri/i965/brw_clear.c
On Fri, Dec 27, 2013 at 7:25 AM, Chad Versace
wrote:
> On 12/10/2013 09:54 PM, Chia-I Wu wrote:
>>
>> When the depth buffer is already cleared, skip GEN6_HIZ_OP_DEPTH_CLEAR.
>> This
>> is made possible by tracking which slices have been cleared in
>> "struct
On Wed, Jan 8, 2014 at 8:23 PM, Steven Newbury wrote:
> On Fri, 2014-01-03 at 13:14 +0800, Chia-I Wu wrote:
>> On Thu, Jan 2, 2014 at 10:39 PM, Steven Newbury
>> wrote:
>> > Forgot to add signed-off-by...
>> >
>> > In trying to get gallium-nine working
On Thu, Jan 23, 2014 at 12:48 PM, Ian Romanick wrote:
> From: Siavash Eliasi
>
> Ian manually ran the map_buffer_range* tests and the
> arb_map_buffer_alignment-* tests, but he did not do a full piglit run.
Thanks for going ahead and testing. The patch is
Reviewed-by: Chia-I Wu
From: Chia-I Wu
Given
mov vgrf7, vgrf9.xyxz
add vgrf9.xyz, vgrf4.xyzw, vgrf5.xyzw
add vgrf10.x, vgrf6.xyzw, vgrf7.
the last instruction would be wrongly changed to
add vgrf10.x, vgrf6.xyzw, vgrf9.
during copy propagation.
The issue is that when deciding if a record should be
On Tue, Apr 8, 2014 at 2:52 AM, Eric Anholt wrote:
> Chia-I Wu writes:
>
>> From: Chia-I Wu
>>
>> Given
>>
>> mov vgrf7, vgrf9.xyxz
>> add vgrf9.xyz, vgrf4.xyzw, vgrf5.xyzw
>> add vgrf10.x, vgrf6.xyzw, vgrf7.
>>
>> the last
-184)
> Table 3.18 (bottom of page 184 to top of 185)
> Table 3.17 (page 185)
>
> Presumably, people saw table 3.16, then saw the table immediately
> following with DEPTH_COMPONENT* formats, and assumed it was 3.17.
>
> Based on a batch by Chia-I Wu, but without the driconf o
This unit test demonstrates a subtle bug fixed by
4ddf51db6af36736d5d42c1043eeea86e47459ce.
Signed-off-by: Chia-I Wu
Cc: Eric Anholt
---
.../dri/i965/test_vec4_copy_propagation.cpp| 30 ++
1 file changed, 30 insertions(+)
diff --git a/src/mesa/drivers/dri/i965
On Wed, Apr 16, 2014 at 3:18 AM, Eric Anholt wrote:
> Kenneth Graunke writes:
>
>> On 04/14/2014 05:33 PM, Eric Anholt wrote:
>>> This manifested as rendering failures or sometimes GPU hangs in
>>> compositors when they accidentally got MSAA visuals due to a bug in the X
>>> Server. Today we dec
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