[llvm-branch-commits] [llvm] DAG: Call SimplifyDemandedBits on copysign value operand (PR #97180)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/97180 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [CodeGen] Add dump() to MachineTraceMetrics.h (PR #97799)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/97799 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of min/max ISD nodes (PR #100514)

@@ -42,75 +42,50 @@ define i32 @umax(i32 %arg) { ; FAST-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I64 = call <2 x i64> @llvm.umax.v2i64(<2 x i64> undef, <2 x i64> undef) ; FAST-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4I64 =

[llvm-branch-commits] [llvm] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes (PR #100521)

RKSimon wrote: I'm not sure whether its better to just focus on removing some of the custom lowering (and improve TargetLowering::expandFP_TO_INT_SAT) or just add better cost table support. https://github.com/llvm/llvm-project/pull/100521 ___ llvm-br

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mulfix ISD nodes (PR #100520)

https://github.com/RKSimon approved this pull request. LGTM - although I don't think we have any legal/custom cost test coverage (only x86 which exapands) https://github.com/llvm/llvm-project/pull/100520 ___ llvm-branch-commits mailing list llvm-branc

[llvm-branch-commits] [llvm] TTI: Check legalization cost of mul overflow ISD nodes (PR #100519)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/100519 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of abs nodes (PR #100523)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/100523 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] TTI: Check legalization cost of fptosi_sat/fptoui_sat nodes (PR #100521)

https://github.com/RKSimon approved this pull request. LGTM - the x86 lowering needs reworking but that shouldn't hold this PR up. https://github.com/llvm/llvm-project/pull/100521 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] Backport [DAGCombine] Fix multi-use miscompile in load combine (#81586) (PR #81633)

https://github.com/RKSimon approved this pull request. LGTM for backport https://github.com/llvm/llvm-project/pull/81633 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch

[llvm-branch-commits] [llvm] release/18.x: [SelectionDAG] Change computeAliasing signature from optional to LocationSize. (#83017) (PR #83848)

RKSimon wrote: @davemgreen Are there further patches for scalable types coming or is this just to address the ~UINT64_T(0) bugfix? https://github.com/llvm/llvm-project/pull/83848 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] release/18.x: [RISCV] Add test for aliasing miscompile fixed by #83017. NFC (PR #83856)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/83856 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86] Resolve FIXME: Enable PC relative calls on Windows (PR #84185)

RKSimon wrote: Now that 18.1 has been released - we shouldn't be merging anything that isn't just a regression from 17.x I've tried to find the release policy for this in case 18.2 is now allow further merges but I can't find anything? https://github.com/llvm/llvm-project/pull/84185 _

[llvm-branch-commits] [clang] release/18.x [X86_64] fix SSE type error in vaarg (PR #86698)

RKSimon wrote: What are the current rules on cherry picks for old bugs? AFAICT this patch wasn't fixing a bug introduced in the 17.x-18.x development region. https://github.com/llvm/llvm-project/pull/86698 ___ llvm-branch-commits mailing list llvm-bra

[llvm-branch-commits] [llvm] release/18.x: [X86][EVEX512] Check hasEVEX512 for canExtendTo512DQ (#90390) (PR #90422)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90422 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86][EVEX512] Add `HasEVEX512` when `NoVLX` used for 512-bit patterns (#91106) (PR #91118)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91118 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91161)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91161 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [X86][FP16] Do not create VBROADCAST_LOAD for f16 without AVX2 (#91125) (PR #91425)

https://github.com/RKSimon approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/91425 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)

RKSimon wrote: > > @AtariDreams I've noticed you've filed a lot of backport requests. How are > > you choosing which fixes to backport? Is there a specific use case you care > > about? > > There a particular LLVM miscompile bug in WebKit I'm trying to figure out. > It's been there since 2019

[llvm-branch-commits] [llvm] abc60e9 - [X86] vec_fabs.ll - add SSE test coverage

Author: Simon Pilgrim Date: 2023-11-30T10:07:00Z New Revision: abc60e9808820c3f6614e6815909d43ed085460e URL: https://github.com/llvm/llvm-project/commit/abc60e9808820c3f6614e6815909d43ed085460e DIFF: https://github.com/llvm/llvm-project/commit/abc60e9808820c3f6614e6815909d43ed085460e.diff LOG:

[llvm-branch-commits] [llvm] [llvm-exegesis] Add additional validation counters (PR #76788)

@@ -121,7 +121,12 @@ def HaswellPfmCounters : ProcPfmCounters { PfmIssueCounter<"HWPort7", "uops_executed_port:port_7"> ]; let ValidationCounters = [ -PfmValidationCounter +PfmValidationCounter, +PfmValidationCounter, +PfmValidationCounter, +PfmValid

[llvm-branch-commits] [llvm] [llvm-exegesis] Add additional validation counters (PR #76788)

RKSimon wrote: Thanks, no more comments from me - but a exegesis owner should review the rest https://github.com/llvm/llvm-project/pull/76788 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman

[llvm-branch-commits] [clang] Backport "[Clang][CodeGen] Fix type for atomic float incdec operators (#107075)" (PR #107184)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/107184 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [compiler-rt] [llvm] [X86] AMD Zen 5 Initial enablement (PR #108816)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/108816 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] Backport "[Clang][CodeGen] Fix type for atomic float incdec operators (#107075)" (PR #107184)

https://github.com/RKSimon approved this pull request. https://github.com/llvm/llvm-project/pull/107184 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [compiler-rt] [llvm] [X86] AMD Zen 5 Initial enablement (PR #108816)

RKSimon wrote: LLVM Release Notes: ``` Changes to the X86 Backend -mcpu=znver5 is now supported. ``` Clang Release Notes: ``` X86 Support -march=znver5 is now supported ``` @ganeshgit Are you happy with this? https://github.com/llvm/llvm-project/pull/108816 __

[llvm-branch-commits] [llvm] 344afa8 - [Support] TrigramIndex::insert - pass std::String argument by const reference. NFCI.

Author: Simon Pilgrim Date: 2021-01-23T11:04:00Z New Revision: 344afa853fcfcc085cb5c957b4a07c7ea013bb1b URL: https://github.com/llvm/llvm-project/commit/344afa853fcfcc085cb5c957b4a07c7ea013bb1b DIFF: https://github.com/llvm/llvm-project/commit/344afa853fcfcc085cb5c957b4a07c7ea013bb1b.diff LOG:

[llvm-branch-commits] [llvm] 9641bd0 - [TableGen] RuleMatcher::defineComplexSubOperand avoid std::string copy. NFCI.

Author: Simon Pilgrim Date: 2021-01-25T11:35:44Z New Revision: 9641bd0f87dda34c09c606358bb0cb08a641a4f6 URL: https://github.com/llvm/llvm-project/commit/9641bd0f87dda34c09c606358bb0cb08a641a4f6 DIFF: https://github.com/llvm/llvm-project/commit/9641bd0f87dda34c09c606358bb0cb08a641a4f6.diff LOG:

[llvm-branch-commits] [llvm] f461e35 - [X86][AVX] combineX86ShuffleChain - avoid bitcasts around insert_subvector() shuffle patterns.

Author: Simon Pilgrim Date: 2021-01-25T11:35:45Z New Revision: f461e35cbafed593e637305e2a76822dfb7ca6c7 URL: https://github.com/llvm/llvm-project/commit/f461e35cbafed593e637305e2a76822dfb7ca6c7 DIFF: https://github.com/llvm/llvm-project/commit/f461e35cbafed593e637305e2a76822dfb7ca6c7.diff LOG:

[llvm-branch-commits] [llvm] 1b780cf - [X86][AVX] LowerTRUNCATE - avoid bitcasts around extract_subvectors.

Author: Simon Pilgrim Date: 2021-01-25T12:10:36Z New Revision: 1b780cf32e3eea193aa2255b852a7ef164ea00a5 URL: https://github.com/llvm/llvm-project/commit/1b780cf32e3eea193aa2255b852a7ef164ea00a5 DIFF: https://github.com/llvm/llvm-project/commit/1b780cf32e3eea193aa2255b852a7ef164ea00a5.diff LOG:

[llvm-branch-commits] [llvm] 821a51a - [X86][AVX] combineX86ShuffleChainWithExtract - widen to at least original root size. NFCI.

Author: Simon Pilgrim Date: 2021-01-25T13:45:37Z New Revision: 821a51a9cacfac7da8b34ccc0498d316471f1dbc URL: https://github.com/llvm/llvm-project/commit/821a51a9cacfac7da8b34ccc0498d316471f1dbc DIFF: https://github.com/llvm/llvm-project/commit/821a51a9cacfac7da8b34ccc0498d316471f1dbc.diff LOG:

[llvm-branch-commits] [llvm] 13f2aee - [X86][AVX] Generalize vperm2f128/vperm2i128 patterns to support all legal 256-bit vector types

Author: Simon Pilgrim Date: 2021-01-25T15:35:36Z New Revision: 13f2aee7831c9bec17006a6d401008df541a121d URL: https://github.com/llvm/llvm-project/commit/13f2aee7831c9bec17006a6d401008df541a121d DIFF: https://github.com/llvm/llvm-project/commit/13f2aee7831c9bec17006a6d401008df541a121d.diff LOG:

[llvm-branch-commits] [llvm] 827d0c5 - [X86] combineToExtendBoolVectorInReg - use explicit arguments. NFC.

Author: Simon Pilgrim Date: 2022-02-11T16:40:29Z New Revision: 827d0c51be93c4b0bcbe43a6cbbcc0e65a8b9f58 URL: https://github.com/llvm/llvm-project/commit/827d0c51be93c4b0bcbe43a6cbbcc0e65a8b9f58 DIFF: https://github.com/llvm/llvm-project/commit/827d0c51be93c4b0bcbe43a6cbbcc0e65a8b9f58.diff LOG:

[llvm-branch-commits] [llvm] 48e1434 - [X86] Move combineToExtendBoolVectorInReg before the select combines. NFC.

Author: Simon Pilgrim Date: 2022-02-11T16:51:46Z New Revision: 48e1434a0a77852f58c1617123f228f1069ba775 URL: https://github.com/llvm/llvm-project/commit/48e1434a0a77852f58c1617123f228f1069ba775 DIFF: https://github.com/llvm/llvm-project/commit/48e1434a0a77852f58c1617123f228f1069ba775.diff LOG:

[llvm-branch-commits] [llvm-branch] r282753 - [3.9.1] Merging r280837 [X86] Don't reduce the width of vector mul if the target doesn't support SSE2.

Author: rksimon Date: Thu Sep 29 14:16:52 2016 New Revision: 282753 URL: http://llvm.org/viewvc/llvm-project?rev=282753&view=rev Log: [3.9.1] Merging r280837 [X86] Don't reduce the width of vector mul if the target doesn't support SSE2. The patch is to fix PR30298, which is caused by rL272694. T

[llvm-branch-commits] [llvm-branch] r286248 - [3.9.1] Merging r282613 - [X86][AVX] Add test showing that VBROADCAST loads don't correctly respect dependencies

Author: rksimon Date: Tue Nov 8 10:45:26 2016 New Revision: 286248 URL: http://llvm.org/viewvc/llvm-project?rev=286248&view=rev Log: [3.9.1] Merging r282613 - [X86][AVX] Add test showing that VBROADCAST loads don't correctly respect dependencies As discussed in PR30596, this is a preliminary te

[llvm-branch-commits] [llvm-branch] r286251 - [3.9.1] Merging r283070 - [X86][AVX] Ensure broadcast loads respect dependencies

Author: rksimon Date: Tue Nov 8 11:01:05 2016 New Revision: 286251 URL: http://llvm.org/viewvc/llvm-project?rev=286251&view=rev Log: [3.9.1] Merging r283070 - [X86][AVX] Ensure broadcast loads respect dependencies To allow broadcast loads of a non-zero'th vector element, lowerVectorShuffleAsBro

[llvm-branch-commits] [llvm] 85aaa3e - [X86] Regenerate sdiv_fix_sat.ll + udiv_fix_sat.ll tests

Author: Simon Pilgrim Date: 2021-01-12T17:25:30Z New Revision: 85aaa3e310c23ec8a375b7a2e2fceee5a72441ef URL: https://github.com/llvm/llvm-project/commit/85aaa3e310c23ec8a375b7a2e2fceee5a72441ef DIFF: https://github.com/llvm/llvm-project/commit/85aaa3e310c23ec8a375b7a2e2fceee5a72441ef.diff LOG:

[llvm-branch-commits] [llvm] a4931d4 - [AMDGPU] Regenerate umax crash test

Author: Simon Pilgrim Date: 2021-01-12T18:02:15Z New Revision: a4931d4fe38d6feef53f97f3dcc7792bfcb06c84 URL: https://github.com/llvm/llvm-project/commit/a4931d4fe38d6feef53f97f3dcc7792bfcb06c84 DIFF: https://github.com/llvm/llvm-project/commit/a4931d4fe38d6feef53f97f3dcc7792bfcb06c84.diff LOG:

[llvm-branch-commits] [llvm] 0f59d09 - [X86][AVX] combineVectorSignBitsTruncation - limit AVX512 truncations to 128-bits (PR48727)

Author: Simon Pilgrim Date: 2021-01-13T10:38:23Z New Revision: 0f59d099571d3d803b54e2ce06aa94babb9b26db URL: https://github.com/llvm/llvm-project/commit/0f59d099571d3d803b54e2ce06aa94babb9b26db DIFF: https://github.com/llvm/llvm-project/commit/0f59d099571d3d803b54e2ce06aa94babb9b26db.diff LOG:

[llvm-branch-commits] [llvm] 0a0ee7f - [X86] canonicalizeShuffleMaskWithHorizOp - minor refactor to support multiple src ops. NFCI.

Author: Simon Pilgrim Date: 2021-01-13T13:59:56Z New Revision: 0a0ee7f5a5af0f5dae65452f649ab665e787e7d6 URL: https://github.com/llvm/llvm-project/commit/0a0ee7f5a5af0f5dae65452f649ab665e787e7d6 DIFF: https://github.com/llvm/llvm-project/commit/0a0ee7f5a5af0f5dae65452f649ab665e787e7d6.diff LOG:

[llvm-branch-commits] [llvm] cbbfc82 - [X86][SSE] canonicalizeShuffleMaskWithHorizOp - simplify shuffle(HOP(HOP(X, Y), HOP(Z, W))) style chains.

Author: Simon Pilgrim Date: 2021-01-13T17:19:40Z New Revision: cbbfc8258615bc971a54c6287abe33c4215d2eac URL: https://github.com/llvm/llvm-project/commit/cbbfc8258615bc971a54c6287abe33c4215d2eac DIFF: https://github.com/llvm/llvm-project/commit/cbbfc8258615bc971a54c6287abe33c4215d2eac.diff LOG:

[llvm-branch-commits] [llvm] efb6e45 - [X86][AVX] Add test for another 'reverse HADD' pattern mentioned in PR41813

Author: Simon Pilgrim Date: 2021-01-13T17:19:41Z New Revision: efb6e45d2be8e3e0843bdc4c2766e6910083c08e URL: https://github.com/llvm/llvm-project/commit/efb6e45d2be8e3e0843bdc4c2766e6910083c08e DIFF: https://github.com/llvm/llvm-project/commit/efb6e45d2be8e3e0843bdc4c2766e6910083c08e.diff LOG:

[llvm-branch-commits] [llvm] 993c488 - [DAG] visitVECTOR_SHUFFLE - use all_of to check for all-undef shuffle mask. NFCI.

Author: Simon Pilgrim Date: 2021-01-13T17:19:41Z New Revision: 993c488ed2b347011d9d71990af38a82aaf5bdf5 URL: https://github.com/llvm/llvm-project/commit/993c488ed2b347011d9d71990af38a82aaf5bdf5 DIFF: https://github.com/llvm/llvm-project/commit/993c488ed2b347011d9d71990af38a82aaf5bdf5.diff LOG:

[llvm-branch-commits] [llvm] af8d27a - [DAG] visitVECTOR_SHUFFLE - pull out shuffle merging code into lambda helper. NFCI.

Author: Simon Pilgrim Date: 2021-01-14T11:05:19Z New Revision: af8d27a7a8266b89916b5e4db2b2fd97eb7d84e5 URL: https://github.com/llvm/llvm-project/commit/af8d27a7a8266b89916b5e4db2b2fd97eb7d84e5 DIFF: https://github.com/llvm/llvm-project/commit/af8d27a7a8266b89916b5e4db2b2fd97eb7d84e5.diff LOG:

[llvm-branch-commits] [llvm] 8f1d7f3 - [X86] Improve sum-of-reductions v4f32 test coverage

Author: Simon Pilgrim Date: 2021-01-14T11:05:19Z New Revision: 8f1d7f3753ca132b310bbb0e62c394cfa75daee5 URL: https://github.com/llvm/llvm-project/commit/8f1d7f3753ca132b310bbb0e62c394cfa75daee5 DIFF: https://github.com/llvm/llvm-project/commit/8f1d7f3753ca132b310bbb0e62c394cfa75daee5.diff LOG:

[llvm-branch-commits] [llvm] 7c30c05 - [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - reset shuffle ops and reorder early-out and second op matching. NFCI.

Author: Simon Pilgrim Date: 2021-01-14T11:55:20Z New Revision: 7c30c05ff71d062f0b8a05b7c3c12ede2c285371 URL: https://github.com/llvm/llvm-project/commit/7c30c05ff71d062f0b8a05b7c3c12ede2c285371 DIFF: https://github.com/llvm/llvm-project/commit/7c30c05ff71d062f0b8a05b7c3c12ede2c285371.diff LOG:

[llvm-branch-commits] [llvm] e8622d2 - [Support] Add KnownBits::sextInReg exhaustive tests

Author: Simon Pilgrim Date: 2021-01-14T14:27:45Z New Revision: e8622d27c0e3020177ff47ad57dd1e5371feb9cf URL: https://github.com/llvm/llvm-project/commit/e8622d27c0e3020177ff47ad57dd1e5371feb9cf DIFF: https://github.com/llvm/llvm-project/commit/e8622d27c0e3020177ff47ad57dd1e5371feb9cf.diff LOG:

[llvm-branch-commits] [llvm] 0b46f19 - [Support] Ensure KnownBits::sextInReg can handle the src == dst sext-in-reg case.

Author: Simon Pilgrim Date: 2021-01-14T14:50:21Z New Revision: 0b46f19a9ecd6215cffb51d19f2403c18b0226f5 URL: https://github.com/llvm/llvm-project/commit/0b46f19a9ecd6215cffb51d19f2403c18b0226f5 DIFF: https://github.com/llvm/llvm-project/commit/0b46f19a9ecd6215cffb51d19f2403c18b0226f5.diff LOG:

[llvm-branch-commits] [llvm] c0939fd - [Support] Simplify KnownBits::sextInReg implementation.

Author: Simon Pilgrim Date: 2021-01-14T15:14:32Z New Revision: c0939fddf80c16829502186e2e5b78f77696310a URL: https://github.com/llvm/llvm-project/commit/c0939fddf80c16829502186e2e5b78f77696310a DIFF: https://github.com/llvm/llvm-project/commit/c0939fddf80c16829502186e2e5b78f77696310a.diff LOG:

[llvm-branch-commits] [llvm] 0a59647 - [SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds

Author: Simon Pilgrim Date: 2021-01-14T15:46:27Z New Revision: 0a59647ee407524e6468cc5be4ba288861aa700d URL: https://github.com/llvm/llvm-project/commit/0a59647ee407524e6468cc5be4ba288861aa700d DIFF: https://github.com/llvm/llvm-project/commit/0a59647ee407524e6468cc5be4ba288861aa700d.diff LOG:

[llvm-branch-commits] [llvm] d0dbb04 - [Support] Remove redundant sign bit tests from KnownBits::getSignedMinValue/getSignedMaxValue

Author: Simon Pilgrim Date: 2021-01-14T15:46:26Z New Revision: d0dbb0468c26bafa88e7340781fb3a0a79379470 URL: https://github.com/llvm/llvm-project/commit/d0dbb0468c26bafa88e7340781fb3a0a79379470 DIFF: https://github.com/llvm/llvm-project/commit/d0dbb0468c26bafa88e7340781fb3a0a79379470.diff LOG:

[llvm-branch-commits] [llvm] b99782c - [X86][AVX] Adjust unsigned saturation downconvert negative test

Author: Simon Pilgrim Date: 2021-01-14T17:51:23Z New Revision: b99782cf7850a481fa36fd95ae04923739e0da6d URL: https://github.com/llvm/llvm-project/commit/b99782cf7850a481fa36fd95ae04923739e0da6d DIFF: https://github.com/llvm/llvm-project/commit/b99782cf7850a481fa36fd95ae04923739e0da6d.diff LOG:

[llvm-branch-commits] [llvm] 1dfd5c9 - [X86][AVX] combineHorizOpWithShuffle - support target shuffles in HOP(SHUFFLE(X, Y), SHUFFLE(X, Y)) -> SHUFFLE(HOP(X, Y))

Author: Simon Pilgrim Date: 2021-01-15T13:55:30Z New Revision: 1dfd5c9ad8cf677fb4c9c3ccf39d7b1f20c397d3 URL: https://github.com/llvm/llvm-project/commit/1dfd5c9ad8cf677fb4c9c3ccf39d7b1f20c397d3 DIFF: https://github.com/llvm/llvm-project/commit/1dfd5c9ad8cf677fb4c9c3ccf39d7b1f20c397d3.diff LOG:

[llvm-branch-commits] [llvm] 5183a13 - [X86] Add umin knownbits/demandedbits ult test for D94532

Author: Simon Pilgrim Date: 2021-01-15T14:42:55Z New Revision: 5183a13d37825f93d92c23c257dbb1c994098bdc URL: https://github.com/llvm/llvm-project/commit/5183a13d37825f93d92c23c257dbb1c994098bdc DIFF: https://github.com/llvm/llvm-project/commit/5183a13d37825f93d92c23c257dbb1c994098bdc.diff LOG:

[llvm-branch-commits] [llvm] 46aa3c6 - [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - improve shuffle(shuffle(x, y), shuffle(x, y)) merging

Author: Simon Pilgrim Date: 2021-01-15T15:08:31Z New Revision: 46aa3c6c331c20b8a4c358488fefab96f944e814 URL: https://github.com/llvm/llvm-project/commit/46aa3c6c331c20b8a4c358488fefab96f944e814 DIFF: https://github.com/llvm/llvm-project/commit/46aa3c6c331c20b8a4c358488fefab96f944e814.diff LOG:

[llvm-branch-commits] [llvm] be69e66 - [X86][SSE] Attempt to fold shuffle(binop(), binop()) -> binop(shuffle(), shuffle())

Author: Simon Pilgrim Date: 2021-01-15T16:25:25Z New Revision: be69e66b1cd826f499566e1c3dadbf04e872baa0 URL: https://github.com/llvm/llvm-project/commit/be69e66b1cd826f499566e1c3dadbf04e872baa0 DIFF: https://github.com/llvm/llvm-project/commit/be69e66b1cd826f499566e1c3dadbf04e872baa0.diff LOG:

[llvm-branch-commits] [llvm] 770d1e0 - [X86][SSE] isHorizontalBinOp - reuse any existing horizontal ops.

Author: Simon Pilgrim Date: 2021-01-18T10:14:45Z New Revision: 770d1e0a8828010a7c95de4596e24d54ed2527c3 URL: https://github.com/llvm/llvm-project/commit/770d1e0a8828010a7c95de4596e24d54ed2527c3 DIFF: https://github.com/llvm/llvm-project/commit/770d1e0a8828010a7c95de4596e24d54ed2527c3.diff LOG:

[llvm-branch-commits] [llvm] 207f329 - [DAG] SimplifyDemandedBits - use KnownBits comparisons to remove ISD::UMIN/UMAX ops

Author: Simon Pilgrim Date: 2021-01-18T10:29:23Z New Revision: 207f32948b2408bebd5a523695f6f7c08049db74 URL: https://github.com/llvm/llvm-project/commit/207f32948b2408bebd5a523695f6f7c08049db74 DIFF: https://github.com/llvm/llvm-project/commit/207f32948b2408bebd5a523695f6f7c08049db74.diff LOG:

[llvm-branch-commits] [llvm] ce06475 - [X86][AVX] IsElementEquivalent - add matchShuffleWithUNPCK + VBROADCAST/VBROADCAST_LOAD handling

Author: Simon Pilgrim Date: 2021-01-18T15:55:00Z New Revision: ce06475da94f1040d17d46d471dd48478576a76f URL: https://github.com/llvm/llvm-project/commit/ce06475da94f1040d17d46d471dd48478576a76f DIFF: https://github.com/llvm/llvm-project/commit/ce06475da94f1040d17d46d471dd48478576a76f.diff LOG:

[llvm-branch-commits] [llvm] 5626adc - [X86][SSE] combineVectorSignBitsTruncation - fold trunc(srl(x, c)) -> packss(sra(x, c))

Author: Simon Pilgrim Date: 2021-01-19T11:04:13Z New Revision: 5626adcd6bbaadd12fe5bf15cd2d39ece2e5c406 URL: https://github.com/llvm/llvm-project/commit/5626adcd6bbaadd12fe5bf15cd2d39ece2e5c406 DIFF: https://github.com/llvm/llvm-project/commit/5626adcd6bbaadd12fe5bf15cd2d39ece2e5c406.diff LOG:

[llvm-branch-commits] [llvm] 2988f94 - [X86] Regenerate fmin/fmax reduction tests

Author: Simon Pilgrim Date: 2021-01-19T14:28:44Z New Revision: 2988f940d861f0fa76bc5b749772f2b9239d5a1b URL: https://github.com/llvm/llvm-project/commit/2988f940d861f0fa76bc5b749772f2b9239d5a1b DIFF: https://github.com/llvm/llvm-project/commit/2988f940d861f0fa76bc5b749772f2b9239d5a1b.diff LOG:

[llvm-branch-commits] [llvm] 19d0284 - [X86][AVX] Fold extract_subvector(VSRLI/VSHLI(x, 32)) -> VSRLI/VSHLI(extract_subvector(x), 32)

Author: Simon Pilgrim Date: 2021-01-20T14:34:54Z New Revision: 19d02842ee56089b9208875ce4582e113e08fb6d URL: https://github.com/llvm/llvm-project/commit/19d02842ee56089b9208875ce4582e113e08fb6d DIFF: https://github.com/llvm/llvm-project/commit/19d02842ee56089b9208875ce4582e113e08fb6d.diff LOG:

[llvm-branch-commits] [llvm] cad4275 - [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE

Author: Simon Pilgrim Date: 2021-01-20T15:39:58Z New Revision: cad4275d697c601761e0819863f487def73c67f8 URL: https://github.com/llvm/llvm-project/commit/cad4275d697c601761e0819863f487def73c67f8 DIFF: https://github.com/llvm/llvm-project/commit/cad4275d697c601761e0819863f487def73c67f8.diff LOG:

[llvm-branch-commits] [llvm] b8b5e87 - [X86][AVX] Handle vperm2x128 shuffling of a subvector splat.

Author: Simon Pilgrim Date: 2021-01-20T18:16:33Z New Revision: b8b5e87e6b8102d77e4e6beccf4e0f0237acc897 URL: https://github.com/llvm/llvm-project/commit/b8b5e87e6b8102d77e4e6beccf4e0f0237acc897 DIFF: https://github.com/llvm/llvm-project/commit/b8b5e87e6b8102d77e4e6beccf4e0f0237acc897.diff LOG:

[llvm-branch-commits] [llvm] 86021d9 - [X86] Avoid a std::string copy by replacing auto with const auto&. NFC.

Author: Simon Pilgrim Date: 2021-01-21T11:04:07Z New Revision: 86021d98d3f8b27f7956cee04f11505c2e836e81 URL: https://github.com/llvm/llvm-project/commit/86021d98d3f8b27f7956cee04f11505c2e836e81 DIFF: https://github.com/llvm/llvm-project/commit/86021d98d3f8b27f7956cee04f11505c2e836e81.diff LOG:

[llvm-branch-commits] [llvm] bc9ab9a - [DAG] CombineToPreIndexedLoadStore - use const APInt& for getAPIntValue(). NFCI.

Author: Simon Pilgrim Date: 2021-01-21T11:04:09Z New Revision: bc9ab9a5cd6bafc5e1293f3d5d51638f8f5cd26c URL: https://github.com/llvm/llvm-project/commit/bc9ab9a5cd6bafc5e1293f3d5d51638f8f5cd26c DIFF: https://github.com/llvm/llvm-project/commit/bc9ab9a5cd6bafc5e1293f3d5d51638f8f5cd26c.diff LOG:

[llvm-branch-commits] [llvm] 935bacd - [DAG] SimplifyDemandedBits - correctly adjust truncated shift amount type

Author: Simon Pilgrim Date: 2021-01-21T12:38:36Z New Revision: 935bacd3a7244f04b7f39818e3fc589529474d13 URL: https://github.com/llvm/llvm-project/commit/935bacd3a7244f04b7f39818e3fc589529474d13 DIFF: https://github.com/llvm/llvm-project/commit/935bacd3a7244f04b7f39818e3fc589529474d13.diff LOG:

[llvm-branch-commits] [llvm] 0ca81b9 - [X86][SSE] Add uitofp(trunc(and(lshr(x, c)))) vector test

Author: Simon Pilgrim Date: 2021-01-21T12:38:36Z New Revision: 0ca81b90d19d395c4891b7507cec0f063dd26d22 URL: https://github.com/llvm/llvm-project/commit/0ca81b90d19d395c4891b7507cec0f063dd26d22 DIFF: https://github.com/llvm/llvm-project/commit/0ca81b90d19d395c4891b7507cec0f063dd26d22.diff LOG:

[llvm-branch-commits] [llvm] 69bc099 - [DAGCombiner] Enable SimplifyDemandedBits vector support for TRUNCATE (REAPPLIED).

Author: Simon Pilgrim Date: 2021-01-21T13:01:34Z New Revision: 69bc0990a9181e6eb86228276d2f59435a7fae67 URL: https://github.com/llvm/llvm-project/commit/69bc0990a9181e6eb86228276d2f59435a7fae67 DIFF: https://github.com/llvm/llvm-project/commit/69bc0990a9181e6eb86228276d2f59435a7fae67.diff LOG:

[llvm-branch-commits] [llvm] 481659c - [X86][SSE] Add v16i8 02_20_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu_uu shuffle test

Author: Simon Pilgrim Date: 2021-01-22T10:05:22Z New Revision: 481659c55c4ec1e133bec82a909e9e6baee70a28 URL: https://github.com/llvm/llvm-project/commit/481659c55c4ec1e133bec82a909e9e6baee70a28 DIFF: https://github.com/llvm/llvm-project/commit/481659c55c4ec1e133bec82a909e9e6baee70a28.diff LOG:

[llvm-branch-commits] [llvm] 636b877 - [X86][SSE] Add PR48823 HSUB test case

Author: Simon Pilgrim Date: 2021-01-22T10:05:22Z New Revision: 636b87785c1de64134254b688d30ab1248b16ed2 URL: https://github.com/llvm/llvm-project/commit/636b87785c1de64134254b688d30ab1248b16ed2 DIFF: https://github.com/llvm/llvm-project/commit/636b87785c1de64134254b688d30ab1248b16ed2.diff LOG:

[llvm-branch-commits] [llvm] ffe72f9 - [X86][SSE] Don't fold shuffle(binop(), binop()) -> binop(shuffle(), shuffle()) if the shuffle are splats

Author: Simon Pilgrim Date: 2021-01-22T11:31:38Z New Revision: ffe72f987f4866c46c18174cdb750dea88bedba3 URL: https://github.com/llvm/llvm-project/commit/ffe72f987f4866c46c18174cdb750dea88bedba3 DIFF: https://github.com/llvm/llvm-project/commit/ffe72f987f4866c46c18174cdb750dea88bedba3.diff LOG:

[llvm-branch-commits] [llvm] 5dbe5d2 - [DAG] Commute shuffle(splat(A, u), shuffle(C, D)) -> shuffle'(shuffle(C, D), splat(A, u))

Author: Simon Pilgrim Date: 2021-01-22T11:43:18Z New Revision: 5dbe5d2c91209db9830d5b17093c408f22a7b471 URL: https://github.com/llvm/llvm-project/commit/5dbe5d2c91209db9830d5b17093c408f22a7b471 DIFF: https://github.com/llvm/llvm-project/commit/5dbe5d2c91209db9830d5b17093c408f22a7b471.diff LOG:

[llvm-branch-commits] [llvm] b1166e1 - [X86][AVX] combineX86ShufflesRecursively - attempt to constant fold before widening shuffle inputs

Author: Simon Pilgrim Date: 2021-01-22T13:19:35Z New Revision: b1166e1317c54e9cfbb28b280af12313cf325a86 URL: https://github.com/llvm/llvm-project/commit/b1166e1317c54e9cfbb28b280af12313cf325a86 DIFF: https://github.com/llvm/llvm-project/commit/b1166e1317c54e9cfbb28b280af12313cf325a86.diff LOG:

[llvm-branch-commits] [llvm] 4846f6a - [X86][AVX] combineTargetShuffle - simplify the X86ISD::VPERM2X128 subvector matching

Author: Simon Pilgrim Date: 2021-01-22T15:47:22Z New Revision: 4846f6ab815c34f6ffbc8d4ecde891d917bf2157 URL: https://github.com/llvm/llvm-project/commit/4846f6ab815c34f6ffbc8d4ecde891d917bf2157 DIFF: https://github.com/llvm/llvm-project/commit/4846f6ab815c34f6ffbc8d4ecde891d917bf2157.diff LOG:

[llvm-branch-commits] [llvm] c33d36e - [X86][AVX] canonicalizeLaneShuffleWithRepeatedOps - handle unary vperm2x128(permute/shift(x, c), undef) cases

Author: Simon Pilgrim Date: 2021-01-22T15:47:23Z New Revision: c33d36e0667e7fff186243ac7a3a9cd63e797438 URL: https://github.com/llvm/llvm-project/commit/c33d36e0667e7fff186243ac7a3a9cd63e797438 DIFF: https://github.com/llvm/llvm-project/commit/c33d36e0667e7fff186243ac7a3a9cd63e797438.diff LOG:

[llvm-branch-commits] [llvm] bd122f6 - [X86][AVX] canonicalizeLaneShuffleWithRepeatedOps - handle vperm2x128(movddup(x), movddup(y)) cases

Author: Simon Pilgrim Date: 2021-01-22T16:05:19Z New Revision: bd122f6d217862b4631ac118c58f62a7dec16a02 URL: https://github.com/llvm/llvm-project/commit/bd122f6d217862b4631ac118c58f62a7dec16a02 DIFF: https://github.com/llvm/llvm-project/commit/bd122f6d217862b4631ac118c58f62a7dec16a02.diff LOG:

[llvm-branch-commits] [llvm] 23b4198 - [Support] Add KnownBits::icmp helpers.

Author: Simon Pilgrim Date: 2021-01-04T12:46:27Z New Revision: 23b41986527a3fc5615480a8f7a0b0debd5fcef4 URL: https://github.com/llvm/llvm-project/commit/23b41986527a3fc5615480a8f7a0b0debd5fcef4 DIFF: https://github.com/llvm/llvm-project/commit/23b41986527a3fc5615480a8f7a0b0debd5fcef4.diff LOG:

[llvm-branch-commits] [llvm] 4d7cb6d - [Sparc] SparcMCExpr::printVariantKind - fix Wcovered-switch-default gcc warning. NFCI.

Author: Simon Pilgrim Date: 2021-01-04T14:08:44Z New Revision: 4d7cb6da9fcf980a8ddaa09ffa2dcab1525a66db URL: https://github.com/llvm/llvm-project/commit/4d7cb6da9fcf980a8ddaa09ffa2dcab1525a66db DIFF: https://github.com/llvm/llvm-project/commit/4d7cb6da9fcf980a8ddaa09ffa2dcab1525a66db.diff LOG:

[llvm-branch-commits] [clang] 9f8c0d1 - DeclCXX - Fix getAs<> null-dereference static analyzer warnings. NFCI.

Author: Simon Pilgrim Date: 2021-01-04T15:12:55Z New Revision: 9f8c0d15c7f706a124ba29e8f40dc1937cd5bd49 URL: https://github.com/llvm/llvm-project/commit/9f8c0d15c7f706a124ba29e8f40dc1937cd5bd49 DIFF: https://github.com/llvm/llvm-project/commit/9f8c0d15c7f706a124ba29e8f40dc1937cd5bd49.diff LOG:

[llvm-branch-commits] [llvm] e9f401d - [IR] CallBase::getBundleOpInfoForOperand - ensure Current iterator is defined. NFCI.

Author: Simon Pilgrim Date: 2021-01-04T15:30:15Z New Revision: e9f401d8a261e747f5dfc9e297f12ab26e56893d URL: https://github.com/llvm/llvm-project/commit/e9f401d8a261e747f5dfc9e297f12ab26e56893d DIFF: https://github.com/llvm/llvm-project/commit/e9f401d8a261e747f5dfc9e297f12ab26e56893d.diff LOG:

[llvm-branch-commits] [llvm] f7463ca - [ProfileData] GCOVFile::readGCNO - silence undefined pointer warning. NFCI.

Author: Simon Pilgrim Date: 2021-01-04T16:50:05Z New Revision: f7463ca3cc5ba8455c4611c5afa79c48d8a79326 URL: https://github.com/llvm/llvm-project/commit/f7463ca3cc5ba8455c4611c5afa79c48d8a79326 DIFF: https://github.com/llvm/llvm-project/commit/f7463ca3cc5ba8455c4611c5afa79c48d8a79326.diff LOG:

[llvm-branch-commits] [clang] 6725860 - Sema::BuildCallExpr - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.

Author: Simon Pilgrim Date: 2021-01-05T09:34:00Z New Revision: 6725860d21a03741d6c3331ab0560416bb19e068 URL: https://github.com/llvm/llvm-project/commit/6725860d21a03741d6c3331ab0560416bb19e068 DIFF: https://github.com/llvm/llvm-project/commit/6725860d21a03741d6c3331ab0560416bb19e068.diff LOG:

[llvm-branch-commits] [llvm] 52e4489 - SystemZTargetLowering::lowerDYNAMIC_STACKALLOC - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.

Author: Simon Pilgrim Date: 2021-01-05T09:34:01Z New Revision: 52e448974b2ec826c8af429c370c4d6e79ce5747 URL: https://github.com/llvm/llvm-project/commit/52e448974b2ec826c8af429c370c4d6e79ce5747 DIFF: https://github.com/llvm/llvm-project/commit/52e448974b2ec826c8af429c370c4d6e79ce5747.diff LOG:

[llvm-branch-commits] [llvm] 84d5768 - MemProfiler::insertDynamicShadowAtFunctionEntry - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.

Author: Simon Pilgrim Date: 2021-01-05T09:34:01Z New Revision: 84d5768d97635602225f5056da96b058e588b2f5 URL: https://github.com/llvm/llvm-project/commit/84d5768d97635602225f5056da96b058e588b2f5 DIFF: https://github.com/llvm/llvm-project/commit/84d5768d97635602225f5056da96b058e588b2f5.diff LOG:

[llvm-branch-commits] [llvm] 7a97eeb - [Coroutines] checkAsyncFuncPointer - use cast<> instead of dyn_cast<> for dereferenced pointer. NFCI.

Author: Simon Pilgrim Date: 2021-01-05T10:31:45Z New Revision: 7a97eeb197a8023acbb800d40b3bb852fc2f5d60 URL: https://github.com/llvm/llvm-project/commit/7a97eeb197a8023acbb800d40b3bb852fc2f5d60 DIFF: https://github.com/llvm/llvm-project/commit/7a97eeb197a8023acbb800d40b3bb852fc2f5d60.diff LOG:

[llvm-branch-commits] [llvm] a000366 - [SimplifyIndVar] createWideIV - make WideIVInfo arg a const ref. NFCI.

Author: Simon Pilgrim Date: 2021-01-05T10:31:45Z New Revision: a000366d0502b35fc0d3b113ace7f0e3bbdc08cd URL: https://github.com/llvm/llvm-project/commit/a000366d0502b35fc0d3b113ace7f0e3bbdc08cd DIFF: https://github.com/llvm/llvm-project/commit/a000366d0502b35fc0d3b113ace7f0e3bbdc08cd.diff LOG:

[llvm-branch-commits] [llvm] 313d982 - [IR] Add ConstantInt::getBool helpers to wrap getTrue/getFalse.

Author: Simon Pilgrim Date: 2021-01-05T11:01:10Z New Revision: 313d982df65a7a8f1da2da5f0e03e6b6e301ce3c URL: https://github.com/llvm/llvm-project/commit/313d982df65a7a8f1da2da5f0e03e6b6e301ce3c DIFF: https://github.com/llvm/llvm-project/commit/313d982df65a7a8f1da2da5f0e03e6b6e301ce3c.diff LOG:

[llvm-branch-commits] [llvm] dc74d7e - [X86] getMemoryOpCost - use dyn_cast_or_null. NFCI.

Author: Simon Pilgrim Date: 2021-01-05T13:23:09Z New Revision: dc74d7ed1f651aa61d15b4eaaa32200df1f38d37 URL: https://github.com/llvm/llvm-project/commit/dc74d7ed1f651aa61d15b4eaaa32200df1f38d37 DIFF: https://github.com/llvm/llvm-project/commit/dc74d7ed1f651aa61d15b4eaaa32200df1f38d37.diff LOG:

[llvm-branch-commits] [llvm] 73a44f4 - [X86][AVX] combineVectorSignBitsTruncation - use PACKSS/PACKUS in more AVX cases

Author: Simon Pilgrim Date: 2021-01-05T15:01:45Z New Revision: 73a44f437bf19ecf2c865e6c8b9b8a2e4a811960 URL: https://github.com/llvm/llvm-project/commit/73a44f437bf19ecf2c865e6c8b9b8a2e4a811960 DIFF: https://github.com/llvm/llvm-project/commit/73a44f437bf19ecf2c865e6c8b9b8a2e4a811960.diff LOG:

[llvm-branch-commits] [clang] 55488bd - CGExpr - EmitMatrixSubscriptExpr - fix getAs<> null-dereference static analyzer warning. NFCI.

Author: Simon Pilgrim Date: 2021-01-05T17:08:11Z New Revision: 55488bd3cd1a468941e26ad4cf94f2bad887fc02 URL: https://github.com/llvm/llvm-project/commit/55488bd3cd1a468941e26ad4cf94f2bad887fc02 DIFF: https://github.com/llvm/llvm-project/commit/55488bd3cd1a468941e26ad4cf94f2bad887fc02.diff LOG:

[llvm-branch-commits] [llvm] dfcb872 - [X86] Add scalar/vector test coverage for D93599

Author: Simon Pilgrim Date: 2021-01-06T11:58:27Z New Revision: dfcb872c3e82c821bb32a2dd53ab73314d38ce38 URL: https://github.com/llvm/llvm-project/commit/dfcb872c3e82c821bb32a2dd53ab73314d38ce38 DIFF: https://github.com/llvm/llvm-project/commit/dfcb872c3e82c821bb32a2dd53ab73314d38ce38.diff LOG:

[llvm-branch-commits] [llvm] 37ac4f8 - [Hexagon] Regenerate zext-v4i1.ll tests

Author: Simon Pilgrim Date: 2021-01-06T12:56:06Z New Revision: 37ac4f865fba451d969bd9b4b1e28ce296e093da URL: https://github.com/llvm/llvm-project/commit/37ac4f865fba451d969bd9b4b1e28ce296e093da DIFF: https://github.com/llvm/llvm-project/commit/37ac4f865fba451d969bd9b4b1e28ce296e093da.diff LOG:

[llvm-branch-commits] [llvm] 396dd6c - [ProfileData] Pass Twine by const reference instead of by value.

Author: Simon Pilgrim Date: 2021-01-06T14:22:03Z New Revision: 396dd6cd3d8bdcda9dcb606ad4c054560bf0649f URL: https://github.com/llvm/llvm-project/commit/396dd6cd3d8bdcda9dcb606ad4c054560bf0649f DIFF: https://github.com/llvm/llvm-project/commit/396dd6cd3d8bdcda9dcb606ad4c054560bf0649f.diff LOG:

[llvm-branch-commits] [llvm] df5c2ca - [MIPS] MipsAsmParser - Pass Twine by const reference instead of by value. NFCI.

Author: Simon Pilgrim Date: 2021-01-06T14:22:04Z New Revision: df5c2caf0fc0d59d4d2e0ce99da4aa58f204791a URL: https://github.com/llvm/llvm-project/commit/df5c2caf0fc0d59d4d2e0ce99da4aa58f204791a DIFF: https://github.com/llvm/llvm-project/commit/df5c2caf0fc0d59d4d2e0ce99da4aa58f204791a.diff LOG:

[llvm-branch-commits] [llvm] 26c486c - [TableGen] RegisterBankEmitter - Pass Twine by const reference instead of by value. NFCI.

Author: Simon Pilgrim Date: 2021-01-06T14:22:05Z New Revision: 26c486c2eb1a0f302eb60a4b959456f09adbbacb URL: https://github.com/llvm/llvm-project/commit/26c486c2eb1a0f302eb60a4b959456f09adbbacb DIFF: https://github.com/llvm/llvm-project/commit/26c486c2eb1a0f302eb60a4b959456f09adbbacb.diff LOG:

[llvm-branch-commits] [llvm] b69fe6a - [X86] Add icmp ne/eq (srl (ctlz x), log2(bw)) test coverage.

Author: Simon Pilgrim Date: 2021-01-06T15:50:29Z New Revision: b69fe6a85db43df27ebb260716d41a3e1b0d7534 URL: https://github.com/llvm/llvm-project/commit/b69fe6a85db43df27ebb260716d41a3e1b0d7534 DIFF: https://github.com/llvm/llvm-project/commit/b69fe6a85db43df27ebb260716d41a3e1b0d7534.diff LOG:

[llvm-branch-commits] [llvm] 500864f - Remove some unused includes. NFCI.

Author: Simon Pilgrim Date: 2021-01-06T15:50:29Z New Revision: 500864f928c272e8ebfd6493cb749083124bfd8b URL: https://github.com/llvm/llvm-project/commit/500864f928c272e8ebfd6493cb749083124bfd8b DIFF: https://github.com/llvm/llvm-project/commit/500864f928c272e8ebfd6493cb749083124bfd8b.diff LOG:

[llvm-branch-commits] [llvm] 1307e3f - [TargetLowering] Add icmp ne/eq (srl (ctlz x), log2(bw)) vector support.

Author: Simon Pilgrim Date: 2021-01-06T16:13:51Z New Revision: 1307e3f6c46cc3a6e6ad9cd46fc67efafcac939e URL: https://github.com/llvm/llvm-project/commit/1307e3f6c46cc3a6e6ad9cd46fc67efafcac939e DIFF: https://github.com/llvm/llvm-project/commit/1307e3f6c46cc3a6e6ad9cd46fc67efafcac939e.diff LOG:

[llvm-branch-commits] [llvm] 3f8c252 - [X86] Add commuted patterns test coverage for D93599

Author: Simon Pilgrim Date: 2021-01-06T18:03:20Z New Revision: 3f8c2520c0424860b4bd3ae7b20f8033ed09363a URL: https://github.com/llvm/llvm-project/commit/3f8c2520c0424860b4bd3ae7b20f8033ed09363a DIFF: https://github.com/llvm/llvm-project/commit/3f8c2520c0424860b4bd3ae7b20f8033ed09363a.diff LOG:

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