Rename is_private to is-private as ordered by DT policy.
The change leaves the support for the old format.
Signed-off-by: Eugeniy Paltsev
---
drivers/dma/dw/platform.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index 5bda0eb..4103f
Memory-to-memory dma transfers were disabled by default if we
used DT to cofigure DMAC.
Add is-memcpu property, so it became possible to enable
memory-to-memory transfers support via DT.
Signed-off-by: Eugeniy Paltsev
---
drivers/dma/dw/platform.c | 3 +++
1 file changed, 3 insertions(+)
diff -
Several versions of DW DMAC have multi block transfers hardware
support. Hardware support of multi block transfers is disabled
by default if we use DT to configure DMAC and software emulation
of multi block transfers used instead.
Add hw-llp property, so it is possible to enable hardware
multi bloc
It wasn't possible to enable some features like
memory-to-memory transfers or multi block transfers via DT.
It is fixed by these patches.
* Rename is_private to is-private as ordered by DT policy.
(just for cleanup) The change leaves the support for the
old format.
* Add is-memcpu property,
* Rename is_private to is-private as ordered by DT policy.
The change leaves the support for the old format.
* Add is-memcpu property, so it is possible to
enable memory-to-memory transfers support via DT.
* Add hw-llp property, so it is possible to enable
hardware multi block transfers sup
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote:
> Rename is_private to is-private as ordered by DT policy.
> The change leaves the support for the old format.
>
> Signed-off-by: Eugeniy Paltsev
> ---
> drivers/dma/dw/platform.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote:
> * Rename is_private to is-private as ordered by DT policy.
> The change leaves the support for the old format.
>
> * Add is-memcpu property, so it is possible to
> enable memory-to-memory transfers support via DT.
>
> * Add hw-llp p
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote:
> Memory-to-memory dma transfers were disabled by default if we
> used DT to cofigure DMAC.
> Add is-memcpu property, so it became possible to enable
> memory-to-memory transfers support via DT.
Fix "memcpu" to "memcpy" everywhere you use i
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote:
> Several versions of DW DMAC have multi block transfers hardware
> support. Hardware support of multi block transfers is disabled
> by default if we use DT to configure DMAC and software emulation
> of multi block transfers used instead.
>
On Wed, 2016-11-16 at 16:56 +0300, Eugeniy Paltsev wrote:
> It wasn't possible to enable some features like
> memory-to-memory transfers or multi block transfers via DT.
> It is fixed by these patches.
>
> * Rename is_private to is-private as ordered by DT policy.
> (just for cleanup) The change
Hi Andy,
On Wed, 2016-11-16 at 17:10 +0200, Andy Shevchenko wrote:
> Overall, since we are going to expose some properties to the Device
> Tree
> I would really think twice about naming. Better if we reuse something
> existing already.
>
> So, what I can see is
>
> dmacap,private
> dmacap,memcpy
On Wed, 2016-11-16 at 17:01 +, Eugeniy Paltsev wrote:
> On Wed, 2016-11-16 at 17:10 +0200, Andy Shevchenko wrote:
> > Overall, since we are going to expose some properties to the Device
> > Tree
> > I would really think twice about naming. Better if we reuse
> > something
> > existing already.
On Wed, Nov 16, 2016 at 12:08 PM, Andy Shevchenko
wrote:
> On Wed, 2016-11-16 at 17:01 +, Eugeniy Paltsev wrote:
>> On Wed, 2016-11-16 at 17:10 +0200, Andy Shevchenko wrote:
>> > Overall, since we are going to expose some properties to the Device
>> > Tree
>> > I would really think twice about
Hi Vineet,
Vineet Gupta wrote,
> In gcc 6.x cleanup, the macros got renamed.
> (Need to support the old toggle for some more time)
Applied and pushed,
thx
Waldemar
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From: Noam Camus
Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to con
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