.
Moreover, we need expand the recorded data to get more information of the crash.
small...@aliyun.com
From: Sebastian Huber
Date: 2020-09-18 00:00
To: small...@aliyun.com; devel
Subject: Re: does rtems 5.1 support create a core dump file when accessing a
invalid address or other fatal errors
Flash disk is used in our normal procedure. We use qspi interface to read and
write data from/to a flash disk in order to record our logs.
The flash disk is parted to several parts. In such case, a new part could be
allocated to save the crash data.
small...@aliyun.com
From: Sebastian Huber
Hi, all
I compile rtems 5.1 with bsp xilinx-zynqmp. The single core mode is ok.
But I can not use 2 or 3 or 4 cores of this bsp.
After analysing the source code, I found there is no code to address smp
condition. Does rtems 5.1 indeed not support smp mode for xilinx-zynqmp bsp?
small
The board is Ultra96 board with JTAG boot.
And yes, there is a bspsmp.c in rtems-5.1\bsps\arm\xilinx-zynqmp\start\
small...@aliyun.com
From: Gedare Bloom
Date: 2020-10-06 00:16
To: small...@aliyun.com
CC: devel
Subject: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp
It should
cial care to limit levels on the secondary
* are required there.
*/
arm_cp15_data_cache_invalidate_all_levels();
arm_cp15_branch_predictor_invalidate_all();
arm_cp15_tlb_invalidate();
arm_cp15_flush_prefetch_buffer();
}
small...@aliyun.com
From: Kinsey Moore
Date: 2020-10-06
a boot PROM of an ERC32 or LEON system.
small...@aliyun.com
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
coverage?
Thank you very much!
small...@aliyun.com
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
.html
file in which the instructions are listed as "NOT EXECUTED" or executed.
The main different is only assembly language is used, while the conventional
approach will list the souce code in C language.
small...@aliyun.com
From: Joel Sherrill
Date: 2020-10-22 23:49
To: small..
Thank you once again. Your reply is very very fast.
small...@aliyun.com
From: Joel Sherrill
Date: 2020-10-23 10:03
To: smallphd
CC: devel
Subject: Re: Re: rtems-5.1 source code test coverage failed
Hit send too soon
On Thu, Oct 22, 2020, 8:59 PM Joel Sherrill wrote:
On Thu, Oct 22, 2020
.
small...@aliyun.com
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
e
will be supported by rtems 5.x ?
small...@aliyun.com
From: Joel Sherrill
Date: 2020-12-17 03:39
To: rtems-de...@rtems.org; David Edelsohn
Subject: Planning for RTEMS 6 Branch
Hi
It took a long time to get from 4.10 to 4.11 and then on to 5. I don't see any
reason getting from 5 to 6 should
Hi,joel
Your reply is helpful and fast as usual. Thanks very much!
small...@aliyun.com
From: Joel Sherrill
Date: 2020-12-17 08:44
To: smallphd
CC: devel; David Edelsohn
Subject: Re: Planning for RTEMS 6 Branch
On Wed, Dec 16, 2020, 6:38 PM small...@aliyun.com wrote:
Hi, joel
Our team is
Thanks both of you for these advice. It is very clear for me now.
small...@aliyun.com
From: Gedare Bloom
Date: 2020-07-18 23:49
To: Christian Mauderer
CC: small...@aliyun.com; devel
Subject: Re: A question about rtems license
On Sat, Jul 18, 2020 at 9:20 AM Christian Mauderer wrote
Hello，
I have a TI bsp which uses a ARM cortex A72 process. It has 4 cores and MMU
enabled.
So does rtems support SMP and MMU in such a platform?
After searching the mail and source code, I only find a cortex A53 platform.
small...@aliyun.com
32-bit mode is OK.
Does it fully support SMP and MMU in this bsp?
small...@aliyun.com
From: Joel Sherrill
Date: 2020-07-24 00:14
To: Sebastian Huber
CC: small...@aliyun.com; devel
Subject: Re: Is rtems available on a 4-cores cortex A72 (ARM-v8a) bsp?
On Thu, Jul 23, 2020 at 7:25 AM
xilinx-zynqmp BSP has a ARM cortex A53 processor. Is it a ARMv8-A architeture?
small...@aliyun.com
From: Sebastian Huber
Date: 2020-07-24 12:49
To: small...@aliyun.com; joel
CC: devel
Subject: Re: Is rtems available on a 4-cores cortex A72 (ARM-v8a) bsp?
On 24/07/2020 03:09, small
.
But after I compare the two edition's source code, I find the difference is
much more than the document listed.
small...@aliyun.com
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman/listinfo/devel
qemu.
Does anybody try use rtems to access a pci device in arm platform, especially a
qemu environment, as I want use the ivshmem function of qemu.
Thank you very much!
small...@aliyun.com
___
devel mailing list
devel@rtems.org
http://lists.rtems.org
Thank you very much!
If anything found, please send me a message.
small...@aliyun.com
From: Sebastian Huber
Date: 2020-09-04 16:10
To: small...@aliyun.com; devel
Subject: Re: Does rtems support pci device in arm architecture?
Hello,
there is some support for PCI in libbsd. I would have a
whole contents of memory and I could use a debuger to
analyse the file to handle the bug.
The question arise because I do not want always debug rtems in the bsp.
small...@aliyun.com
___
devel mailing list
devel@rtems.org
http://lists.rtems.org/mailman
of the normal kernel.
small...@aliyun.com
From: Gedare Bloom
Date: 2020-09-15 23:26
To: small...@aliyun.com
CC: devel
Subject: Re: does rtems 5.1 support create a core dump file when accessing a
invalid address or other fatal errors?
No, there is no facility to generate a core dump. Due to
.
small...@aliyun.com
From: Chris Johns
Date: 2020-09-16 08:33
To: small...@aliyun.com; devel
Subject: Re: does rtems 5.1 support create a core dump file when accessing a
invalid address or other fatal errors?
On 15/9/20 8:58 pm, small...@aliyun.com wrote:
> I am developing applications in rtems 5.
22 matches
Mail list logo
