I think the key problem is the bsp_start_hook_0 function which will be executed
in all cores.
However, this function does not distinguish each core. It means all four cores
run the same code.
The right procedure is core 0 run the init code while other cores wait for it
to complete.
BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
{
uint32_t sctlr_val;
sctlr_val = arm_cp15_get_control();
sctlr_val |= ARM_CP15_CTRL_CP15BEN;
arm_cp15_set_control( sctlr_val );
/*
* Current U-boot loader seems to start kernel image
* with I and D caches on and MMU enabled.
* If RTEMS application image finds that cache is on
* during startup then disable caches.
*/
if ( sctlr_val & (ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
if ( sctlr_val & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) {
/*
* If the data cache is on then ensure that it is clean
* before switching off to be extra carefull.
*/
arm_cp15_data_cache_clean_all_levels();
}
arm_cp15_flush_prefetch_buffer();
sctlr_val &= ~ ( ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M |
ARM_CP15_CTRL_A );
arm_cp15_set_control( sctlr_val );
}
arm_cp15_instruction_cache_invalidate();
/*
* The care should be taken there that no shared levels
* are invalidated by secondary CPUs in SMP case.
* It is not problem on Zynq because level of coherency
* is L1 only and higher level is not maintained and seen
* by CP15. So no special care to limit levels on the secondary
* are required there.
*/
arm_cp15_data_cache_invalidate_all_levels();
arm_cp15_branch_predictor_invalidate_all();
arm_cp15_tlb_invalidate();
arm_cp15_flush_prefetch_buffer();
}
small...@aliyun.com
From: Kinsey Moore
Date: 2020-10-06 21:56
To: j...@rtems.org; small...@aliyun.com
CC: Gedare Bloom; devel
Subject: RE: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp
Is it possible that the application was only started on the first core instead
of all cores? Is it possible to check the execution state of the other cores?
Kinsey
From: Joel Sherrill <j...@rtems.org>
Sent: Tuesday, October 6, 2020 08:11
To: small...@aliyun.com
Cc: Gedare Bloom <ged...@rtems.org>; devel <devel@rtems.org>; Kinsey Moore
<kinsey.mo...@oarcorp.com>
Subject: Re: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp
Maybe Kinsey has an idea.
On Tue, Oct 6, 2020 at 1:29 AM small...@aliyun.com <small...@aliyun.com> wrote:
The board is Ultra96 board with JTAG boot.
And yes, there is a bspsmp.c in rtems-5.1\bsps\arm\xilinx-zynqmp\start\
small...@aliyun.com
From: Gedare Bloom
Date: 2020-10-06 00:16
To: small...@aliyun.com
CC: devel
Subject: Re: I can not run rtems 5.1 smp correctly on bsp xilinx-zynqmp
It should, I believe. The bsp has bspsmp.c file.
How did you configure (../rtems/configure)?
What board/target do you run it on?
On Mon, Oct 5, 2020 at 2:24 AM small...@aliyun.com <small...@aliyun.com> wrote:
>
> Hi, all
> I compile rtems 5.1 with bsp xilinx-zynqmp. The single core mode is ok.
> But I can not use 2 or 3 or 4 cores of this bsp.
> After analysing the source code, I found there is no code to address smp
> condition. Does rtems 5.1 indeed not support smp mode for xilinx-zynqmp bsp?
>
> ________________________________
> small...@aliyun.com
> _______________________________________________
> devel mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
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