[PATCH] D83955: [PowerPC][Power10] Implementation of 128-bit Binary Vector Multiply builtins

Conanap created this revision. Conanap added reviewers: PowerPC, saghir, nemanjai, hfinkel. Conanap added projects: LLVM, clang, PowerPC. Herald added subscribers: steven.zhang, kbarton. This patch implements 128-bit Binary Vector Multiply builtins for PowerPC10. Repository: rG LLVM Github Mon

[PATCH] D84197: [PowerPC][Power10] 128-bit Vector String Isolate instruction definitions and MC Tests

Conanap created this revision. Conanap added reviewers: PowerPC, saghir, nemanjai, hfinkel. Conanap added projects: LLVM, clang, PowerPC. Herald added a subscriber: kbarton. This implements vector string isolate instructions used in vector string isolate builtins. Repository: rG LLVM Github M

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap updated this revision to Diff 279348. Conanap marked 8 inline comments as done. Conanap added a comment. Fixed function names, test case clean up Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338 File

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 279362. Conanap marked 5 inline comments as done. Conanap added a comment. Return signature fix, added recognition for ISD:EXTLOAD, some code clean up. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ h

[PATCH] D83955: [PowerPC][Power10] Implementation of 128-bit Binary Vector Multiply builtins

Conanap updated this revision to Diff 279637. Conanap marked 2 inline comments as done. Conanap added a comment. Changed if def to use pwer10_vector Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83955/new/ https://reviews.llvm.org/D83955 Files:

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap updated this revision to Diff 280592. Conanap removed a reviewer: power-llvm-team. Conanap added a comment. Herald added a subscriber: kbarton. Converted the impelmentation to an open coded implementation and updated the test cases as appropriate. Repository: rG LLVM Github Monorepo

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 280597. Conanap marked 2 inline comments as done. Conanap retitled this revision from "[PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend" to "[PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend". Conanap edited the

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap added a comment. Addressed formatting comments Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14156 + + // This transformation is only valid if the we are loading either a byte, + // halfword, word, or doubleword. NeHuang wrote: > nit: if we

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 281035. Conanap added a comment. Included sext test case. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 Files: clang/lib/Headers/altivec.h clang/test/CodeGen/buil

[PATCH] D84197: [PowerPC][Power10] 128-bit Vector String Isolate instruction definitions and MC Tests

Conanap updated this revision to Diff 281042. Conanap added a comment. Recovered accidentally deleted test cases. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84197/new/ https://reviews.llvm.org/D84197 Files: llvm/lib/Target/PowerPC/PPCInstrPre

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap updated this revision to Diff 281735. Conanap added a comment. Fixed formatting based on bot feedback. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338 Files: clang/lib/Headers/altivec.h clang/te

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap updated this revision to Diff 281783. Conanap added a comment. Replaced a forgotten test file. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338 Files: clang/lib/Headers/altivec.h clang/test/CodeG

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap marked 2 inline comments as done. Conanap added a comment. Addressed Anil's comments with regards to the test cases Comment at: llvm/test/CodeGen/PowerPC/p10-vsx-builtins.ll:56 + +; CHECK: lxvrdx +; Function Attrs: norecurse nounwind readonly anil9 wrot

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap added a comment. Addressed Lei's comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https:

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 275124. Conanap marked 4 inline comments as done. Conanap added a comment. Fixed some formatting stuff. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 Files: clang/l

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 275159. Conanap added a comment. Fixed a missing comma; ensured it builds. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 Files: clang/lib/Headers/altivec.h clang/

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap marked an inline comment as done. Conanap added a comment. fixed a missing comma and ensure that it compiles Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 275423. Conanap marked 3 inline comments as done. Conanap added a comment. Moved some code to the top of the file as per Lei's request Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.ll

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap marked 2 inline comments as done. Conanap added a comment. Addressed Lei's comments Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___ cfe-commits mail

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap created this revision. Conanap added reviewers: PowerPC, power-llvm-team, saghir, nemanjai, hfinkel. Conanap added projects: LLVM, clang, PowerPC. Implemented the following vector right and left shift builtins and its test cases: vector unsigned __int128 vec_sl(vector unsigned __int128

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

Conanap created this revision. Conanap added reviewers: power-llvm-team, PowerPC, saghir, nemanjai, hfinkel. Conanap added projects: LLVM, clang, PowerPC. Includes instruction defintion and MC Tests for above instructions. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D83364 F

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

Conanap updated this revision to Diff 276564. Conanap added a comment. Relocated some of the instructions to a more appropriate place. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83364/new/ https://reviews.llvm.org/D83364 Files: llvm/lib/Targe

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

Conanap marked 2 inline comments as done. Conanap added a comment. Relocated the isntr definitions to a more appropriate place. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83364/new/ https://reviews.llvm.org/D83364

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap added a comment. Also removed unnecessary brackets and comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 ___ cfe-commits mailing list cfe-commit

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 276785. Conanap marked 3 inline comments as done. Conanap added a comment. Now depends on D83364 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.

[PATCH] D83364: [PowerPC][Power10] Implement Instruction definition and MC Tests for Load and Store VSX Vector with Zero or Sign Extend

Conanap marked an inline comment as done. Conanap added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:939 + // The XFormMemOp flag for the following 8 insts is set on the instruction format. + let mayLoad = 1, mayStore = 1 in { +def LXVRBX : X_XT6_

[PATCH] D83516: [PowerPC][Power10] RFC 2608 Instruction definitions and MC Tests

Conanap created this revision. Conanap added reviewers: power-llvm-team, PowerPC, saghir, nemanjai, hfinkel. Conanap added projects: LLVM, clang, PowerPC. This implements instruction definitions and MC tests for RFC2608. Please note that some instrs have classes that will need to be changed later

[PATCH] D83516: [PowerPC][Power10] Vector shift Instruction definitions and MC Tests

Conanap updated this revision to Diff 277127. Conanap added a comment. Added a new line to the end of ppc64-encoding-ISA31.txt Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83516/new/ https://reviews.llvm.org/D83516 Files: llvm/lib/Target/PowerP

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 277415. Conanap marked 2 inline comments as done. Conanap added a comment. Removed unecessary comments and unintended changes. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 Files: clang/lib/Headers/altiv

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 277418. Conanap added a comment. Removed duplicate test code found in the instructions and MC Test implementation of VSX Vector store and load with sign extend or zero extend; re-added a test file that was omitted in the last diff update. Repository: rG

[PATCH] D83516: [PowerPC][Power10] 128-bit Binary Integer Operation instruction definitions and MC Tests

Conanap updated this revision to Diff 277442. Conanap marked an inline comment as done. Conanap added a comment. Some formatting changes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83516/new/ https://reviews.llvm.org/D83516 Files: llvm/lib/Tar

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap updated this revision to Diff 277896. Conanap marked 3 inline comments as done. Conanap added a comment. Added tests, added extra comments. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338 Files: c

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap added a comment. Also removed instr def as it will be part of D83516 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338 ___

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 277952. Conanap added a comment. Restored accidentally deleted pattern, removed duplicate tests, moved new tests to another pre-existing file instead. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ h

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap updated this revision to Diff 278235. Conanap marked 7 inline comments as done. Conanap added a comment. Formatting fixes, fixed test case return type, updated builtins' signatures to correct signatures. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap created this revision. Conanap added reviewers: power-llvm-team, PowerPC, nemanjai, saghir, hfinkel. Conanap added projects: LLVM, clang, PowerPC. Implemented following functions for Load VSX Vector Sign extend nad zero extend instructions: vector signed __int128 vec_xl_sext (signed lo

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 273393. Conanap added a comment. Addressed Amy's comments regarding documentation of the changes. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://reviews.llvm.org/D82502 Files: clang/lib/Hea

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 273421. Conanap marked 9 inline comments as done. Conanap added a comment. Fixed return signature for the open coded functions in altivec.h Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/ https://revie

[PATCH] D82502: [PowerPC][Power10] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 274097. Conanap marked an inline comment as done. Conanap added a comment. Reordered some declarations in test cases and removed unecessary extra CHECKs. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82502/new/

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 281974. Conanap marked 2 inline comments as done. Conanap removed a reviewer: power-llvm-team. Conanap added a comment. Herald added a subscriber: kbarton. Some updates on formatting and updated to match an updated test file. Repository: rG LLVM Github Mon

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

Conanap created this revision. Conanap added reviewers: PowerPC, saghir, nemanjai, hfinkel. Conanap added projects: LLVM, clang, PowerPC. Herald added subscribers: cfe-commits, shchenz. Conanap requested review of this revision. Repository: rG LLVM Github Monorepo https://reviews.llvm.org/D8496

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

Conanap updated this revision to Diff 283061. Conanap marked 2 inline comments as done. Conanap added a comment. Clang formatted relevant lines, combined LE and BE tests as they produced the same ASM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D8

[PATCH] D85453: [PowerPC] Implement __int128 vector divide operations

Conanap created this revision. Conanap added reviewers: PowerPC, saghir, nemanjai, hfinkel. Conanap added projects: LLVM, clang, PowerPC. Herald added a subscriber: kbarton. Conanap requested review of this revision. Herald added a subscriber: wuzish. This patch implements __int128 vector divide o

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap updated this revision to Diff 283980. Conanap marked 8 inline comments as done. Conanap added a comment. Added shl tests, formatting fixes Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83338/new/ https://reviews.llvm.org/D83338 Files: cl

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

Conanap added inline comments. Comment at: clang/lib/Headers/altivec.h:17243 + // return (vector signed __int128)vec_sr((vector unsigned __int128)__a, __b); + return (vector signed __int128)( +((vector unsigned __int128) __a) >> amyk wrote: > Could

[PATCH] D83338: [PowerPC][Power10] Implemented Vector Shift Builtins

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG3136cbe29e74: [PowerPC] Implement Vector Shift Builtins (authored by Conanap). Changed prior to commit: https://reviews.llvm.org/D83338?vs=283980

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359066. Conanap added a comment. Added more tests, corrected sema checking and intrinsic flag Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 Files: clang/include/c

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359097. Conanap marked 2 inline comments as done. Conanap added a comment. Changed xoaddr, removed extws, changed check prefix Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359104. Conanap added a comment. Changed more xoaddr to ForceXForm Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 Files: clang/include/clang/Basic/BuiltinsPPC.def

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

Conanap created this revision. Herald added subscribers: steven.zhang, shchenz, kbarton, hiraditya, nemanjai. Conanap requested review of this revision. Herald added projects: clang, LLVM. Herald added subscribers: llvm-commits, cfe-commits. Implemented builtins for mtmsr, mfspr, mtspr on PowerPC;

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

Conanap updated this revision to Diff 359236. Conanap added a comment. Added sema checking Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106130/new/ https://reviews.llvm.org/D106130 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Ba

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359259. Conanap added a comment. Updated lharx and lbarx to inline asm implementation, implemented stfiw. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 Files: cla

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359322. Conanap marked 5 inline comments as done. Conanap added a comment. Added non-vsx pattern for stfiw, extra testline for that pattern, some nits Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ h

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359380. Conanap added a comment. Updated a test case Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Ba

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

Conanap updated this revision to Diff 359400. Conanap marked 4 inline comments as done. Conanap added a comment. Changed `i32` to `timm` for patterns, some nits Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106130/new/ https://reviews.llvm.org/D106

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

Conanap added inline comments. Comment at: clang/lib/CodeGen/CGBuiltin.cpp:15586 + case PPC::BI__builtin_ppc_mfspr: { +llvm::Type *RetType = CGM.getDataLayout().getTypeSizeInBits(VoidPtrTy) == 32 + ? Int32Ty nemanjai wrote: > Is

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

Conanap updated this revision to Diff 359424. Conanap added a comment. added an error test Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106130/new/ https://reviews.llvm.org/D106130 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Ba

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359433. Conanap marked an inline comment as done. Conanap added a comment. Updated test cases Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 Files: clang/include/c

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap marked 4 inline comments as done. Conanap added a comment. Addressed comments Comment at: clang/test/CodeGen/builtins-ppc-xlcompat-LoadReseve-StoreCond.c:15 + // CHECK-LABEL: @test_lwarx // CHECK: %0 = tail call i32 asm sideeffect "lwarx $0, ${1:y}", "=r,*Z,~{memor

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359516. Conanap marked an inline comment as done. Conanap added a comment. Moved pattern to a more appropriate place, updated test cases Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews

[PATCH] D105926: [PowerPC] Extra test case for LDARX

Conanap added a comment. In D105926#2885291 , @teemperor wrote: > Sorry for raising an unrelated topic here, but I can't reach @Conanap > directly via the mail from the git commits: @Conanap could you please create > the git branches for your patches in

[PATCH] D105926: [PowerPC] Extra test case for LDARX

Conanap updated this revision to Diff 359681. Conanap added a comment. Removed metadata, -O3 to generate the test case Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105926/new/ https://reviews.llvm.org/D105926 Files: clang/test/CodeGen/builtins-

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359850. Conanap added a comment. Changed flags for intrinsic of dcbtt and dcbtstt Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 Files: clang/include/clang/Basic/B

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap updated this revision to Diff 359945. Conanap added a comment. Fixed a typo Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Basic/Tar

[PATCH] D105926: [PowerPC] Extra test case for LDARX

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG1d3e77e7a842: [PowerPC] Extra test case for LDARX (authored by Conanap). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://

[PATCH] D105926: [PowerPC] Extra test case for LDARX

Conanap reopened this revision. Conanap added a comment. This revision is now accepted and ready to land. Had to revert this as I'm seeing failures on buildbots not owned by us. The error is: llc: error: : error: unable to get target for 'powerpc64le-unknown-linux-gnu', see --version and --tr

[PATCH] D105926: [PowerPC] Extra test case for LDARX

Conanap updated this revision to Diff 360114. Conanap added a comment. Herald added a project: LLVM. Herald added a subscriber: llvm-commits. Moved to llvm/test/CodeGen/PowerPC Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105926/new/ https://revie

[PATCH] D105926: [PowerPC] Extra test case for LDARX

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2a7711f33a04: [PowerPC] Extra test case for LDARX (authored by Conanap). Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG3434ac9e3902: [PowerPC] Store, load, move from and to registers related builtins (authored by Conanap). Changed prior to commit: https://reviews.l

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap added a comment. I'm aware of the getting target issue; the fix will be up soon. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105946/new/ https://reviews.llvm.org/D105946 ___ cfe-commits mailing

[PATCH] D106130: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2fd1520247de: [PowerPC] Implemented mtmsr, mfspr, mtspr Builtins (authored by Conanap). Changed prior to commit: https://reviews.llvm.org/D106130?

[PATCH] D105946: [PowerPC] Store, load, move from and to registers related builtins

Conanap added a comment. issue should be fixed now; pushed with this: https://reviews.llvm.org/D106130#change-PZi4uueeCg9i (I just had to move the test files into the `PowerPC` folder). Will continue to monitor Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.

[PATCH] D106484: [PowerPC] Add PowerPC "__stbcx" builtin and intrinsic for XL compatibility

Conanap added inline comments. Comment at: clang/lib/Sema/SemaChecking.cpp:3437 case PPC::BI__builtin_ppc_icbt: + case PPC::BI__builtin_ppc_stbcx: return SemaFeatureCheck(*this, TheCall, "isa-v207-instructions", would prefer if this joined the list of `s

[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

Conanap added inline comments. Comment at: clang/lib/Headers/altivec.h:3151 +#else +#define __vec_ldrmb __builtin_vsx_ldrmb +#define __vec_strmb __builtin_vsx_strmb I believe the preference is to have this defined in `clang/lib/Basic/Targets/PPC.cpp` under `defi

[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

Conanap added a comment. do we need an IR -> ASM test case as well? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106757/new/ https://reviews.llvm.org/D106757 ___ cfe-commits mailing list cfe-commits@lis

[PATCH] D106757: [PowerPC] Implement partial vector ld/st builtins for XL compatibility

Conanap accepted this revision. Conanap added a comment. This revision is now accepted and ready to land. Thanks for answering the Qs. LGTM. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106757/new/ https://reviews.llvm.org/D106757 ___

[PATCH] D106817: [PowerPC] Changed sema checking range for tdw td builtin

Conanap created this revision. Herald added subscribers: steven.zhang, shchenz, nemanjai. Conanap requested review of this revision. Herald added a project: clang. Herald added a subscriber: cfe-commits. To match xlc behaviour and definition in the PowerPC ISA3.1, it is a better idea to have the c

[PATCH] D106817: [PowerPC] Changed sema checking range for tdw td builtin

Conanap updated this revision to Diff 361754. Conanap added a comment. Herald added a subscriber: kbarton. Updated test cases Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D106817/new/ https://reviews.llvm.org/D106817 Files: clang/lib/Sema/SemaCh

[PATCH] D106817: [PowerPC] Changed sema checking range for tdw td builtin

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG18526b0d661f: [PowerPC] Changed sema checking range for tdw td builtin (authored by Conanap). Repository: rG LLVM Github Monorepo CHANGES SINCE L

[PATCH] D85453: [PowerPC] Implement __int128 vector divide operations

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG05aa997d511e: [PowerPC] Implement __int128 vector divide operations (authored by Conanap). Changed prior to commit: https://reviews.llvm.org/D8545

[PATCH] D87729: [PowerPC] Implement the 128-bit Vector Divide Extended Builtins in Clang/LLVM

Conanap requested changes to this revision. Conanap added a comment. This revision now requires changes to proceed. Looks like there's some unit test failures; could you double check? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87729/new/ https:/

[PATCH] D87729: [PowerPC] Implement the 128-bit Vector Divide Extended Builtins in Clang/LLVM

Conanap accepted this revision. Conanap added a comment. This revision is now accepted and ready to land. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87729/new/ https://reviews.llvm.org/D87729 ___

[PATCH] D87804: [PowerPC][Power10] Implement Vector signed/unsigned __int128 overloads for the comparison builtins

Conanap created this revision. Conanap added reviewers: PowerPC, saghir, nemanjai, hfinkel. Conanap added projects: LLVM, PowerPC, clang. Herald added a subscriber: kbarton. Conanap requested review of this revision. This patch implements Vector signed/unsigned __int128 overloads for the comparis

[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

Conanap added inline comments. Comment at: clang/lib/Headers/altivec.h:17394 +static __inline__ vector signed __int128 __ATTRS_o_ai +vec_mod(vector signed __int128 __a, vector signed __int128 __b) { + return __builtin_altivec_vmodsq(__a, __b); amyk wrote: > nit:

[PATCH] D84962: [PowerPC] Correct cpsgn's behaviour on PowerPC to match that of the ABI

Conanap updated this revision to Diff 292589. Conanap added a comment. Herald added a subscriber: kbarton. Added extra test case to demonstrate that the arguments will be reversed CHANGES SINCE LAST ACTION https://reviews.llvm.org/D84962/new/ https://reviews.llvm.org/D84962 Files: clang/li

[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

Conanap updated this revision to Diff 292901. Conanap added a comment. Open coded VMODS/UQ instead. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87394/new/ https://reviews.llvm.org/D87394 Files: clang/include/clang/Basic/BuiltinsPPC.def clang

[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

Conanap updated this revision to Diff 293076. Conanap added a comment. Open Coded instead CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87394/new/ https://reviews.llvm.org/D87394 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/Headers/altivec.h clang/test/CodeGen/built

[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

Conanap added inline comments. Comment at: clang/lib/Headers/altivec.h:17394 +static __inline__ vector signed __int128 __ATTRS_o_ai +vec_mod(vector signed __int128 __a, vector signed __int128 __b) { + return __builtin_altivec_vmodsq(__a, __b); Conanap wrote: > a

[PATCH] D87671: [PowerPC] Implement Vector String Isolate Builtins in Clang/LLVM

Conanap accepted this revision. Conanap added a comment. This revision is now accepted and ready to land. lgtm Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87671/new/ https://reviews.llvm.org/D87671 ___

[PATCH] D87910: [PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins in Clang/LLVM

Conanap accepted this revision. Conanap added a comment. This revision is now accepted and ready to land. lgtm Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87910/new/ https://reviews.llvm.org/D87910 ___

[PATCH] D86819: [PowerPC][Power10] Implementation of 128-bit Binary Vector Rotate builtins

Conanap updated this revision to Diff 293474. Conanap marked 2 inline comments as done. Conanap added a comment. Changed implementation for vrlqnm as per Nemanja CHANGES SINCE LAST ACTION https://reviews.llvm.org/D86819/new/ https://reviews.llvm.org/D86819 Files: clang/include/clang/Basic/

[PATCH] D87921: Fix -funique-internal-linkage-names to work with -O2 and new pass manager

Conanap added a comment. It looks like this commit is causing a few failures on nearly all PPC bots and a sanitizer bot; would it be possible to revert this commit for now until the issue is resolved? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D

[PATCH] D87394: [PowerPC][Power10] Implementation of 128-bit Binary Vector Mod and Sign Extend builtins

Conanap closed this revision. Conanap added a comment. Committed with Nemanja's comments addressed in the commit. Hash d7eb917a7cb793f49e16841fc24826b988dd5c8f CHANGES SINCE LAST ACTION https://reviews.llvm.org/D87394/new/

[PATCH] D87804: [PowerPC][Power10] Implement Vector signed/unsigned __int128 overloads for the comparison builtins

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Conanap marked an inline comment as done. Closed by commit rG88cdbeab417c: [PowerPC] Implement Vector signed/unsigned __int128 overloads for the… (authored by Conanap).

[PATCH] D87910: [PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge] builtins in Clang/LLVM

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG2e7117f84770: [PowerPC] Implement the 128-bit vec_[all|any]_[eq | ne | lt | gt | le | ge]… (authored by amyk, committed by Conanap). Changed prior

[PATCH] D82502: [PowerPC] Implement Load VSX Vector and Sign Extend and Zero Extend

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Conanap marked an inline comment as done. Closed by commit rG331dcc43eac2: [PowerPC] Implemented Vector Load with Zero and Signed Extend Builtins (authored by Conanap).

[PATCH] D86819: [PowerPC][Power10] Implementation of 128-bit Binary Vector Rotate builtins

Conanap created this revision. Conanap added reviewers: PowerPC, saghir, nemanjai, hfinkel. Conanap added projects: LLVM, clang, PowerPC. Herald added subscribers: danielkiss, steven.zhang, kbarton. Conanap requested review of this revision. This patch implements 128-bit Binary Vector Rotate built

[PATCH] D86819: [PowerPC][Power10] Implementation of 128-bit Binary Vector Rotate builtins

Conanap updated this revision to Diff 289064. Conanap added a comment. Included extra test cases Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D86819/new/ https://reviews.llvm.org/D86819 Files: clang/include/clang/Basic/BuiltinsPPC.def clang/li

[PATCH] D83955: [PowerPC][Power10] Implementation of 128-bit Binary Vector Multiply builtins

This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rG5d1fe3f903b9: [PowerPC] Implemented Vector Multiply Builtins (authored by Conanap). Changed prior to commit: https://reviews.llvm.org/D83955?vs=27

[PATCH] D82727: [PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

Conanap added inline comments. Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:993 + [(set v16i8:$vD, (int_ppc_altivec_vexpandbm + v16i8:$vB))]>; def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (ou

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