Conanap created this revision.
Conanap added reviewers: power-llvm-team, PowerPC, saghir, nemanjai, hfinkel.
Conanap added projects: LLVM, clang, PowerPC.
This implements instruction definitions and MC tests for RFC2608. Please note
that some instrs have classes that will need to be changed later as their
classes have not been implemented yet - they will be implemented in their
respective patches.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D83516
Files:
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
Index: llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
===================================================================
--- llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
+++ llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
@@ -405,3 +405,84 @@
# CHECK-BE: vinsdrx 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xcf]
# CHECK-LE: vinsdrx 1, 2, 3 # encoding: [0xcf,0x1b,0x22,0x10]
vinsdrx 1, 2, 3
+# CHECK-BE: vmulesd 1, 2, 3 # encoding: [0x10,0x22,0x1b,0xc8]
+# CHECK-LE: vmulesd 1, 2, 3 # encoding: [0xc8,0x1b,0x22,0x10]
+ vmulesd 1, 2, 3
+# CHECK-BE: vmulosd 1, 2, 3 # encoding: [0x10,0x22,0x19,0xc8]
+# CHECK-LE: vmulosd 1, 2, 3 # encoding: [0xc8,0x19,0x22,0x10]
+ vmulosd 1, 2, 3
+# CHECK-BE: vmuleud 1, 2, 3 # encoding: [0x10,0x22,0x1a,0xc8]
+# CHECK-LE: vmuleud 1, 2, 3 # encoding: [0xc8,0x1a,0x22,0x10]
+ vmuleud 1, 2, 3
+# CHECK-BE: vmuloud 1, 2, 3 # encoding: [0x10,0x22,0x18,0xc8]
+# CHECK-LE: vmuloud 1, 2, 3 # encoding: [0xc8,0x18,0x22,0x10]
+ vmuloud 1, 2, 3
+# CHECK-BE: vmsumcud 1, 2, 3, 4 # encoding: [0x10,0x22,0x19,0x17]
+# CHECK-LE: vmsumcud 1, 2, 3, 4 # encoding: [0x17,0x19,0x22,0x10]
+ vmsumcud 1, 2, 3, 4
+# CHECK-BE: vdivsq 3, 4, 5 # encoding: [0x10,0x64,0x29,0x0b]
+# CHECK-LE: vdivsq 3, 4, 5 # encoding: [0x0b,0x29,0x64,0x10]
+ vdivsq 3, 4, 5
+# CHECK-BE: vdivuq 3, 4, 5 # encoding: [0x10,0x64,0x28,0x0b]
+# CHECK-LE: vdivuq 3, 4, 5 # encoding: [0x0b,0x28,0x64,0x10]
+ vdivuq 3, 4, 5
+# CHECK-BE: vdivesq 3, 4, 5 # encoding: [0x10,0x64,0x2b,0x0b]
+# CHECK-LE: vdivesq 3, 4, 5 # encoding: [0x0b,0x2b,0x64,0x10]
+ vdivesq 3, 4, 5
+# CHECK-BE: vdiveuq 3, 4, 5 # encoding: [0x10,0x64,0x2a,0x0b]
+# CHECK-LE: vdiveuq 3, 4, 5 # encoding: [0x0b,0x2a,0x64,0x10]
+ vdiveuq 3, 4, 5
+# CHECK-BE: vcmpequq 4, 5, 6 # encoding: [0x10,0x85,0x31,0xc7]
+# CHECK-LE: vcmpequq 4, 5, 6 # encoding: [0xc7,0x31,0x85,0x10]
+ vcmpequq 4, 5, 6
+# CHECK-BE: vcmpequq. 4, 5, 6 # encoding: [0x10,0x85,0x35,0xc7]
+# CHECK-LE: vcmpequq. 4, 5, 6 # encoding: [0xc7,0x35,0x85,0x10]
+ vcmpequq. 4, 5, 6
+# CHECK-BE: vcmpgtsq 4, 5, 6 # encoding: [0x10,0x85,0x33,0x87]
+# CHECK-LE: vcmpgtsq 4, 5, 6 # encoding: [0x87,0x33,0x85,0x10]
+ vcmpgtsq 4, 5, 6
+# CHECK-BE: vcmpgtsq. 4, 5, 6 # encoding: [0x10,0x85,0x37,0x87]
+# CHECK-LE: vcmpgtsq. 4, 5, 6 # encoding: [0x87,0x37,0x85,0x10]
+ vcmpgtsq. 4, 5, 6
+# CHECK-BE: vcmpgtuq 4, 5, 6 # encoding: [0x10,0x85,0x32,0x87]
+# CHECK-LE: vcmpgtuq 4, 5, 6 # encoding: [0x87,0x32,0x85,0x10]
+ vcmpgtuq 4, 5, 6
+# CHECK-BE: vcmpgtuq. 4, 5, 6 # encoding: [0x10,0x85,0x36,0x87]
+# CHECK-LE: vcmpgtuq. 4, 5, 6 # encoding: [0x87,0x36,0x85,0x10]
+ vcmpgtuq. 4, 5, 6
+# CHECK-BE: vmoduq 3, 4, 5 # encoding: [0x10,0x64,0x2e,0x0b]
+# CHECK-LE: vmoduq 3, 4, 5 # encoding: [0x0b,0x2e,0x64,0x10]
+ vmoduq 3, 4, 5
+# CHECK-BE: vextsd2q 20, 25 # encoding: [0x12,0x9b,0xce,0x02]
+# CHECK-LE: vextsd2q 20, 25 # encoding: [0x02,0xce,0x9b,0x12]
+ vextsd2q 20, 25
+# CHECK-BE: vrlq 4, 5, 6 # encoding: [0x10,0x85,0x30,0x05]
+# CHECK-LE: vrlq 4, 5, 6 # encoding: [0x05,0x30,0x85,0x10]
+ vrlq 4, 5, 6
+# CHECK-BE: vrlqnm 4, 5, 6 # encoding: [0x10,0x85,0x31,0x45]
+# CHECK-LE: vrlqnm 4, 5, 6 # encoding: [0x45,0x31,0x85,0x10]
+ vrlqnm 4, 5, 6
+# CHECK-BE: vrlqmi 4, 5, 6 # encoding: [0x10,0x85,0x30,0x45]
+# CHECK-LE: vrlqmi 4, 5, 6 # encoding: [0x45,0x30,0x85,0x10]
+ vrlqmi 4, 5, 6
+# CHECK-BE: vslq 4, 5, 6 # encoding: [0x10,0x85,0x31,0x05]
+# CHECK-LE: vslq 4, 5, 6 # encoding: [0x05,0x31,0x85,0x10]
+ vslq 4, 5, 6
+# CHECK-BE: vsrq 4, 5, 6 # encoding: [0x10,0x85,0x32,0x05]
+# CHECK-LE: vsrq 4, 5, 6 # encoding: [0x05,0x32,0x85,0x10]
+ vsrq 4, 5, 6
+# CHECK-BE: vsraq 4, 5, 6 # encoding: [0x10,0x85,0x33,0x05]
+# CHECK-LE: vsraq 4, 5, 6 # encoding: [0x05,0x33,0x85,0x10]
+ vsraq 4, 5, 6
+# CHECK-BE: xscvqpuqz 8, 28 # encoding: [0xfd,0x00,0xe6,0x88]
+# CHECK-LE: xscvqpuqz 8, 28 # encoding: [0x88,0xe6,0x00,0xfd]
+ xscvqpuqz 8, 28
+# CHECK-BE: xscvqpsqz 8, 28 # encoding: [0xfd,0x08,0xe6,0x88]
+# CHECK-LE: xscvqpsqz 8, 28 # encoding: [0x88,0xe6,0x08,0xfd]
+ xscvqpsqz 8, 28
+# CHECK-BE: xscvuqqp 8, 28 # encoding: [0xfd,0x03,0xe6,0x88]
+# CHECK-LE: xscvuqqp 8, 28 # encoding: [0x88,0xe6,0x03,0xfd]
+ xscvuqqp 8, 28
+# CHECK-BE: xscvsqqp 8, 28 # encoding: [0xfd,0x0b,0xe6,0x88]
+# CHECK-LE: xscvsqqp 8, 28 # encoding: [0x88,0xe6,0x0b,0xfd]
+ xscvsqqp 8, 28
Index: llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
===================================================================
--- llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
+++ llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
@@ -278,3 +278,84 @@
# CHECK: vinsdrx 1, 2, 3
0x10 0x22 0x1b 0xcf
+
+# CHECK: vmulesd 1, 2, 3
+0x10 0x22 0x1b 0xc8
+
+# CHECK: vmulosd 1, 2, 3
+0x10 0x22 0x19 0xc8
+
+# CHECK: vmuleud 1, 2, 3
+0x10 0x22 0x1a 0xc8
+
+# CHECK: vmuloud 1, 2, 3
+0x10 0x22 0x18 0xc8
+
+# CHECK: vmsumcud 1, 2, 3, 4
+0x10 0x22 0x19 0x17
+
+# CHECK: vdivsq 3, 4, 5
+0x10 0x64 0x29 0x0b
+
+# CHECK: vdivuq 3, 4, 5
+0x10 0x64 0x28 0x0b
+
+# CHECK: vdivesq 3, 4, 5
+0x10 0x64 0x2b 0x0b
+
+# CHECK: vdiveuq 3, 4, 5
+0x10 0x64 0x2a 0x0b
+
+# CHECK: vcmpequq 4, 5, 6
+0x10 0x85 0x31 0xc7
+
+# CHECK: vcmpequq. 4, 5, 6
+0x10 0x85 0x35 0xc7
+
+# CHECK: vcmpgtsq 4, 5, 6
+0x10 0x85 0x33 0x87
+
+# CHECK: vcmpgtsq. 4, 5, 6
+0x10 0x85 0x37 0x87
+
+# CHECK: vcmpgtuq 4, 5, 6
+0x10 0x85 0x32 0x87
+
+# CHECK: vcmpgtuq. 4, 5, 6
+0x10 0x85 0x36 0x87
+
+# CHECK: vmoduq 3, 4, 5
+0x10 0x64 0x2e 0x0b
+
+# CHECK: vextsd2q 20, 25
+0x12 0x9b 0xce 0x02
+
+# CHECK: vrlq 4, 5, 6
+0x10 0x85 0x30 0x05
+
+# CHECK: vrlqnm 4, 5, 6
+0x10 0x85 0x31 0x45
+
+# CHECK: vrlqmi 4, 5, 6
+0x10 0x85 0x30 0x45
+
+# CHECK: vslq 4, 5, 6
+0x10 0x85 0x31 0x05
+
+# CHECK: vsrq 4, 5, 6
+0x10 0x85 0x32 0x05
+
+# CHECK: vsraq 4, 5, 6
+0x10 0x85 0x33 0x05
+
+# CHECK: xscvqpuqz 8, 28
+0xfd 0x00 0xe6 0x88
+
+# CHECK: xscvqpsqz 8, 28
+0xfd 0x08 0xe6 0x88
+
+# CHECK: xscvuqqp 8, 28
+0xfd 0x03 0xe6 0x88
+
+# CHECK: xscvsqqp 8, 28
+0xfd 0xb 0xe6 0x88
\ No newline at end of file
Index: llvm/lib/Target/PowerPC/PPCInstrPrefix.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrPrefix.td
+++ llvm/lib/Target/PowerPC/PPCInstrPrefix.td
@@ -265,6 +265,23 @@
!strconcat(opc, " $vD, $rA, $rB"), IIC_VecGeneral, pattern>,
RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+// VX-Form: [ PO BF // VRA VRB XO ]
+class VXForm_BF3_VAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
+ InstrItinClass itin, list<dag> pattern>
+ : I<4, OOL, IOL, asmstr, itin> {
+ bits<3> BF;
+ bits<5> VA;
+ bits<5> VB;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = BF;
+ let Inst{9-10} = 0;
+ let Inst{11-15} = VA;
+ let Inst{16-20} = VB;
+ let Inst{21-31} = xo;
+}
+
// VN-Form: [PO VRT VRA VRB PS SD XO]
// SD is "Shift Direction"
class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
@@ -942,6 +959,67 @@
"vclrrb $vD, $vA, $rB", IIC_VecGeneral,
[(set v16i8:$vD,
(int_ppc_altivec_vclrrb v16i8:$vA, i32:$rB))]>;
+
+ def VMULESD : VXForm_1<968, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmulesd $vD, $vA, $vB", IIC_VecGeneral, []>;
+
+ def VMULEUD : VXForm_1<712, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmuleud $vD, $vA, $vB", IIC_VecGeneral, []>;
+
+ def VMULOSD : VXForm_1<456, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmulosd $vD, $vA, $vB", IIC_VecGeneral, []>;
+
+ def VMULOUD : VXForm_1<200, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmuloud $vD, $vA, $vB", IIC_VecGeneral, []>;
+
+ def VMSUMCUD : VAForm_1a<23, (outs vrrc:$vD),
+ (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
+ "vmsumcud $vD, $vA, $vB, $vC", IIC_VecGeneral, []>;
+
+ def VDIVSQ : VXForm_1<267, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdivsq $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVUQ : VXForm_1<11, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdivuq $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVESQ : VXForm_1<779, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdivesq $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VDIVEUQ : VXForm_1<523, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vdiveuq $vD, $vA, $vB", IIC_VecGeneral, []>;
+
+ def VCMPEQUQ : VCMP <455, "vcmpequq $vD, $vA, $vB" , v1i128>;
+ def VCMPGTSQ : VCMP <903, "vcmpgtsq $vD, $vA, $vB" , v1i128>;
+ def VCMPGTUQ : VCMP <647, "vcmpgtuq $vD, $vA, $vB" , v1i128>;
+
+ def VCMPEQUQ_rec : VCMPo <455, "vcmpequq. $vD, $vA, $vB" , v1i128>;
+ def VCMPGTSQ_rec : VCMPo <903, "vcmpgtsq. $vD, $vA, $vB" , v1i128>;
+ def VCMPGTUQ_rec : VCMPo <647, "vcmpgtuq. $vD, $vA, $vB" , v1i128>;
+
+ def VMODSQ : VXForm_1<1803, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmodsq $vD, $vA, $vB", IIC_VecGeneral, []>;
+ def VMODUQ : VXForm_1<1547, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
+ "vmoduq $vD, $vA, $vB", IIC_VecGeneral, []>;
+
+ def VEXTSD2Q : VXForm_RD5_XO5_RS5<1538, 27, (outs vrrc:$vD), (ins vrrc:$vB),
+ "vextsd2q $vD, $vB", IIC_VecGeneral, []>;
+
+ def VCMPUQ : VXForm_BF3_VAB5<257, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
+ "vcmpuq $BF, $vA, $vB", IIC_VecGeneral, []>;
+ def VCMPSQ : VXForm_BF3_VAB5<321, (outs crrc:$BF), (ins vrrc:$vA, vrrc:$vB),
+ "vcmpsq $BF, $vA, $vB", IIC_VecGeneral, []>;
+
+ def VRLQNM : VX1_VT5_VA5_VB5<325, "vrlqnm", []>;
+ def VRLQMI : VXForm_1<69, (outs vrrc:$vD),
+ (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi),
+ "vrlqmi $vD, $vA, $vB", IIC_VecFP, []>,
+ RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">;
+ def VSLQ : VX1_VT5_VA5_VB5<261, "vslq", []>;
+ def VSRAQ : VX1_VT5_VA5_VB5<773, "vsraq", []>;
+ def VSRQ : VX1_VT5_VA5_VB5<517, "vsrq", []>;
+ def VRLQ : VX1_VT5_VA5_VB5<5, "vrlq", []>;
+
+ def XSCVQPUQZ : X_VT5_XO5_VB5<63, 0, 836, "xscvqpuqz", []>;
+ def XSCVQPSQZ : X_VT5_XO5_VB5<63, 8, 836, "xscvqpsqz", []>;
+ def XSCVUQQP : X_VT5_XO5_VB5<63, 3, 836, "xscvuqqp", []>;
+ def XSCVSQQP: X_VT5_XO5_VB5<63, 11, 836, "xscvsqqp", []>;
}
//---------------------------- Anonymous Patterns ----------------------------//
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