On 6/30/23 17:11, Christoph Müllner wrote:
On Fri, Jun 30, 2023 at 4:03 PM Richard Henderson
<[email protected]> wrote:
On 6/30/23 13:52, Christoph Muellner wrote:
+bool trans_fmvh_x_d(DisasContext *ctx, arg_fmvh_x_d *a)
+{
+ REQUIRE_FPU;
+ REQUIRE_ZFA(ctx);
+ REQUIRE_EXT(ctx, RVD);
+ REQUIRE_32BIT(ctx);
+
+ TCGv dst = dest_gpr(ctx, a->rd);
+ TCGv_i64 t1 = tcg_temp_new_i64();
+
+ tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32);
+ tcg_gen_trunc_i64_tl(dst, t1);
+ gen_set_gpr(ctx, a->rd, dst);
I think you would prefer
tcg_gen_srai_tl(t1, cpu_fpr[rs1], 32);
sari_tl() will not work, because cpu_fpr[a->rs1] is a TCGv_i64.
So I need to use sari_i64() and keep the trunc_i64_tl():
TCGv dst = dest_gpr(ctx, a->rd);
TCGv_i64 t1 = tcg_temp_new_i64();
tcg_gen_sari_i64(dst, cpu_fpr[a->rs1], 32);
tcg_gen_trunc_i64_tl(dst, t1);
gen_set_gpr(ctx, a->rd, dst);
I beg your pardon, typo. You have grasped my intent, thanks.
r~
