Having the south bridge assign the ISA interrupts to the ISA bus itself makes the south bridge more self contained. Furthermore, it allows ISA interrupt wiring in pci_piix3_realize() which will be used in subsequent patches.
Signed-off-by: Bernhard Beschow <[email protected]> --- hw/i386/pc_piix.c | 6 +++--- hw/isa/piix3.c | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 5ea8d4a585..dbddc3d060 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -245,10 +245,10 @@ static void pc_init1(MachineState *machine, object_property_set_bool(OBJECT(pci_dev), "smm-enabled", x86_machine_is_smm_enabled(x86ms), &error_abort); - pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); - piix3 = PIIX3_PCI_DEVICE(pci_dev); piix3->pic = x86ms->gsi; + pci_realize_and_unref(pci_dev, pci_bus, &error_fatal); + piix3_devfn = piix3->dev.devfn; isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev), @@ -259,6 +259,7 @@ static void pc_init1(MachineState *machine, piix4_pm = NULL; isa_bus = isa_bus_new(NULL, get_system_memory(), system_io, &error_abort); + isa_bus_irqs(isa_bus, x86ms->gsi); rtc_state = isa_new(TYPE_MC146818_RTC); qdev_prop_set_int32(DEVICE(rtc_state), "base_year", 2000); @@ -267,7 +268,6 @@ static void pc_init1(MachineState *machine, i8257_dma_init(isa_bus, 0); pcms->hpet_enabled = false; } - isa_bus_irqs(isa_bus, x86ms->gsi); if (x86ms->pic == ON_OFF_AUTO_ON || x86ms->pic == ON_OFF_AUTO_AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 27bd4dbf65..007225a96e 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -302,6 +302,8 @@ static void pci_piix3_realize(PCIDevice *dev, Error **errp) memory_region_add_subregion_overlap(pci_address_space_io(dev), PIIX_RCR_IOPORT, &d->rcr_mem, 1); + isa_bus_irqs(isa_bus, d->pic); + i8257_dma_init(isa_bus, 0); /* RTC */ -- 2.39.1
