While jirl shares the same instruction format as bne etc,
it is not assembled the same. In particular, rd is printed
first not second and the immediate is not pc-relative.
Decode into the arg_rr_i structure, which prints correctly.
This changes the "offs" member to "imm", to update translate.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/loongarch/disas.c | 2 +-
target/loongarch/insn_trans/trans_branch.c.inc | 2 +-
target/loongarch/insns.decode | 3 ++-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 858dfcc53a..7cffd853ec 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -628,7 +628,7 @@ INSN(beqz, r_offs)
INSN(bnez, r_offs)
INSN(bceqz, c_offs)
INSN(bcnez, c_offs)
-INSN(jirl, rr_offs)
+INSN(jirl, rr_i)
INSN(b, offs)
INSN(bl, offs)
INSN(beq, rr_offs)
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc
b/target/loongarch/insn_trans/trans_branch.c.inc
index 65dbdff41e..a860f7e733 100644
--- a/target/loongarch/insn_trans/trans_branch.c.inc
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
@@ -23,7 +23,7 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
- tcg_gen_addi_tl(cpu_pc, src1, a->offs);
+ tcg_gen_addi_tl(cpu_pc, src1, a->imm);
tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
gen_set_gpr(a->rd, dest, EXT_NONE);
tcg_gen_lookup_and_goto_ptr();
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 3fdc6e148c..de7b8f0f3c 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -67,6 +67,7 @@
@rr_ui12 .... ...... imm:12 rj:5 rd:5 &rr_i
@rr_i14s2 .... .... .............. rj:5 rd:5 &rr_i imm=%i14s2
@rr_i16 .... .. imm:s16 rj:5 rd:5 &rr_i
+@rr_i16s2 .... .. ................ rj:5 rd:5 &rr_i imm=%offs16
@hint_r_i12 .... ...... imm:s12 rj:5 hint:5 &hint_r_i
@rrr_sa2p1 .... ........ ... .. rk:5 rj:5 rd:5 &rrr_sa sa=%sa2p1
@rrr_sa2 .... ........ ... sa:2 rk:5 rj:5 rd:5 &rrr_sa
@@ -444,7 +445,7 @@ beqz 0100 00 ................ ..... .....
@r_offs21
bnez 0100 01 ................ ..... ..... @r_offs21
bceqz 0100 10 ................ 00 ... ..... @c_offs21
bcnez 0100 10 ................ 01 ... ..... @c_offs21
-jirl 0100 11 ................ ..... ..... @rr_offs16
+jirl 0100 11 ................ ..... ..... @rr_i16s2
b 0101 00 .......................... @offs26
bl 0101 01 .......................... @offs26
beq 0101 10 ................ ..... ..... @rr_offs16
--
2.34.1
