It uses two PTE bits, but QEMU is sequentially consistent, So it has no effect on QEMU currently.
Signed-off-by: liweiwei <liwei...@iscas.ac.cn> Signed-off-by: wangjunqiang <wangjunqi...@iscas.ac.cn> --- target/riscv/cpu_bits.h | 4 ++++ target/riscv/cpu_helper.c | 9 +++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 70391424b0..62713ec37a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -473,7 +473,11 @@ typedef enum { #define PTE_A 0x040 /* Accessed */ #define PTE_D 0x080 /* Dirty */ #define PTE_SOFT 0x300 /* Reserved for Software */ +#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future use */ +#define PTE_PBMT 0x6000000000000000 /* Page-based memory types */ #define PTE_N 0x8000000000000000 +#define PTE_ATTR 0xFFC0000000000000 /* All attributes bits */ + /* Page table PPN shift amount */ #define PTE_PPN_SHIFT 10 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e68db3e119..94b01bbf78 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -588,13 +588,18 @@ restart: return TRANSLATE_FAIL; } - hwaddr ppn = (pte & ~(target_ulong)PTE_N) >> PTE_PPN_SHIFT; + hwaddr ppn = (pte & ~(target_ulong)PTE_ATTR) >> PTE_PPN_SHIFT; - if (!(pte & PTE_V)) { + if (pte & PTE_RSVD) { + return TRANSLATE_FAIL; + } else if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */ + if (pte & (PTE_D | PTE_A | PTE_U | PTE_N | PTE_PBMT)) { + return TRANSLATE_FAIL; + } base = ppn << PGSHIFT; } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { /* Reserved leaf PTE flags: PTE_W */ -- 2.17.1