This patchset implements virtual memory related RISC-V extensions: Svnapot version 0.1, Svinval vesion 0.1, Svpbmt version 0.1.
Specification: https://github.com/riscv/virtual-memory/tree/main/specs The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-vritmem-upstream To test svinval implementation, specify cpu argument with 'x-svinval=true'. Other two extensions are enabled by default. This implementation can pass the riscv-tests for rv64ssvnapot. liweiwei (3): target/riscv: add support for svnapot extension target/riscv: add support for svinval extension target/riscv: add support for svpbmt extension target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/cpu_bits.h | 5 ++ target/riscv/cpu_helper.c | 25 +++++-- target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_svinval.c.inc | 75 +++++++++++++++++++++ target/riscv/translate.c | 1 + 7 files changed, 108 insertions(+), 7 deletions(-) create mode 100644 target/riscv/insn_trans/trans_svinval.c.inc -- 2.17.1
