On Thu, Oct 14, 2021 at 10:11 PM Richard Henderson < [email protected]> wrote:
> Split host_signal_pc and host_signal_write out of user-exec.c. > > Reviewed-by: Philippe Mathieu-Daudé <[email protected]> > Signed-off-by: Richard Henderson <[email protected]> > --- > linux-user/host/mips/host-signal.h | 62 +++++++++++++++++++++++++++++- > accel/tcg/user-exec.c | 52 +------------------------ > 2 files changed, 62 insertions(+), 52 deletions(-) > Reviewed-by: Warner Losh <[email protected]> > diff --git a/linux-user/host/mips/host-signal.h > b/linux-user/host/mips/host-signal.h > index f4b4d65031..9c83e51130 100644 > --- a/linux-user/host/mips/host-signal.h > +++ b/linux-user/host/mips/host-signal.h > @@ -1 +1,61 @@ > -#define HOST_SIGNAL_PLACEHOLDER > +/* > + * host-signal.h: signal info dependent on the host architecture > + * > + * Copyright (C) 2021 Linaro Limited > + * > + * This work is licensed under the terms of the GNU GPL, version 2 or > later. > + * See the COPYING file in the top-level directory. > + */ > + > +#ifndef MIPS_HOST_SIGNAL_H > +#define MIPS_HOST_SIGNAL_H > + > +static inline uintptr_t host_signal_pc(ucontext_t *uc) > +{ > + return uc->uc_mcontext.pc; > +} > + > +#if defined(__misp16) || defined(__mips_micromips) > +#error "Unsupported encoding" > +#endif > + > +static inline bool host_signal_write(siginfo_t *info, ucontext_t *uc) > +{ > + uint32_t insn = *(uint32_t *)host_signal_pc(uc); > + > + /* Detect all store instructions at program counter. */ > + switch ((insn >> 26) & 077) { > + case 050: /* SB */ > + case 051: /* SH */ > + case 052: /* SWL */ > + case 053: /* SW */ > + case 054: /* SDL */ > + case 055: /* SDR */ > + case 056: /* SWR */ > + case 070: /* SC */ > + case 071: /* SWC1 */ > + case 074: /* SCD */ > + case 075: /* SDC1 */ > + case 077: /* SD */ > +#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 > + case 072: /* SWC2 */ > + case 076: /* SDC2 */ > +#endif > + return true; > + case 023: /* COP1X */ > + /* > + * Required in all versions of MIPS64 since > + * MIPS64r1 and subsequent versions of MIPS32r2. > + */ > + switch (insn & 077) { > + case 010: /* SWXC1 */ > + case 011: /* SDXC1 */ > + case 015: /* SUXC1 */ > + return true; > + } > + break; > + } > + return false; > +} > + > +#endif > diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c > index bfd964b578..287f03dac5 100644 > --- a/accel/tcg/user-exec.c > +++ b/accel/tcg/user-exec.c > @@ -255,57 +255,7 @@ void *probe_access(CPUArchState *env, target_ulong > addr, int size, > return size ? g2h(env_cpu(env), addr) : NULL; > } > > -#if defined(__mips__) > - > -#if defined(__misp16) || defined(__mips_micromips) > -#error "Unsupported encoding" > -#endif > - > -int cpu_signal_handler(int host_signum, void *pinfo, > - void *puc) > -{ > - siginfo_t *info = pinfo; > - ucontext_t *uc = puc; > - uintptr_t pc = uc->uc_mcontext.pc; > - uint32_t insn = *(uint32_t *)pc; > - int is_write = 0; > - > - /* Detect all store instructions at program counter. */ > - switch((insn >> 26) & 077) { > - case 050: /* SB */ > - case 051: /* SH */ > - case 052: /* SWL */ > - case 053: /* SW */ > - case 054: /* SDL */ > - case 055: /* SDR */ > - case 056: /* SWR */ > - case 070: /* SC */ > - case 071: /* SWC1 */ > - case 074: /* SCD */ > - case 075: /* SDC1 */ > - case 077: /* SD */ > -#if !defined(__mips_isa_rev) || __mips_isa_rev < 6 > - case 072: /* SWC2 */ > - case 076: /* SDC2 */ > -#endif > - is_write = 1; > - break; > - case 023: /* COP1X */ > - /* Required in all versions of MIPS64 since > - MIPS64r1 and subsequent versions of MIPS32r2. */ > - switch (insn & 077) { > - case 010: /* SWXC1 */ > - case 011: /* SDXC1 */ > - case 015: /* SUXC1 */ > - is_write = 1; > - } > - break; > - } > - > - return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); > -} > - > -#elif defined(__riscv) > +#if defined(__riscv) > > int cpu_signal_handler(int host_signum, void *pinfo, > void *puc) > -- > 2.25.1 > >
