On 10/16/20 3:11 PM, Alexey Baturo wrote: > Signed-off-by: Alexey Baturo <[email protected]> > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu.h | 11 ++ > target/riscv/cpu_bits.h | 66 ++++++++++ > target/riscv/csr.c | 264 ++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 342 insertions(+)
Acked-by: Richard Henderson <[email protected]> I'd be delighted to see the J working group address the security concerns. And to address the fact that existing hardware will *not* read 0 for the *MTE CSRs, so it's silly to insist on that retroactively. Code should be explicitly checking for J in MISA. r~
