Hi folks,
This is third iteration of patches to support Pointer Masking for RISC-V.
Most of suggestions have been addressed, however some of them not:
- applying mask for return value while reading PM CSR has been kept to mask
higher priv level bits
- check_pm_current_disabled is not placed into CSR predicate, since the spec
expects to read zero from PM CSR if no PM extenstion is present
Thanks
Alexey Baturo (4):
[RISCV_PM] Add J-extension into RISC-V
[RISCV_PM] Support CSRs required for RISC-V PM extension except for
ones in hypervisor mode
[RISCV_PM] Print new PM CSRs in QEMU logs
[RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of
instructions
Anatoly Parshintsev (1):
[RISCV_PM] Implement address masking functions required for RISC-V
Pointer Masking extension
target/riscv/cpu.c | 24 +++
target/riscv/cpu.h | 32 +++
target/riscv/cpu_bits.h | 66 ++++++
target/riscv/csr.c | 264 ++++++++++++++++++++++++
target/riscv/insn_trans/trans_rva.c.inc | 3 +
target/riscv/insn_trans/trans_rvd.c.inc | 2 +
target/riscv/insn_trans/trans_rvf.c.inc | 2 +
target/riscv/insn_trans/trans_rvi.c.inc | 2 +
target/riscv/translate.c | 44 ++++
9 files changed, 439 insertions(+)
--
2.20.1
