在 2020/8/11 上午1:21, Philippe Mathieu-Daudé 写道:
On 8/6/20 11:37 PM, Philippe Mathieu-Daudé wrote:
On 8/6/20 10:51 PM, Peter Maydell wrote:
On Thu, 6 Aug 2020 at 21:31, Philippe Mathieu-Daudé <[email protected]> wrote:
On 8/6/20 8:01 PM, Jiaxun Yang wrote:
在 2020/8/6 下午8:26, Philippe Mathieu-Daudé 写道:
We only implement the Index[Store/Load]Tag from the 'cache' opcode.
Instead of ignoring the other cache operations, report them as
unimplemented.
Hmm, I don't think we have anything to do with Invalidate/Writeback etc.
opcodes
in QEMU. Why do we log this?
I'm noticed this code is run on Linux 3.3.8 (4KEc):
8880: 3082000f andi v0,a0,0xf
8884: 10800008 beqz a0,88a8
8888: 00a21021 addu v0,a1,v0
888c: 08002227 j 889c
8890: 00001821 move v1,zero
8894: bcf90000 cache 0x19,0(a3)
8898: 24630010 addiu v1,v1,16
889c: 0062302b sltu a2,v1,v0
88a0: 14c0fffc bnez a2,8894
88a4: 00833821 addu a3,a0,v1
88a8: 03e00008 jr ra
88ac: 00000000 nop
Why silently ignore the opcode is not implemented instead of logging it?
I think the question is whether the opcode is supposed to have
some behaviour which we're not implementing, or whether "no-op"
is the correct behaviour for it (which it usually is for
cache invalidate type operations; compare the way the Arm
cache ops like IC_IALLU are just ARM_CP_NOP ops).
OK now I understand better, thanks.
I haven't found useful information about this 0x19=25 opcode value.
Just to close this thread, some findings from last WE:
- I couldn't find where Linux 3.3.8 use that op
- I eventually figured out it comes from a kernel module called 'tiatm'.
- This kmod is released by OpenWRT in packages named kmod-sangam-atm-annex
- Googling for strings from the object, this file has been added in [1]
based on the file included in [2]
- Someone imported these files in a git repo and published
- There is a commented reference [4] as:
#define DataCacheHitInvalidate(a) {__asm__(" cache 17, (%0)"
: : "r" (a));}
#define DataCacheHitWriteback(a) {__asm__(" cache 25, (%0)"
: : "r" (a));}
- Also referenced (not commented) in [5] "Linux atm module implementation".
For my use I'm happy using a trace event:
-- >8 --
FYI, I took a look at MIPS M14K (interAptiv) RTL from MIPSOpen project,
HitInvalidate and HitWriteback cache Ops to L2/L3 Cache will also act
on L1 Cache. So probably that's kinda... Undocumented trick...
Thanks.
- Jiaxun
