在 2020/8/11 上午1:21, Philippe Mathieu-Daudé 写道:
On 8/6/20 11:37 PM, Philippe Mathieu-Daudé wrote:
On 8/6/20 10:51 PM, Peter Maydell wrote:
On Thu, 6 Aug 2020 at 21:31, Philippe Mathieu-Daudé <[email protected]> wrote:
On 8/6/20 8:01 PM, Jiaxun Yang wrote:
在 2020/8/6 下午8:26, Philippe Mathieu-Daudé 写道:
We only implement the Index[Store/Load]Tag from the 'cache' opcode.
Instead of ignoring the other cache operations, report them as
unimplemented.
[...]
On a r10k core it is listed as 'Hit Writeback Invalidate (D)' but here
this is a 4kEc. The address used is a SRAM shared with a embedded DSP
on the same SoC. From a RevEng PoV it is helpful to see there is a such
cache access, as I can separate better the peripheral involved.
I'm happy using a trace event instead.
Jiaxun, can you list me the list of opcodes QEMU can safely ignore from
the TCG emulation PoV? That way we can comment them in the code such:
Hi Phil,
I believe we have nothing to do with all VA Hit based invalidate,
writeback, fetch and lock,
According to MD00086-2B-MIPS32BIS-AFP, the Code (Bit[20:18]) should be
0b100 (Hit Inavlidate), 0b101(Hit Fill), 0b110 (Hit FB), 0b111 (Fetch
and Lock).
I'm unsure about what applications expected from Index based ops, so
we'd better keep a
log for them. What I can say is Linux rarely use Index based ops.
Thanks.
- Jiaxun
