On 2/28/20 8:22 AM, Peter Maydell wrote:
>> + if (ri->state == ARM_CP_STATE_AA32) {
>> + /*
>> + * Writes from aarch32 mode have more RES0 bits.
>> + * This includes TDZ, RW, E2H, and more.
>> + */
>> + valid_mask &= ~0xff80ff8c90000000ull;
>> + }
>
> Isn't bit HCR2 bit 16 (aka bit 32+16==48 here) also RES0 from AArch32 ?
Yes, and it's set in the above.
> I'm not really a fan of the hex-number here either, given we
> have HCR_* constants.
While plenty of those bits have names, many don't. Shall I simply name all of
the ones that have names, and that differ from the aa64 masking?
r~
