The ISA has a 128/64-bit division instruction.
Cc: qemu-s3...@nongnu.org
Cc: Cornelia Huck <coh...@redhat.com>
Cc: David Hildenbrand <da...@redhat.com>
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
include/fpu/softfloat-macros.h | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h
index 6d58615709..e702607b43 100644
--- a/include/fpu/softfloat-macros.h
+++ b/include/fpu/softfloat-macros.h
@@ -626,6 +626,12 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1,
uint64_t q;
asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d));
return q;
+#elif defined(__s390x__)
+ /* Need to use a TImode type to get an even register pair for DLGR. */
+ unsigned __int128 n = (unsigned __int128)n1 << 64 | n0;
+ asm("dlgr %0, %1" : "+r"(n) : "r"(d));
+ *r = n >> 64;
+ return n;
#else
uint64_t d0, d1, q0, q1, r1, r0, m;
--
2.17.1
