On 22 June 2018 at 08:56, Cédric Le Goater <[email protected]> wrote: > Hello, > > The Aspeed SoC clocks are driven by an input source clock which can > have different frequencies : 24MHz or 25MHz, and also, on the Aspeed > AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a calculation > using parameters in the H-PLL Parameter register or from a predefined > set of frequencies if the setting is strapped by hardware (Aspeed > AST2400 SoC). The other clocks of the SoC are then defined from the > H-PLL using dividers. > > We first introduce the APB clock because it drives the timer model. > This fixes a slowdown issue on the palmetto machine (AST2400) when > running Linux. The latest Linux versions take into account more > precisely the SoC settings for the clocks and the APB freq is set to > 48MHz but modeled at 24MHz by QEMU. > > Thanks, >
Applied to target-arm.next, thanks. -- PMM
