Hello, The Aspeed SoC clocks are driven by an input source clock which can have different frequencies : 24MHz or 25MHz, and also, on the Aspeed AST2400 SoC, 48MHz. The H-PLL (CPU) clock is defined from a calculation using parameters in the H-PLL Parameter register or from a predefined set of frequencies if the setting is strapped by hardware (Aspeed AST2400 SoC). The other clocks of the SoC are then defined from the H-PLL using dividers.
We first introduce the APB clock because it drives the timer model. This fixes a slowdown issue on the palmetto machine (AST2400) when running Linux. The latest Linux versions take into account more precisely the SoC settings for the clocks and the APB freq is set to 48MHz but modeled at 24MHz by QEMU. Thanks, C. Changes since v1: - fixed AST2400 HPLL calculation when CLKIN is 25MHz Cédric Le Goater (3): aspeed/scu: introduce clock frequencies aspeed: initialize the SCU controller first aspeed/timer: use the APB frequency from the SCU include/hw/misc/aspeed_scu.h | 70 ++++++++++++++++++++++++-- include/hw/timer/aspeed_timer.h | 4 ++ hw/arm/aspeed_soc.c | 42 ++++++++-------- hw/misc/aspeed_scu.c | 106 ++++++++++++++++++++++++++++++++++++++++ hw/timer/aspeed_timer.c | 19 +++++-- 5 files changed, 213 insertions(+), 28 deletions(-) -- 2.13.6
