On Thu, Jun 21, 2018 at 11:02 AM, Philippe Mathieu-Daudé <[email protected]> wrote: > Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > hw/ssi/omap_spi.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > diff --git a/hw/ssi/omap_spi.c b/hw/ssi/omap_spi.c > index 34163e5646..f278a55160 100644 > --- a/hw/ssi/omap_spi.c > +++ b/hw/ssi/omap_spi.c > @@ -20,6 +20,7 @@ > * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. > */ > #include "qemu/osdep.h" > +#include "qemu/log.h" > #include "hw/hw.h" > #include "hw/arm/omap.h" > > @@ -294,11 +295,15 @@ static void omap_mcspi_write(void *opaque, hwaddr addr, > case 0x2c: /* MCSPI_CHCONF */ > if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */ > omap_mcspi_dmarequest_update(s->ch + ch); > - if (((value >> 12) & 3) == 3) /* TRM */ > - fprintf(stderr, "%s: invalid TRM value (3)\n", __func__); > - if (((value >> 7) & 0x1f) < 3) /* WL */ > - fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n", > - __func__, (value >> 7) & 0x1f); > + if (((value >> 12) & 3) == 3) { /* TRM */ > + qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid TRM value (3)\n", > + __func__); > + } > + if (((value >> 7) & 0x1f) < 3) { /* WL */ > + qemu_log_mask(LOG_GUEST_ERROR, > + "%s: invalid WL value (%" PRIx64 ")\n", > + __func__, (value >> 7) & 0x1f); > + } > s->ch[ch].config = value & 0x7fffff; > break; > > -- > 2.18.0.rc2 > >
