Does the qemu implements cache emulation? I did see some comments saying otherwise.
Best regards, Karthik On Wed, May 25, 2016 at 5:57 PM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 25 May 2016 at 06:44, Karthik <karthikshanmu...@gmail.com> wrote: > > Hi, > > > > CPU: Cortex R5F > > > > I have this instruction that invalidates the entire data cache > > > > MCR p15, 0, r0, c15, c5, 0 > > > > > > > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460c/Chdhgibd.html > > > > This instruction generates undefined exception, and further debugging > > showed it is because the co-processor register was not implemented. > > > > To get around, I have added the below entry in the cortexr5_cp_reginfo[] > > (target-arm/cpu.c) > > > > { > > {.name = "INVALLDC", .cp=15, .opc1 = 0, .crn = 5, .opc2 = 0. > > .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_OVERRIDE}, > > } > > > > or > > > > I have to add > > set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); > > > > So, which option is recommended? > > Better to implement exactly the registers that are required; > the DUMMY_C15_REGS feature is mostly there for our older CPU > emulation because it's what we've always done, and it's a bit > tricky to move to being more specific without potentially breaking > guest code that used to work. We shouldn't be adding it to more > CPUs. > > You should check against the ARM ARM whether these cache > invalidation registers are really R5-specific, or if they're > a part of the generic PMSA architecture. If they're generic > PMSA then they should be implemented in the generic code, > enabled by a new feature flag, not in the R5-only reginfo > array. > > thanks > -- PMM >
