Hi, CPU: Cortex R5F
I have this instruction that invalidates the entire data cache MCR p15, 0, r0, c15, c5, 0 http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0460c/Chdhgibd.html This instruction generates undefined exception, and further debugging showed it is because the co-processor register was not implemented. To get around, I have added the below entry in the cortexr5_cp_reginfo[] (target-arm/cpu.c) { {.name = "INVALLDC", .cp=15, .opc1 = 0, .crn = 5, .opc2 = 0. .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_OVERRIDE}, } or I have to add set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); So, which option is recommended? Best regards, Karthik
