On 13 May 2016 at 17:41, Andrew Baumann <[email protected]> wrote: > I'm trying to use the MRS/MSR banked register instructions you > recently implemented, but found that they raised an undefined > instruction exception on the cortex-a15 CPU model. This seems to > be caused by the check in msr_banked_access_decode(), which looks > for ARM_FEATURE_V8 or ARM_FEATURE_EL2. > > The quick kludge below worked for me, but I don't have high > confidence in its correctness -- the CPU supports the virtualisation > extensions, but I've no idea whether the rest of qemu is consistent > with enabling that feature. I guess you have a better idea?
Yeah, this came up earlier this week in the context of the A53 and A57: https://lists.nongnu.org/archive/html/qemu-devel/2016-05/msg01006.html The short answer is that EL2 support isn't finished yet, and I don't want to enable the feature until we have something that's complete enough to be able to run a real guest that uses it. thanks -- PMM
