Hi Peter,
I'm trying to use the MRS/MSR banked register instructions you recently
implemented, but found that they raised an undefined instruction exception on
the cortex-a15 CPU model. This seems to be caused by the check in
msr_banked_access_decode(), which looks for ARM_FEATURE_V8 or ARM_FEATURE_EL2.
The quick kludge below worked for me, but I don't have high confidence in its
correctness -- the CPU supports the virtualisation extensions, but I've no idea
whether the rest of qemu is consistent with enabling that feature. I guess you
have a better idea?
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -1132,6 +1132,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_LPAE);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
set_feature(&cpu->env, ARM_FEATURE_EL3);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
Cheers,
Andrew