On 4/1/10, Artyom Tarasenko <atar4q...@googlemail.com> wrote: > 2010/4/1 Blue Swirl <blauwir...@gmail.com>: > > Which list? > > This mailing list? > > > > On 4/1/10, Artyom Tarasenko <atar4q...@googlemail.com> wrote: > >> and looks wrong or incomplete to me: > >> > >> >According to Sun4M System Architecture Manual chapter 5.3.2, a limit > >> >of 0 will not generate interrupts. > >> > >> This is indeed correct, but the chapter 5.3.2 also explains why: > >> > >> "Setting the limit register to 0 allows the counter to free run. Since > the > >> timer always resets to a value of 500 nS after reaching maximum count, > >> there is no match and no interrupts are generated." > >> > >> The part about 500 nS (0x00000200 in the counter register) and > >> no match seems to be not addressed. > > > > The 500ns offset part could be addressed by making the timer period > > shorter by 1 tick. I doubt such a change would have any visible > > difference with QEMU, except that tick count of 0 should never appear > > in the counter but it may now. > > > as well as all the other values between 0 and 0x200. But it's less > important I guess.
The counter tick is also 500ns, so there can't be values where any of the 9 LSBs were set. > > For the no match part, t->reached should not be set if t->limit == 0. > > > > -- > Regards, > Artyom Tarasenko > > solaris/sparc under qemu blog: http://tyom.blogspot.com/ >
