and looks wrong or incomplete to me: >According to Sun4M System Architecture Manual chapter 5.3.2, a limit >of 0 will not generate interrupts.
This is indeed correct, but the chapter 5.3.2 also explains why: "Setting the limit register to 0 allows the counter to free run. Since the timer always resets to a value of 500 nS after reaching maximum count, there is no match and no interrupts are generated." The part about 500 nS (0x00000200 in the counter register) and no match seems to be not addressed. -- Regards, Artyom Tarasenko solaris/sparc under qemu blog: http://tyom.blogspot.com/
