On 1 September 2014 19:01, Ard Biesheuvel <ard.biesheu...@linaro.org> wrote:
> On 1 September 2014 13:55, Ard Biesheuvel <ard.biesheu...@linaro.org> wrote:
>> @@ -3599,6 +3609,28 @@ void arm_cpu_do_interrupt(CPUState *cs)
>> mask = CPSR_A | CPSR_I | CPSR_F;
>> offset = 4;
>> break;
>> + case EXCP_HVC:
>> + if (arm_cpu_do_hvc(cs)) {
>> + return;
>> + }
>> + qemu_log_mask(LOG_GUEST_ERROR, "HVC not implemented on this CPU\n");
>> + goto hvc_unallocated;
>> + case EXCP_SMC:
>> + if (arm_cpu_do_smc(cs)) {
>> + return;
>> + }
>> + qemu_log_mask(LOG_GUEST_ERROR, "SMC not implemented on this CPU\n");
>> + hvc_unallocated:
>> + /* Treat as unallocated encoding */
>> + new_mode = ARM_CPU_MODE_UND;
>> + addr = 0x04;
>> + mask = CPSR_I;
>> + if (env->thumb) {
>> + offset = 2;
>> + } else {
>> + offset = 4;
>> + }
>> + break;
>
> Replying to self: I guess I forgot to set the correct ESR value here, would
> this
>
> env->cp15.esr_el[1] = syn_uncategorized();
>
> be sufficient?
That's not necessary in the AArch32 do_interrupt code:
AArch32 doesn't have a syndrome register, and the
esr_el[1] holds the AArch32 DFSR value. DFSR isn't
set on UNDEF exceptions, so we should leave esr_el[1]
unchanged.
thanks
-- PMM
