On Thu, 5 Mar 2026 at 10:39, Kuan-Jui Chiu <[email protected]> wrote: > > This patch seriers add a new model for Cadence GPIO controller which > supports 32 pins and interrupts for level-triggered/edge-triggered type on > input pins. > > Also define new trace functions for analysis purpose and new configuration to > enable this model. > > Kuan-Jui Chiu (1): > hw/gpio: Add Cadence GPIO model > > hw/gpio/Kconfig | 3 + > hw/gpio/cadence_gpio.c | 312 +++++++++++++++++++++++++++++++++ > hw/gpio/meson.build | 1 + > hw/gpio/trace-events | 5 + > include/hw/gpio/cadence_gpio.h | 66 +++++++ > 5 files changed, 387 insertions(+)
Hi; this patch adds a new TYPE_SYSBUS (memory-mapped) device, but it doesn't add that new device to any board models, so this is dead code, as it stands. What's the intended user? Generally we recommend adding new devices to QEMU along with the machine/SoC/whatever that uses them. thanks -- PMM
