On 3/4/2026 12:09 PM, Jay Chang wrote:
Signed-off-by: Jay Chang <[email protected]>
Reviewed-by: Frank Chang <[email protected]>
---
hw/riscv/riscv-iommu-bits.h | 1 +
hw/riscv/riscv-iommu.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h
index 47fe01bee5..a938fd3eb4 100644
--- a/hw/riscv/riscv-iommu-bits.h
+++ b/hw/riscv/riscv-iommu-bits.h
@@ -189,6 +189,7 @@ enum riscv_iommu_ddtp_modes {
#define RISCV_IOMMU_REG_IPSR 0x0054
#define RISCV_IOMMU_IPSR_CIP BIT(0)
#define RISCV_IOMMU_IPSR_FIP BIT(1)
+#define RISCV_IOMMU_IPSR_PMIP BIT(2)
#define RISCV_IOMMU_IPSR_PIP BIT(3)
enum {
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 98345b1280..610cdebac2 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2153,6 +2153,10 @@ static void riscv_iommu_update_ipsr(RISCVIOMMUState *s,
uint64_t data)
ipsr_clr |= RISCV_IOMMU_IPSR_FIP;
}
+ if (!(data & RISCV_IOMMU_IPSR_PMIP)) {
+ ipsr_clr |= RISCV_IOMMU_IPSR_PMIP;
+ }
+
According to the following description of 'pmip' in the specification:
"The performance-monitoring-interrupt-pending is set to 1 when OF bit
iniohpmcycles or in any of the iohpmctr1-31 registers transitions
from 0 to 1."
Would it be better to handle like the following ?
if (data & RISCV_IOMMU_IPSR_PMIP) {
ipsr_set ...
} else {
ipsr_clr ...
}
Otherwise,
Reviewed-by: Nutty Liu <[email protected]>
Thanks,
Nutty
if (data & RISCV_IOMMU_IPSR_PIP) {
pqcsr = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_PQCSR);
