This series contains two fixes for the RISC-V IOMMU implementation: 1. Fix a bug in the HPM (Hardware Performance Monitor) timer setup where irq_overflow_left was not properly reset, causing stale values from previous timer setups to affect new timer behavior.
2. Add proper RW1C (Read/Write 1 to Clear) support for the IPSR.PMIP (Performance Monitor Interrupt Pending) bit, which was missing from the IPSR register implementation. Jay Chang (2): hw/riscv/riscv-iommu-hpm: Fix irq_overflow_left residual value bug hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support hw/riscv/riscv-iommu-bits.h | 1 + hw/riscv/riscv-iommu-hpm.c | 1 + hw/riscv/riscv-iommu.c | 4 ++++ 3 files changed, 6 insertions(+) -- 2.48.1
