On 3/2/2026 5:21 PM, Sairaj Kodilkar wrote:
> When MMIO 0x18[IntCapXTEn]=1, interrupts originating from the IOMMU itself are
> sent based on the programming in XT IOMMU Interrupt Control Registers in MMIO
> 0x170-0x180 instead of the programming in the IOMMU's MSI capability
> registers.
> The guest programs these registers with appropriate vector and destination
> ID instead of writing to PCI MSI capability.
>
> Current AMD vIOMMU is capable of generating interrupts only through PCI
> MSI capability and does not care about xt mode. Because of this AMD
> vIOMMU cannot generate event log interrupts when the guest has enabled
> xt mode.
>
> Introduce a new flag "intcapxten" which is set when guest writes control
> register [IntCapXTEn] (bit 51) and use vector and destination field in
> the XT MMIO register (0x170) to support XT mode.
>
> Signed-off-by: Sairaj Kodilkar <[email protected]>
> Reviewed-by: Vasant Hegde <[email protected]>
> Reviewed-by: Alejandro Jimenez <[email protected]>
> ---
> hw/i386/amd_iommu.c | 47 ++++++++++++++++++++++++++++++++++++++------
> hw/i386/amd_iommu.h | 17 ++++++++++++++++
> hw/i386/trace-events | 1 +
> 3 files changed, 59 insertions(+), 6 deletions(-)
>
.../...
>
> /* update the flags depending on the control register */
> if (s->cmdbuf_enabled) {
> @@ -1732,6 +1762,9 @@ static void amdvi_mmio_write(void *opaque, hwaddr addr,
> uint64_t val,
> case AMDVI_MMIO_STATUS:
> amdvi_mmio_reg_write(s, size, val, addr);
> break;
> + case AMDVI_MMIO_XT_GEN_INTR:
> + amdvi_mmio_reg_write(s, size, val, addr);
> + break;
> }
> }
>
> @@ -2382,6 +2415,7 @@ static void amdvi_init(AMDVIState *s)
> s->enabled = false;
> s->cmdbuf_enabled = false;
> s->xten = false;
> + s->intcapxten = false;
>
> /* reset MMIO */
> memset(s->mmior, 0, AMDVI_MMIO_SIZE);
> @@ -2452,6 +2486,7 @@ static const VMStateDescription vmstate_xt = {
> .minimum_version_id = 1,
> .fields = (VMStateField[]) {
> VMSTATE_BOOL(xten, AMDVIState),
> + VMSTATE_BOOL(intcapxten, AMDVIState),
Do we need to increase the version no?
-Vasant
