This makes it easier to add new MMIO registers for tracing and removes the unnecessary complexity introduced by amdvi_mmio_(low/high) array.
Signed-off-by: Sairaj Kodilkar <[email protected]> Reviewed-by: Vasant Hegde <[email protected]> Reviewed-by: Alejandro Jimenez <[email protected]> --- hw/i386/amd_iommu.c | 76 ++++++++++++++++----------------------------- hw/i386/amd_iommu.h | 4 --- 2 files changed, 27 insertions(+), 53 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index 789e09d6f2bc..f5aa9c763d02 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -35,29 +35,6 @@ #include "kvm/kvm_i386.h" #include "qemu/iova-tree.h" -/* used AMD-Vi MMIO registers */ -const char *amdvi_mmio_low[] = { - "AMDVI_MMIO_DEVTAB_BASE", - "AMDVI_MMIO_CMDBUF_BASE", - "AMDVI_MMIO_EVTLOG_BASE", - "AMDVI_MMIO_CONTROL", - "AMDVI_MMIO_EXCL_BASE", - "AMDVI_MMIO_EXCL_LIMIT", - "AMDVI_MMIO_EXT_FEATURES", - "AMDVI_MMIO_PPR_BASE", - "UNHANDLED" -}; -const char *amdvi_mmio_high[] = { - "AMDVI_MMIO_COMMAND_HEAD", - "AMDVI_MMIO_COMMAND_TAIL", - "AMDVI_MMIO_EVTLOG_HEAD", - "AMDVI_MMIO_EVTLOG_TAIL", - "AMDVI_MMIO_STATUS", - "AMDVI_MMIO_PPR_HEAD", - "AMDVI_MMIO_PPR_TAIL", - "UNHANDLED" -}; - struct AMDVIAddressSpace { PCIBus *bus; /* PCIBus (for bus number) */ uint8_t devfn; /* device function */ @@ -1484,31 +1461,31 @@ static void amdvi_cmdbuf_run(AMDVIState *s) } } -static inline uint8_t amdvi_mmio_get_index(hwaddr addr) -{ - uint8_t index = (addr & ~0x2000) / 8; - - if ((addr & 0x2000)) { - /* high table */ - index = index >= AMDVI_MMIO_REGS_HIGH ? AMDVI_MMIO_REGS_HIGH : index; - } else { - index = index >= AMDVI_MMIO_REGS_LOW ? AMDVI_MMIO_REGS_LOW : index; +static inline +const char *amdvi_mmio_get_name(hwaddr addr) +{ + /* Return MMIO names as string literals */ + switch (addr) { +#define MMIO_REG_TO_STRING(mmio_reg) case mmio_reg: return #mmio_reg + MMIO_REG_TO_STRING(AMDVI_MMIO_DEVICE_TABLE); + MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_BASE); + MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_BASE); + MMIO_REG_TO_STRING(AMDVI_MMIO_CONTROL); + MMIO_REG_TO_STRING(AMDVI_MMIO_EXCL_BASE); + MMIO_REG_TO_STRING(AMDVI_MMIO_EXCL_LIMIT); + MMIO_REG_TO_STRING(AMDVI_MMIO_EXT_FEATURES); + MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_HEAD); + MMIO_REG_TO_STRING(AMDVI_MMIO_COMMAND_TAIL); + MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_HEAD); + MMIO_REG_TO_STRING(AMDVI_MMIO_EVENT_TAIL); + MMIO_REG_TO_STRING(AMDVI_MMIO_STATUS); + MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_BASE); + MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_HEAD); + MMIO_REG_TO_STRING(AMDVI_MMIO_PPR_TAIL); +#undef MMIO_REG_TO_STRING + default: + return "UNHANDLED"; } - - return index; -} - -static void amdvi_mmio_trace_read(hwaddr addr, unsigned size) -{ - uint8_t index = amdvi_mmio_get_index(addr); - trace_amdvi_mmio_read(amdvi_mmio_low[index], addr, size, addr & ~0x07); -} - -static void amdvi_mmio_trace_write(hwaddr addr, unsigned size, uint64_t val) -{ - uint8_t index = amdvi_mmio_get_index(addr); - trace_amdvi_mmio_write(amdvi_mmio_low[index], addr, size, val, - addr & ~0x07); } static uint64_t amdvi_mmio_read(void *opaque, hwaddr addr, unsigned size) @@ -1528,7 +1505,7 @@ static uint64_t amdvi_mmio_read(void *opaque, hwaddr addr, unsigned size) } else if (size == 8) { val = amdvi_readq(s, addr); } - amdvi_mmio_trace_read(addr, size); + trace_amdvi_mmio_read(amdvi_mmio_get_name(addr), addr, size, addr & ~0x07); return val; } @@ -1684,7 +1661,8 @@ static void amdvi_mmio_write(void *opaque, hwaddr addr, uint64_t val, return; } - amdvi_mmio_trace_write(addr, size, val); + trace_amdvi_mmio_write(amdvi_mmio_get_name(addr), addr, size, val, offset); + switch (addr & ~0x07) { case AMDVI_MMIO_CONTROL: amdvi_mmio_reg_write(s, size, val, addr); diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 302ccca5121f..ca4ff9fffee3 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -45,10 +45,6 @@ #define AMDVI_CAPAB_FLAG_IOTLBSUP (1 << 24) #define AMDVI_CAPAB_INIT_TYPE (3 << 16) -/* No. of used MMIO registers */ -#define AMDVI_MMIO_REGS_HIGH 7 -#define AMDVI_MMIO_REGS_LOW 8 - /* MMIO registers */ #define AMDVI_MMIO_DEVICE_TABLE 0x0000 #define AMDVI_MMIO_COMMAND_BASE 0x0008 -- 2.34.1
