Have the CPUClass::disas_set_info() handler take a const CPUState to be sure it is not modified. In order to do that, first constify few callees (ARM & RISCV).
Philippe Mathieu-Daudé (7): target/arm: Have arm_feature() take a const @env argument target/arm: Have cpu_isar_feature() use a const ARMCPU object target/arm: Have is_64() take a const @env argument target/arm: Have arm_sctlr_b() take a const @env argument disas/riscv: Make rv_decode::cfg const disas: Make disassemble_info::target_info field const disas: Have disas_set_info() take a const CPUState disas/riscv.h | 2 +- include/disas/dis-asm.h | 2 +- include/hw/core/cpu.h | 2 +- target/arm/cpu-features.h | 2 +- target/arm/cpu.h | 6 +++--- disas/riscv.c | 5 +++-- target/alpha/cpu.c | 3 ++- target/arm/cpu.c | 6 +++--- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 3 ++- target/hppa/cpu.c | 2 +- target/i386/cpu.c | 6 +++--- target/loongarch/cpu.c | 3 ++- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 7 +++++-- target/openrisc/cpu.c | 2 +- target/ppc/cpu_init.c | 5 +++-- target/riscv/cpu.c | 7 ++++--- target/rx/cpu.c | 2 +- target/s390x/cpu.c | 2 +- target/sh4/cpu.c | 3 ++- target/sparc/cpu.c | 3 ++- target/xtensa/cpu.c | 3 ++- 24 files changed, 47 insertions(+), 35 deletions(-) -- 2.52.0
