Chao Liu <[email protected]> writes:
> Add a qtest suite for the RISC-V IOMMU PCI device on the virt machine.
> The test exercises bare, S-stage, G-stage, and nested translation paths
> using iommu-testdev and the qos-riscv-iommu helpers.
>
> The test validates:
> - Device context (DC) configuration
> - SV39 page table walks for S-stage translation
> - SV39x4 page table walks for G-stage translation
> - Nested translation combining both stages
> - FCTL register constraints
>
> This provides regression coverage for the RISC-V IOMMU implementation
> without requiring a full guest OS boot.
>
> Signed-off-by: Chao Liu <[email protected]>
...
> +static bool riscv_iommu_test_setup(RiscvIommuTestState *state)
> +{
> + if (!qtest_has_machine("virt")) {
> + g_test_skip("virt machine not available");
> + return false;
> + }
> +
> + state->qts = qtest_init("-machine virt,acpi=off "
> + "-cpu max -smp 1 -m 512 -net none "
> + "-device riscv-iommu-pci "
> + "-device iommu-testdev");
> +
> + qpci_init_generic(&state->gbus, state->qts, NULL, false);
> + riscv_config_qpci_bus(&state->gbus);
> +
> + state->iommu_dev = find_riscv_iommu_pci(&state->gbus,
> &state->iommu_base);
> + g_assert(state->iommu_dev);
> +
> + state->testdev = find_iommu_testdev(&state->gbus, &state->testdev_bar);
> + g_assert(state->testdev);
> +
These two will leak. Otherwise, looks good.
Reviewed-by: Fabiano Rosas <[email protected]>
