Hi Zhao,
On 07-01-2026 12:55, Zhao Liu wrote:
> Hi Shivansh,
>
> Sorry for late reply.
>
> On Fri, Nov 21, 2025 at 08:34:48AM +0000, Shivansh Dhiman wrote:
>> Date: Fri, 21 Nov 2025 08:34:48 +0000
>> From: Shivansh Dhiman <[email protected]>
>> Subject: [PATCH 1/5] i386: Implement CPUID 0x80000026
>> X-Mailer: git-send-email 2.43.0
>>
>> Implement CPUID leaf 0x80000026 (AMD Extended CPU Topology). It presents the
>> complete topology information to guests via a single CPUID with multiple
>> subleafs, each describing a specific hierarchy level, viz. core, complex,
>> die, socket.
>>
>> Note that complex/CCX level relates to "die" in QEMU, and die/CCD level is
>> not supported in QEMU yet. Hence, use CCX at CCD level until diegroups are
>> implemented.
>
> I'm trying to understand AMD's topology hierarchy by comparing it to the
> kernel's arch/x86/kernel/cpu/topology_ext.c file:
>
> static const unsigned int topo_domain_map_0b_1f[MAX_TYPE_1F] = {
> [SMT_TYPE] = TOPO_SMT_DOMAIN,
> [CORE_TYPE] = TOPO_CORE_DOMAIN,
> [MODULE_TYPE] = TOPO_MODULE_DOMAIN,
> [TILE_TYPE] = TOPO_TILE_DOMAIN,
> [DIE_TYPE] = TOPO_DIE_DOMAIN,
> [DIEGRP_TYPE] = TOPO_DIEGRP_DOMAIN,
> };
>
> static const unsigned int topo_domain_map_80000026[MAX_TYPE_80000026] = {
> [SMT_TYPE] = TOPO_SMT_DOMAIN,
> [CORE_TYPE] = TOPO_CORE_DOMAIN,
> [AMD_CCD_TYPE] = TOPO_TILE_DOMAIN,
> [AMD_SOCKET_TYPE] = TOPO_DIE_DOMAIN,
> };
These mappings reuse some original names (SMT_TYPE and CORE_TYPE) along with the
new ones (AMD_CCD_TYPE and AMD_SOCKET_TYPE). I think to avoid defining more AMD
specific types the original names are used. So, essentially you can read them
like this:
static const unsigned int topo_domain_map_80000026[MAX_TYPE_80000026] = {
[AMD_CORE_TYPE] = TOPO_SMT_DOMAIN,
[AMD_CCX_TYPE] = TOPO_CORE_DOMAIN,
[AMD_CCD_TYPE] = TOPO_TILE_DOMAIN,
[AMD_SOCKET_TYPE] = TOPO_DIE_DOMAIN,
};
>
> What particularly puzzles me is that "complex" isn't listed here, yet it
> should be positioned between "core" and CCD. Does this mean complex
> actually corresponds to kernel's module domain?
There is a nuance with CPUID 80000026h related to the shifting of x2APIC ID.
According to APM, EAX[4:0] tells us the number of bits to shift x2APIC ID right
to get unique topology ID of the next instance of the current level type.
So, all logical processors with the same next level ID share current level. This
results in mapping the Nth level type to (N-1)th domain. This is unlike Intel's
CPUID 0xb which maps Nth level type to Nth domain.
Back to your question, the complex is same as tile since both represent a L3
cache boundary.
>
> Back to QEMU, now CCX is mapped as QEMU's die level, and AMD socket is mapped
> to socket level. Should we revisit QEMU's topology level mapping for AMD, to
> align with the above topology domain mapping?
>
> If we want to go further: supporting CCD configuration would be quite
> tricky. I feel that adding another new parameter between the smp.dies
> and smp.sockets would create significant confusion.
The current kernel doesn't have sensitivity to a level between L3 boundary and
socket. Also, most production systems in current AMD CPU landscape have CCD=CCX.
Only a handful of models feature CCD=2CCX, so this isn't an immediate pressing
need.
In QEMU's terminology, socket represents an actual socket and die represents the
L3 cache boundary. There is no intermediate level between them. Looking ahead,
when more granular topology information (like CCD) becomes necessary for VMs,
introducing a "diegroup" level would be the logical approach. This level would
fit naturally between die and socket, as its role cannot be fulfilled by
existing topology levels.
Also, I was looking at Intel's SDM Vol. 2A "Instruction Set Reference, A-Z"
Table 3-8. "Information Returned by CPUID Instruction". The presence of a
"diegrp" level between die and socket suggests Intel has already recognized the
need for this intermediate topology level. If this maps to a similar concept as
AMD's CCD, it would indeed strengthen the case for introducing a new level in
QEMU.
>
>> Signed-off-by: Shivansh Dhiman <[email protected]>
>> ---
>> target/i386/cpu.c | 76 +++++++++++++++++++++++++++++++++++++++++++
>> target/i386/kvm/kvm.c | 17 ++++++++++
>> 2 files changed, 93 insertions(+)
>>
>> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
>> index 641777578637..b7827e448aa5 100644
>> --- a/target/i386/cpu.c
>> +++ b/target/i386/cpu.c
>> @@ -495,6 +495,78 @@ static void encode_topo_cpuid1f(CPUX86State *env,
>> uint32_t count,
>> assert(!(*eax & ~0x1f));
>> }
>>
>> +/*
>> + * CPUID_Fn80000026: Extended CPU Topology
>> + *
>> + * EAX Bits Description
>> + * 31:5 Reserved
>> + * 4:0 Number of bits to shift Extended APIC ID right to get a unique
>> + * topology ID of the current hierarchy level.
>> + *
>> + * EBX Bits Description
>> + * 31:16 Reserved
>> + * 15:0 Number of logical processors at the current hierarchy level.
>> + *
>> + * ECX Bits Description
>> + * 31:16 Reserved
>> + * 15:8 Level Type. Values:
>> + * Value Description
>> + * 0h Reserved
>> + * 1h Core
>> + * 2h Complex
>> + * 3h Die
>> + * 4h Socket
>> + * FFh-05h Reserved
>> + * 7:0 Input ECX
>> + *
>> + * EDX Bits Description
>> + * 31:0 Extended APIC ID of the logical processor
>> + */
>
> I feel this long comment is not necessary, since people could check APM for
> details. Or this description could be included in commit message.
Sure. Will do. Thanks.
>
>> +static void encode_topo_cpuid80000026(CPUX86State *env, uint32_t count,
>> + X86CPUTopoInfo *topo_info,
>> + uint32_t *eax, uint32_t *ebx,
>> + uint32_t *ecx, uint32_t *edx)
>
> Regards,
> Zhao
>
