On Tue, Sep 30, 2025 at 01:57:18PM +0200, Clément Chigot wrote: > From: Frederic Konrad <[email protected]> > > This wires a second GIC for the Cortex-R5, all the IRQs are split when there > is an RPU instanciated. > > Signed-off-by: Clément Chigot <[email protected]>
Acked-by: Edgar E. Iglesias <[email protected]> > --- > hw/arm/xlnx-zynqmp.c | 77 +++++++++++++++++++++++++++++++++++- > include/hw/arm/xlnx-zynqmp.h | 4 ++ > 2 files changed, 80 insertions(+), 1 deletion(-) > > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index 3d8c46986e..ffed6e5126 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -384,6 +384,7 @@ static void xlnx_zynqmp_init(Object *obj) > XlnxZynqMPState *s = XLNX_ZYNQMP(obj); > int i; > int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); > + int num_rpus = xlnx_zynqmp_get_rpu_number(ms); > > object_initialize_child(obj, "apu-cluster", &s->apu_cluster, > TYPE_CPU_CLUSTER); > @@ -397,6 +398,12 @@ static void xlnx_zynqmp_init(Object *obj) > > object_initialize_child(obj, "gic", &s->gic, gic_class_name()); > > + if (num_rpus) { > + /* Do not create the rpu_gic if we don't have rpus */ > + object_initialize_child(obj, "rpu_gic", &s->rpu_gic, > + gic_class_name()); > + } > + > for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { > object_initialize_child(obj, "gem[*]", &s->gem[i], TYPE_CADENCE_GEM); > object_initialize_child(obj, "gem-irq-orgate[*]", > @@ -446,6 +453,15 @@ static void xlnx_zynqmp_init(Object *obj) > object_initialize_child(obj, "qspi-irq-orgate", > &s->qspi_irq_orgate, TYPE_OR_IRQ); > > + if (num_rpus) { > + for (i = 0; i < ARRAY_SIZE(s->splitter); i++) { > + g_autofree char *name = g_strdup_printf("irq-splitter%d", i); > + object_initialize_child(obj, name, &s->splitter[i], > TYPE_SPLIT_IRQ); > + } > + } > + > + > + > for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) { > object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3); > } > @@ -459,6 +475,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error > **errp) > uint8_t i; > uint64_t ram_size; > int num_apus = MIN(ms->smp.cpus, XLNX_ZYNQMP_NUM_APU_CPUS); > + int num_rpus = xlnx_zynqmp_get_rpu_number(ms); > const char *boot_cpu = s->boot_cpu ? s->boot_cpu : "apu-cpu[0]"; > ram_addr_t ddr_low_size, ddr_high_size; > qemu_irq gic_spi[XLNX_ZYNQMP_GIC_NUM_SPI_INTR]; > @@ -517,6 +534,14 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error > **errp) > qdev_prop_set_bit(DEVICE(&s->gic), > "has-virtualization-extensions", s->virt); > > + if (num_rpus) { > + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-irq", > + XLNX_ZYNQMP_GIC_NUM_SPI_INTR + 32); > + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "revision", 1); > + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "num-cpu", num_rpus); > + qdev_prop_set_uint32(DEVICE(&s->rpu_gic), "first-cpu-index", 4); > + } > + > qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); > > /* Realize APUs before realizing the GIC. KVM requires this. */ > @@ -616,13 +641,63 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error > **errp) > return; > } > > + if (num_rpus) { > + if (!sysbus_realize(SYS_BUS_DEVICE(&s->rpu_gic), errp)) { > + return; > + } > + > + for (i = 0; i < num_rpus; i++) { > + qemu_irq irq; > + > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), i + 1, > + GIC_BASE_ADDR + i * 0x1000); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i, > + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), > + ARM_CPU_IRQ)); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus, > + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), > + ARM_CPU_FIQ)); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus * 2, > + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), > + ARM_CPU_VIRQ)); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rpu_gic), i + num_rpus * 3, > + qdev_get_gpio_in(DEVICE(&s->rpu_cpu[i]), > + ARM_CPU_VFIQ)); > + irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic), > + arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); > + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_PHYS, irq); > + irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic), > + arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); > + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_VIRT, irq); > + irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic), > + arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); > + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_HYP, irq); > + irq = qdev_get_gpio_in(DEVICE(&s->rpu_gic), > + arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); > + qdev_connect_gpio_out(DEVICE(&s->rpu_cpu[i]), GTIMER_SEC, irq); > + } > + > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->rpu_gic), 0, GIC_BASE_ADDR); > + } > + > if (!s->boot_cpu_ptr) { > error_setg(errp, "ZynqMP Boot cpu %s not found", boot_cpu); > return; > } > > for (i = 0; i < XLNX_ZYNQMP_GIC_NUM_SPI_INTR; i++) { > - gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); > + if (num_rpus) { > + DeviceState *splitter = DEVICE(&s->splitter[i]); > + qdev_prop_set_uint16(splitter, "num-lines", 2); > + qdev_realize(splitter, NULL, &error_abort); > + gic_spi[i] = qdev_get_gpio_in(splitter, 0); > + qdev_connect_gpio_out(splitter, 0, > + qdev_get_gpio_in(DEVICE(&s->gic), i)); > + qdev_connect_gpio_out(splitter, 1, > + qdev_get_gpio_in(DEVICE(&s->rpu_gic), i)); > + } else { > + gic_spi[i] = qdev_get_gpio_in(DEVICE(&s->gic), i); > + } > } > > for (i = 0; i < XLNX_ZYNQMP_NUM_GEMS; i++) { > diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h > index 6a407c2962..a3117bd6c5 100644 > --- a/include/hw/arm/xlnx-zynqmp.h > +++ b/include/hw/arm/xlnx-zynqmp.h > @@ -42,6 +42,7 @@ > #include "hw/misc/xlnx-zynqmp-crf.h" > #include "hw/timer/cadence_ttc.h" > #include "hw/usb/hcd-dwc3.h" > +#include "hw/core/split-irq.h" > > #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" > OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) > @@ -106,6 +107,9 @@ struct XlnxZynqMPState { > GICState gic; > MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; > > + GICState rpu_gic; > + SplitIRQ splitter[XLNX_ZYNQMP_GIC_NUM_SPI_INTR]; > + > MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; > > MemoryRegion *ddr_ram; > -- > 2.34.1 >
