On 9/25/25 19:30, Aditya Gupta wrote:
Overview ============Add support for Power11 powernv machine type. As Power11 core is same as Power10, hence much of the code has been reused from Power10. Power11 PSeries already added in QEMU in: commit 273db89bcaf4 ("ppc/pseries: Add Power11 cpu type") Git Tree for Testing ==================== QEMU: https://github.com/adi-g15-ibm/qemu/tree/p11-powernv-v10 The patches apply cleanly on below commit: 95b9e0d2ade5 ("Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging") Tests ran: * `make check` * '-M powernv' / '-M powernv10' / '-M powernv11' * '-smp' option tested * 'e1000e' device * tested changing irq affinities to remote chips for xive functionality * compile test with --without-default-devices
Did you run 'make check-functional' ? This config looks fine : Architecture: ppc64le Byte Order: Little Endian CPU(s): 16 On-line CPU(s) list: 0-15 Model name: Power11, altivec supported Model: 18.0 (pvr 0082 1200) <-- is that a bug ? Thread(s) per core: 4 Core(s) per socket: 2 Socket(s): 2 Frequency boost: enabled CPU(s) scaling MHz: 64% CPU max MHz: 3800.0000 CPU min MHz: 2000.0000 Caches (sum of all): L1d: 128 KiB (4 instances) L1i: 128 KiB (4 instances) NUMA: NUMA node(s): 2 NUMA node0 CPU(s): 0-7 NUMA node1 CPU(s): 8-15 Tested-by: Cédric Le Goater <[email protected]> Thanks, C.
skiboot with Power11 support: https://github.com/open-power/skiboot, since commit 785a5e3 Linux with Power11 support: https://github.com/torvalds/linux, since v6.9-rc1 Changelog ========= v10: + [PATCH 1/8]: Do same change for Power11 as done for Power10 in commit 46d03b, as changes required for successful build with --without-default-devices + [PATCH 3/8]: Added new patch to remove assuming chip as Power10 in xive2 + rebase to upstream v9 (https://lore.kernel.org/qemu-devel/[email protected]/): + [PATCH 1/7]: apply hunks from commit cf0eb929e59cb, and commit 24c8fa968a6d8, for changes that were done for Power10, as those changes make sense for Power11 also + [PATCH 3/7]: fixed build breakage identified with QEMU CI, due to changes in upstream function pointer types v8 (https://lore.kernel.org/qemu-devel/[email protected]/): + rebase to upstream + propose myself as a powernv reviewer v7 (https://lore.kernel.org/qemu-devel/[email protected]/): + use Power10 models of homer, sbe, occ, psi, lpc. As they are same. + switch powernv tests to use buildroot images instead of op-build images + add functional test for powernv11 - remove dynamic sysbus device for PHBs, so no more dynamic number of PHBs in Power11 as it became complex to handle it and not much used v6 (https://lore.kernel.org/qemu-devel/[email protected]/): + make Pnv11Chip's parent as PnvChip, instead of Pnv10Chip + rebase on upstream/master v5 (https://lore.kernel.org/qemu-devel/[email protected]/): + add chiptod + add instance_init for P11 to use P11 models + move patch introducing Pnv11Chip to the last + update skiboot.lid to skiboot's upstream/master v4: + patch #5: fix memory leak in pnv_chip_power10_quad_realize - no change in other patches v3: + patch #1: version power11 as power11_v2.0 + patch #2: split target hw/pseries code into patch #2 + patch #3,#4: fix regression due to Power10 and Power11 having same PCR + patch #5: create pnv_chip_power11_dt_populate and split pnv_chip_power10_common_realize as per review + patch #6-#11: no change - remove commit to make Power11 as default v2: + split powernv patch into homer,lpc,occ,psi,sbe + reduce code duplication by reusing power10 code + make power11 as default + rebase on qemu upstream/master + add more information in commit descriptions + update docs + update skiboot.lid Aditya Gupta (8): ppc/pnv: Introduce Pnv11Chip ppc/pnv: Introduce Power11 PowerNV machine ppc/pnv: Add PnvChipClass handler to get reference to interrupt controller ppc/pnv: Add XIVE2 controller to Power11 ppc/pnv: Add PHB5 PCIe Host bridge to Power11 ppc/pnv: Add ChipTOD model for Power11 tests/powernv: Switch to buildroot images instead of op-build tests/powernv: Add PowerNV test for Power11 docs/system/ppc/powernv.rst | 9 +- hw/intc/pnv_xive2.c | 4 +- hw/ppc/pnv.c | 560 +++++++++++++++++++++++++ hw/ppc/pnv_chiptod.c | 59 +++ hw/ppc/pnv_core.c | 17 + include/hw/ppc/pnv.h | 38 ++ include/hw/ppc/pnv_chip.h | 8 + include/hw/ppc/pnv_chiptod.h | 2 + include/hw/ppc/pnv_xscom.h | 49 +++ tests/functional/ppc64/test_powernv.py | 34 +- 10 files changed, 760 insertions(+), 20 deletions(-)
